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{
    "id": 45254,
    "url": "http://patches.dpdk.org/api/patches/45254/",
    "web_url": "http://patches.dpdk.org/patch/45254/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20180924231721.15799-7-yskoh@mellanox.com>",
    "date": "2018-09-24T23:17:45",
    "name": "[v3,06/11] net/mlx5: add Direct Verbs prepare function",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "c1ca053f6cce27371e3cd41a256dcbd11fdf6f93",
    "submitter": {
        "id": 636,
        "url": "http://patches.dpdk.org/api/people/636/",
        "name": "Yongseok Koh",
        "email": "yskoh@mellanox.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/patch/45254/mbox/",
    "series": [
        {
            "id": 1476,
            "url": "http://patches.dpdk.org/api/series/1476/",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1476",
            "date": "2018-09-24T23:17:33",
            "name": "net/mlx5: add Direct Verbs flow driver support",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/1476/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/45254/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/45254/checks/",
    "tags": {},
    "headers": {
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        "References": "<20180919072143.23211-1-yskoh@mellanox.com>\n\t<20180924231721.15799-1-yskoh@mellanox.com>",
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        "CC": "\"dev@dpdk.org\" <dev@dpdk.org>, Ori Kam <orika@mellanox.com>",
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        "To": "Thomas Monjalon <thomas@monjalon.net>,\n\tShahaf Shuler <shahafs@mellanox.com>",
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        "Date": "Mon, 24 Sep 2018 23:17:45 +0000",
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        "From": "Yongseok Koh <yskoh@mellanox.com>",
        "Thread-Topic": "[PATCH v3 06/11] net/mlx5: add Direct Verbs prepare function",
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        "Subject": "[dpdk-dev] [PATCH v3 06/11] net/mlx5: add Direct Verbs prepare\n\tfunction"
    },
    "content": "From: Ori Kam <orika@mellanox.com>\n\nThis function allocates the Direct Verbs device flow, and\nintroduce the relevant PRM structures.\n\nThis commit also adds the matcher object. The matcher object acts as a\nmask and should be shared between flows. For example all rules that\nshould match source IP with full mask should use the same matcher. A\nflow that should match dest IP or source IP but without full mask should\nhave a new matcher allocated.\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\nAcked-by: Yongseok Koh <yskoh@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h         |   1 +\n drivers/net/mlx5/mlx5_flow.h    |  31 +++++-\n drivers/net/mlx5/mlx5_flow_dv.c |  45 ++++++++-\n drivers/net/mlx5/mlx5_prm.h     | 213 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_rxtx.h    |   7 ++\n 5 files changed, 295 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 4d3e9f38f..8ff6d6987 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -213,6 +213,7 @@ struct priv {\n \tLIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */\n \t/* Verbs Indirection tables. */\n \tLIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;\n+\tLIST_HEAD(matcher, mlx5_cache) matchers;\n \tuint32_t link_speed_capa; /* Link speed capabilities. */\n \tstruct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */\n \tint primary_socket; /* Unix socket for primary process. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 9b0cd28ae..0cf496db3 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -106,6 +106,34 @@\n /* Max number of actions per DV flow. */\n #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8\n \n+/* Matcher PRM representation */\n+struct mlx5_flow_dv_match_params {\n+\tsize_t size;\n+\t/**< Size of match value. Do NOT split size and key! */\n+\tuint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];\n+\t/**< Matcher value. This value is used as the mask or as a key. */\n+};\n+\n+/* Matcher structure. */\n+struct mlx5_flow_dv_matcher {\n+\tstruct mlx5_cache cache; /**< Cache to struct mlx5dv_flow_matcher. */\n+\tuint16_t crc; /**< CRC of key. */\n+\tuint16_t priority; /**< Priority of matcher. */\n+\tuint8_t egress; /**< Egress matcher. */\n+\tstruct mlx5_flow_dv_match_params mask; /**< Matcher mask. */\n+};\n+\n+/* DV flows structure. */\n+struct mlx5_flow_dv {\n+\tuint64_t hash_fields; /**< Fields that participate in the hash. */\n+\tstruct mlx5_hrxq *hrxq; /**< Hash Rx queues. */\n+\t/* Flow DV api: */\n+\tstruct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */\n+\tstruct mlx5_flow_dv_match_params value;\n+\t/**< Holds the value that the packet is compared to. */\n+\tstruct ibv_flow *flow; /**< Installed flow. */\n+};\n+\n /* Verbs specification header. */\n struct ibv_spec_header {\n \tenum ibv_flow_spec_type type;\n@@ -132,7 +160,8 @@ struct mlx5_flow {\n \tstruct rte_flow *flow; /**< Pointer to the main flow. */\n \tuint32_t layers; /**< Bit-fields that holds the detected layers. */\n \tunion {\n-\t\tstruct mlx5_flow_verbs verbs; /**< Holds the verbs dev-flow. */\n+\t\tstruct mlx5_flow_dv dv;\n+\t\tstruct mlx5_flow_verbs verbs;\n \t};\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 86a8b3cd0..30d501a61 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -291,6 +291,49 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n }\n \n /**\n+ * Internal preparation function. Allocates the DV flow size,\n+ * this size is constant.\n+ *\n+ * @param[in] attr\n+ *   Pointer to the flow attributes.\n+ * @param[in] items\n+ *   Pointer to the list of items.\n+ * @param[in] actions\n+ *   Pointer to the list of actions.\n+ * @param[out] item_flags\n+ *   Pointer to bit mask of all items detected.\n+ * @param[out] action_flags\n+ *   Pointer to bit mask of all actions detected.\n+ * @param[out] error\n+ *   Pointer to the error structure.\n+ *\n+ * @return\n+ *   Pointer to mlx5_flow object on success,\n+ *   otherwise NULL and rte_ernno is set.\n+ */\n+static struct mlx5_flow *\n+flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,\n+\t\tconst struct rte_flow_item items[] __rte_unused,\n+\t\tconst struct rte_flow_action actions[] __rte_unused,\n+\t\tuint64_t *item_flags __rte_unused,\n+\t\tuint64_t *action_flags __rte_unused,\n+\t\tstruct rte_flow_error *error)\n+{\n+\tuint32_t size = sizeof(struct mlx5_flow);\n+\tstruct mlx5_flow *flow;\n+\n+\tflow = rte_calloc(__func__, 1, size, 0);\n+\tif (!flow) {\n+\t\trte_flow_error_set(error, ENOMEM,\n+\t\t\t\t   RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t   \"not enough memory to create flow\");\n+\t\treturn NULL;\n+\t}\n+\tflow->dv.value.size = MLX5_ST_SZ_DB(fte_match_param);\n+\treturn flow;\n+}\n+\n+/**\n  * Fills the flow_ops with the function pointers.\n  *\n  * @param[out] flow_ops\n@@ -301,7 +344,7 @@ mlx5_flow_dv_get_driver_ops(struct mlx5_flow_driver_ops *flow_ops)\n {\n \t*flow_ops = (struct mlx5_flow_driver_ops) {\n \t\t.validate = flow_dv_validate,\n-\t\t.prepare = NULL,\n+\t\t.prepare = flow_dv_prepare,\n \t\t.translate = NULL,\n \t\t.apply = NULL,\n \t\t.remove = NULL,\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 0870d32fd..2222e7fbd 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -280,6 +280,219 @@ struct mlx5_cqe {\n /* CQE format value. */\n #define MLX5_COMPRESSED 0x3\n \n+/* The field of packet to be modified. */\n+enum mlx5_modificaiton_field {\n+\tMLX5_MODI_OUT_SMAC_47_16 = 1,\n+\tMLX5_MODI_OUT_SMAC_15_0,\n+\tMLX5_MODI_OUT_ETHERTYPE,\n+\tMLX5_MODI_OUT_DMAC_47_16,\n+\tMLX5_MODI_OUT_DMAC_15_0,\n+\tMLX5_MODI_OUT_IP_DSCP,\n+\tMLX5_MODI_OUT_TCP_FLAGS,\n+\tMLX5_MODI_OUT_TCP_SPORT,\n+\tMLX5_MODI_OUT_TCP_DPORT,\n+\tMLX5_MODI_OUT_IPV4_TTL,\n+\tMLX5_MODI_OUT_UDP_SPORT,\n+\tMLX5_MODI_OUT_UDP_DPORT,\n+\tMLX5_MODI_OUT_SIPV6_127_96,\n+\tMLX5_MODI_OUT_SIPV6_95_64,\n+\tMLX5_MODI_OUT_SIPV6_63_32,\n+\tMLX5_MODI_OUT_SIPV6_31_0,\n+\tMLX5_MODI_OUT_DIPV6_127_96,\n+\tMLX5_MODI_OUT_DIPV6_95_64,\n+\tMLX5_MODI_OUT_DIPV6_63_32,\n+\tMLX5_MODI_OUT_DIPV6_31_0,\n+\tMLX5_MODI_OUT_SIPV4,\n+\tMLX5_MODI_OUT_DIPV4,\n+\tMLX5_MODI_IN_SMAC_47_16 = 0x31,\n+\tMLX5_MODI_IN_SMAC_15_0,\n+\tMLX5_MODI_IN_ETHERTYPE,\n+\tMLX5_MODI_IN_DMAC_47_16,\n+\tMLX5_MODI_IN_DMAC_15_0,\n+\tMLX5_MODI_IN_IP_DSCP,\n+\tMLX5_MODI_IN_TCP_FLAGS,\n+\tMLX5_MODI_IN_TCP_SPORT,\n+\tMLX5_MODI_IN_TCP_DPORT,\n+\tMLX5_MODI_IN_IPV4_TTL,\n+\tMLX5_MODI_IN_UDP_SPORT,\n+\tMLX5_MODI_IN_UDP_DPORT,\n+\tMLX5_MODI_IN_SIPV6_127_96,\n+\tMLX5_MODI_IN_SIPV6_95_64,\n+\tMLX5_MODI_IN_SIPV6_63_32,\n+\tMLX5_MODI_IN_SIPV6_31_0,\n+\tMLX5_MODI_IN_DIPV6_127_96,\n+\tMLX5_MODI_IN_DIPV6_95_64,\n+\tMLX5_MODI_IN_DIPV6_63_32,\n+\tMLX5_MODI_IN_DIPV6_31_0,\n+\tMLX5_MODI_IN_SIPV4,\n+\tMLX5_MODI_IN_DIPV4,\n+\tMLX5_MODI_OUT_IPV6_HOPLIMIT,\n+\tMLX5_MODI_IN_IPV6_HOPLIMIT,\n+\tMLX5_MODI_META_DATA_REG_A,\n+\tMLX5_MODI_META_DATA_REG_B = 0x50,\n+};\n+\n+/* Modification sub command. */\n+struct mlx5_modification_cmd {\n+\tunion {\n+\t\tuint32_t data0;\n+\t\tstruct {\n+\t\t\tunsigned int bits:5;\n+\t\t\tunsigned int rsvd0:3;\n+\t\t\tunsigned int src_offset:5; /* Start bit offset. */\n+\t\t\tunsigned int rsvd1:3;\n+\t\t\tunsigned int src_field:12;\n+\t\t\tunsigned int type:4;\n+\t\t};\n+\t};\n+\tunion {\n+\t\tuint32_t data1;\n+\t\tuint8_t data[4];\n+\t\tstruct {\n+\t\t\tunsigned int rsvd2:8;\n+\t\t\tunsigned int dst_offset:8;\n+\t\t\tunsigned int dst_field:12;\n+\t\t\tunsigned int rsvd3:4;\n+\t\t};\n+\t};\n+};\n+\n+typedef uint32_t u32;\n+typedef uint16_t u16;\n+typedef uint8_t u8;\n+\n+#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)\n+#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)\n+#define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \\\n+\t\t\t\t  (&(__mlx5_nullp(typ)->fld)))\n+#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \\\n+\t\t\t\t    (__mlx5_bit_off(typ, fld) & 0x1f))\n+#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)\n+#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \\\n+\t\t\t\t  __mlx5_dw_bit_off(typ, fld))\n+#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))\n+#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)\n+#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \\\n+\t\t\t\t    (__mlx5_bit_off(typ, fld) & 0xf))\n+#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))\n+#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)\n+#define MLX5_ST_SZ_DB(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)\n+#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)\n+#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))\n+\n+/* insert a value to a struct */\n+#define MLX5_SET(typ, p, fld, v) \\\n+\tdo { \\\n+\t\tu32 _v = v; \\\n+\t\t*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \\\n+\t\trte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \\\n+\t\t\t\t  __mlx5_dw_off(typ, fld))) & \\\n+\t\t\t\t  (~__mlx5_dw_mask(typ, fld))) | \\\n+\t\t\t\t (((_v) & __mlx5_mask(typ, fld)) << \\\n+\t\t\t\t   __mlx5_dw_bit_off(typ, fld))); \\\n+\t} while (0)\n+#define MLX5_GET16(typ, p, fld) \\\n+\t((rte_be_to_cpu_16(*((__be16 *)(p) + \\\n+\t  __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \\\n+\t __mlx5_mask16(typ, fld))\n+#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)\n+\n+struct mlx5_ifc_fte_match_set_misc_bits {\n+\tu8 reserved_at_0[0x8];\n+\tu8 source_sqn[0x18];\n+\tu8 reserved_at_20[0x10];\n+\tu8 source_port[0x10];\n+\tu8 outer_second_prio[0x3];\n+\tu8 outer_second_cfi[0x1];\n+\tu8 outer_second_vid[0xc];\n+\tu8 inner_second_prio[0x3];\n+\tu8 inner_second_cfi[0x1];\n+\tu8 inner_second_vid[0xc];\n+\tu8 outer_second_cvlan_tag[0x1];\n+\tu8 inner_second_cvlan_tag[0x1];\n+\tu8 outer_second_svlan_tag[0x1];\n+\tu8 inner_second_svlan_tag[0x1];\n+\tu8 reserved_at_64[0xc];\n+\tu8 gre_protocol[0x10];\n+\tu8 gre_key_h[0x18];\n+\tu8 gre_key_l[0x8];\n+\tu8 vxlan_vni[0x18];\n+\tu8 reserved_at_b8[0x8];\n+\tu8 reserved_at_c0[0x20];\n+\tu8 reserved_at_e0[0xc];\n+\tu8 outer_ipv6_flow_label[0x14];\n+\tu8 reserved_at_100[0xc];\n+\tu8 inner_ipv6_flow_label[0x14];\n+\tu8 reserved_at_120[0xe0];\n+};\n+\n+struct mlx5_ifc_ipv4_layout_bits {\n+\tu8 reserved_at_0[0x60];\n+\tu8 ipv4[0x20];\n+};\n+\n+struct mlx5_ifc_ipv6_layout_bits {\n+\tu8 ipv6[16][0x8];\n+};\n+\n+union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {\n+\tstruct mlx5_ifc_ipv6_layout_bits ipv6_layout;\n+\tstruct mlx5_ifc_ipv4_layout_bits ipv4_layout;\n+\tu8 reserved_at_0[0x80];\n+};\n+\n+struct mlx5_ifc_fte_match_set_lyr_2_4_bits {\n+\tu8 smac_47_16[0x20];\n+\tu8 smac_15_0[0x10];\n+\tu8 ethertype[0x10];\n+\tu8 dmac_47_16[0x20];\n+\tu8 dmac_15_0[0x10];\n+\tu8 first_prio[0x3];\n+\tu8 first_cfi[0x1];\n+\tu8 first_vid[0xc];\n+\tu8 ip_protocol[0x8];\n+\tu8 ip_dscp[0x6];\n+\tu8 ip_ecn[0x2];\n+\tu8 cvlan_tag[0x1];\n+\tu8 svlan_tag[0x1];\n+\tu8 frag[0x1];\n+\tu8 ip_version[0x4];\n+\tu8 tcp_flags[0x9];\n+\tu8 tcp_sport[0x10];\n+\tu8 tcp_dport[0x10];\n+\tu8 reserved_at_c0[0x20];\n+\tu8 udp_sport[0x10];\n+\tu8 udp_dport[0x10];\n+\tunion mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;\n+\tunion mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;\n+};\n+\n+struct mlx5_ifc_fte_match_mpls_bits {\n+\tu8 mpls_label[0x14];\n+\tu8 mpls_exp[0x3];\n+\tu8 mpls_s_bos[0x1];\n+\tu8 mpls_ttl[0x8];\n+};\n+\n+struct mlx5_ifc_fte_match_set_misc2_bits {\n+\tstruct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;\n+\tstruct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;\n+\tstruct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;\n+\tstruct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;\n+\tu8 reserved_at_80[0x100];\n+\tu8 metadata_reg_a[0x20];\n+\tu8 reserved_at_1a0[0x60];\n+};\n+\n+/* Flow matcher. */\n+struct mlx5_ifc_fte_match_param_bits {\n+\tstruct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;\n+\tstruct mlx5_ifc_fte_match_set_misc_bits misc_parameters;\n+\tstruct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;\n+\tstruct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;\n+\tu8 reserved_at_800[0x800];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex d225b9c27..02034a4f4 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -171,6 +171,13 @@ struct mlx5_hrxq {\n \tuint8_t rss_key[]; /* Hash key. */\n };\n \n+/* List of cached objects. */\n+struct mlx5_cache {\n+\tLIST_ENTRY(mlx5_cache) next; /* Pointer to the next element. */\n+\trte_atomic32_t refcnt; /* Reference counter. */\n+\tvoid *resource; /* Cached resource */\n+};\n+\n /* TX queue descriptor. */\n __extension__\n struct mlx5_txq_data {\n",
    "prefixes": [
        "v3",
        "06/11"
    ]
}