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GET /api/patches/44643/?format=api
{ "id": 44643, "url": "http://patches.dpdk.org/api/patches/44643/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180913060846.29930-8-g.singh@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180913060846.29930-8-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180913060846.29930-8-g.singh@nxp.com", "date": "2018-09-13T06:08:43", "name": "[07/10] crypto/caam_jr: add enqueue and dequeue routines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fbc1c1abd58afded6646c4780d636c92ef7bdc06", "submitter": { "id": 1068, "url": "http://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180913060846.29930-8-g.singh@nxp.com/mbox/", "series": [ { "id": 1300, "url": "http://patches.dpdk.org/api/series/1300/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1300", "date": "2018-09-13T06:08:36", "name": "Introducing the NXP CAAM job ring driver", "version": 1, "mbox": "http://patches.dpdk.org/series/1300/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44643/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/44643/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DB8E25F0D;\n\tThu, 13 Sep 2018 08:09:45 +0200 (CEST)", "from EUR02-VE1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr20055.outbound.protection.outlook.com [40.107.2.55])\n\tby dpdk.org (Postfix) with ESMTP id 9C2DF58CB\n\tfor <dev@dpdk.org>; Thu, 13 Sep 2018 08:09:36 +0200 (CEST)", "from Tophie.ap.freescale.net (14.142.187.166) by\n\tHE1PR04MB1529.eurprd04.prod.outlook.com (2a01:111:e400:59a8::19) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1143.15;\n\tThu, 13 Sep 2018 06:09:33 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=k7Om6u8bqruK5cnR0DmuPlVVgK61JauyX5pWDXl/HMk=;\n\tb=V1UV1tTy33JJPpXiPm3GiuGNfqL1S1bJM7q/Et3+9K/YRIWFYCdr+C2rKxTSG8+9YPly8UtFyrjWvAcMVXWkmVfinNOEA6fY+p80ktfb+lvq1m7JuU17tixzA0gUma/NwW6wnAXZP4jgtZMAzLevPdS7ApePskKJiRtHlcXKuK0=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=G.Singh@nxp.com; ", "From": "Gagandeep Singh <g.singh@nxp.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "Hemant Agrawal <hemant.agrawal@nxp.com>,\n\tGagandeep Singh <g.singh@nxp.com>", "Date": "Thu, 13 Sep 2018 11:38:43 +0530", "Message-Id": "<20180913060846.29930-8-g.singh@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20180913060846.29930-1-g.singh@nxp.com>", "References": "<20180913060846.29930-1-g.singh@nxp.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[14.142.187.166]", "X-ClientProxiedBy": "BM1PR01CA0095.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00::11)\n\tTo HE1PR04MB1529.eurprd04.prod.outlook.com\n\t(2a01:111:e400:59a8::19)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "545f8fd4-ee1f-4cc8-291a-08d6193f7a23", "X-MS-Office365-Filtering-HT": "Tenant", "X-Microsoft-Antispam": "BCL:0; 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PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(823301075)(3231311)(944501410)(52105095)(3002001)(93006095)(93001095)(10201501046)(6055026)(149027)(150027)(6041310)(20161123558120)(20161123562045)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(201708071742011)(7699050);\n\tSRVR:HE1PR04MB1529; BCL:0; PCL:0; RULEID:; SRVR:HE1PR04MB1529; ", "X-Forefront-PRVS": "07943272E1", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(366004)(376002)(39860400002)(136003)(346002)(396003)(189003)(199004)(2906002)(6506007)(386003)(5009440100003)(6486002)(51416003)(6512007)(52116002)(486006)(2616005)(68736007)(956004)(53936002)(476003)(446003)(11346002)(305945005)(26005)(7736002)(55236004)(76176011)(186003)(16526019)(50226002)(478600001)(47776003)(1076002)(3846002)(6116002)(48376002)(105586002)(106356001)(25786009)(14444005)(50466002)(5660300001)(36756003)(72206003)(66066001)(316002)(97736004)(8936002)(81166006)(4326008)(8676002)(86362001)(6636002)(6666003)(575784001)(54906003)(81156014)(16586007)(110426005)(134034003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR04MB1529;\n\tH:Tophie.ap.freescale.net; FPR:; \n\tSPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; ", "Received-SPF": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "rUot0h5poEb5+CGHdUwj5g9EdwuMH9WOaWKxInB62flKaK3BI+Y/s4sf6HRrbgwXVCMDDa6XcnUYcxiBhaTkKi9Ulk1vQ+Wj4aNeUPPjmLN0nqkHNfcAGRp/4ow/A71liHTt+WnXQVQg5wsU2cr7CuiQYqMDEzzTG7rfDaLOALZ4mbD7amTUewyO8akKB4mgaDFlz/6X/pcLg1rl3MEtPcuEJojNZ03eah0K0o44c8SXtWnMmyBU1ghfY49Y+tgxY80NHRhG2smZMXkZ08Q5WP4yHTpFZD9IyRADP4w6r77zURnElFvuRIHu17gcQdTJW37qOGrGjGLduuMNK8DKwoqTj0kgrs6//XP6D63WSYo=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Sep 2018 06:09:33.0543\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "545f8fd4-ee1f-4cc8-291a-08d6193f7a23", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "HE1PR04MB1529", "Subject": "[dpdk-dev] [PATCH 07/10] crypto/caam_jr: add enqueue and dequeue\n\troutines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Hemant Agrawal <hemant.agrawal@nxp.com>\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n drivers/crypto/caam_jr/caam_jr.c | 621 +++++++++++++++++++++++++-\n drivers/crypto/caam_jr/caam_jr_desc.h | 289 ++++++++++++\n 2 files changed, 908 insertions(+), 2 deletions(-)\n create mode 100644 drivers/crypto/caam_jr/caam_jr_desc.h", "diff": "diff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c\nindex a0eee3b85..6d30c4f4d 100644\n--- a/drivers/crypto/caam_jr/caam_jr.c\n+++ b/drivers/crypto/caam_jr/caam_jr.c\n@@ -25,6 +25,7 @@\n #include <caam_jr_hw_specific.h>\n #include <caam_jr.h>\n #include <caam_jr_pvt.h>\n+#include <caam_jr_desc.h>\n #include <caam_jr_log.h>\n \n #define CRYPTODEV_NAME_CAAM_JR_PMD\tcrypto_caam_jr\n@@ -50,6 +51,142 @@ static enum sec_driver_state_e g_driver_state = SEC_DRIVER_STATE_IDLE;\n static int g_job_rings_no;\n static int g_job_rings_max;\n \n+struct sec_outring_entry {\n+\tphys_addr_t desc;\t/* Pointer to completed descriptor */\n+\tuint32_t status;\t/* Status for completed descriptor */\n+} __rte_packed;\n+\n+/* virtual address conversin when mempool support is available for ctx */\n+static inline phys_addr_t\n+caam_jr_vtop_ctx(struct caam_jr_op_ctx *ctx, void *vaddr)\n+{\n+\treturn (size_t)vaddr - ctx->vtop_offset;\n+}\n+\n+static inline void\n+caam_jr_op_ending(struct caam_jr_op_ctx *ctx)\n+{\n+\t/* report op status to sym->op and then free the ctx memeory */\n+\trte_mempool_put(ctx->ctx_pool, (void *)ctx);\n+}\n+\n+static inline struct caam_jr_op_ctx *\n+caam_jr_alloc_ctx(struct caam_jr_session *ses)\n+{\n+\tstruct caam_jr_op_ctx *ctx;\n+\tint ret;\n+\n+\tret = rte_mempool_get(ses->ctx_pool, (void **)(&ctx));\n+\tif (!ctx || ret) {\n+\t\tCAAM_JR_DP_WARN(\"Alloc sec descriptor failed!\");\n+\t\treturn NULL;\n+\t}\n+\t/*\n+\t * Clear SG memory. There are 16 SG entries of 16 Bytes each.\n+\t * one call to dcbz_64() clear 64 bytes, hence calling it 4 times\n+\t * to clear all the SG entries. caam_jr_alloc_ctx() is called for\n+\t * each packet, memset is costlier than dcbz_64().\n+\t */\n+\tdcbz_64(&ctx->sg[SG_CACHELINE_0]);\n+\tdcbz_64(&ctx->sg[SG_CACHELINE_1]);\n+\tdcbz_64(&ctx->sg[SG_CACHELINE_2]);\n+\tdcbz_64(&ctx->sg[SG_CACHELINE_3]);\n+\n+\tctx->ctx_pool = ses->ctx_pool;\n+\tctx->vtop_offset = (size_t) ctx - rte_mempool_virt2iova(ctx);\n+\n+\treturn ctx;\n+}\n+static inline int is_cipher_only(struct caam_jr_session *ses)\n+{\n+\treturn ((ses->cipher_alg != RTE_CRYPTO_CIPHER_NULL) &&\n+\t\t(ses->auth_alg == RTE_CRYPTO_AUTH_NULL));\n+}\n+\n+static inline void\n+caam_cipher_alg(struct caam_jr_session *ses, struct alginfo *alginfo_c)\n+{\n+\tswitch (ses->cipher_alg) {\n+\tcase RTE_CRYPTO_CIPHER_NULL:\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_AES_CBC:\n+\t\talginfo_c->algtype = OP_ALG_ALGSEL_AES;\n+\t\talginfo_c->algmode = OP_ALG_AAI_CBC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_3DES_CBC:\n+\t\talginfo_c->algtype = OP_ALG_ALGSEL_3DES;\n+\t\talginfo_c->algmode = OP_ALG_AAI_CBC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_CIPHER_AES_CTR:\n+\t\talginfo_c->algtype = OP_ALG_ALGSEL_AES;\n+\t\talginfo_c->algmode = OP_ALG_AAI_CTR;\n+\t\tbreak;\n+\tdefault:\n+\t\tCAAM_JR_DEBUG(\"unsupported cipher alg %d\", ses->cipher_alg);\n+\t}\n+}\n+\n+/* prepare command block of the session */\n+static int\n+caam_jr_prep_cdb(struct caam_jr_session *ses)\n+{\n+\tstruct alginfo alginfo_c = {0};\n+\tint32_t shared_desc_len = 0;\n+\tstruct sec_cdb *cdb;\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\tint swap = false;\n+#else\n+\tint swap = true;\n+#endif\n+\n+\tif (ses->cdb)\n+\t\tcaam_jr_dma_free(ses->cdb);\n+\n+\tcdb = caam_jr_dma_mem_alloc(L1_CACHE_BYTES, sizeof(struct sec_cdb));\n+\tif (!cdb) {\n+\t\tCAAM_JR_ERR(\"failed to allocate memory for cdb\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tses->cdb = cdb;\n+\n+\tmemset(cdb, 0, sizeof(struct sec_cdb));\n+\n+\tif (is_cipher_only(ses)) {\n+\t\tcaam_cipher_alg(ses, &alginfo_c);\n+\t\tif (alginfo_c.algtype == (unsigned int)CAAM_JR_ALG_UNSUPPORT) {\n+\t\t\tCAAM_JR_ERR(\"not supported cipher alg\");\n+\t\t\trte_free(cdb);\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\n+\t\talginfo_c.key = (size_t)ses->cipher_key.data;\n+\t\talginfo_c.keylen = ses->cipher_key.length;\n+\t\talginfo_c.key_enc_flags = 0;\n+\t\talginfo_c.key_type = RTA_DATA_IMM;\n+\n+\t\tshared_desc_len = cnstr_shdsc_blkcipher(\n+\t\t\t\t\t\tcdb->sh_desc, true,\n+\t\t\t\t\t\tswap, &alginfo_c,\n+\t\t\t\t\t\tNULL,\n+\t\t\t\t\t\tses->iv.length,\n+\t\t\t\t\t\tses->dir);\n+\t}\n+\n+\tif (shared_desc_len < 0) {\n+\t\tCAAM_JR_ERR(\"error in preparing command block\");\n+\t\treturn shared_desc_len;\n+\t}\n+\n+#ifdef RTE_LIBRTE_PMD_CAAM_JR_DEBUG\n+\tSEC_DUMP_DESC(cdb->sh_desc);\n+#endif\n+\n+\tcdb->sh_hdr.hi.field.idlen = shared_desc_len;\n+\n+\treturn 0;\n+}\n+\n /* @brief Poll the HW for already processed jobs in the JR\n * and silently discard the available jobs or notify them to UA\n * with indicated error code.\n@@ -105,6 +242,486 @@ static void hw_flush_job_ring(struct sec_job_ring_t *job_ring,\n \t}\n }\n \n+/* @brief Poll the HW for already processed jobs in the JR\n+ * and notify the available jobs to UA.\n+ *\n+ * @param [in] job_ring\tThe job ring to poll.\n+ * @param [in] limit The maximum number of jobs to notify.\n+ * If set to negative value, all available jobs are\n+ *\t\t\t\tnotified.\n+ *\n+ * @retval >=0 for No of jobs notified to UA.\n+ * @retval -1 for error\n+ */\n+static int\n+hw_poll_job_ring(struct sec_job_ring_t *job_ring,\n+\t\t struct rte_crypto_op **ops, int32_t limit,\n+\t\t struct caam_jr_qp *jr_qp)\n+{\n+\tint32_t jobs_no_to_notify = 0; /* the number of done jobs to notify*/\n+\tint32_t number_of_jobs_available = 0;\n+\tint32_t notified_descs_no = 0;\n+\tuint32_t sec_error_code = 0;\n+\tstruct job_descriptor *current_desc;\n+\tphys_addr_t current_desc_addr;\n+\tphys_addr_t *temp_addr;\n+\tstruct caam_jr_op_ctx *ctx;\n+\n+\t/* TODO check for ops have memory*/\n+\t/* check here if any JR error that cannot be written\n+\t * in the output status word has occurred\n+\t */\n+\tif (JR_REG_JRINT_JRE_EXTRACT(GET_JR_REG(JRINT, job_ring))) {\n+\t\tCAAM_JR_INFO(\"err received\");\n+\t\tsec_error_code = JR_REG_JRINT_ERR_TYPE_EXTRACT(\n+\t\t\t\t\tGET_JR_REG(JRINT, job_ring));\n+\t\tif (unlikely(sec_error_code)) {\n+\t\t\thw_job_ring_error_print(job_ring, sec_error_code);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\t/* compute the number of jobs available in the job ring based on the\n+\t * producer and consumer index values.\n+\t */\n+\tnumber_of_jobs_available = hw_get_no_finished_jobs(job_ring);\n+\t/* Compute the number of notifications that need to be raised to UA\n+\t * If limit > total number of done jobs -> notify all done jobs\n+\t * If limit = 0 -> error\n+\t * If limit < total number of done jobs -> notify a number\n+\t * of done jobs equal with limit\n+\t */\n+\tjobs_no_to_notify = (limit > number_of_jobs_available) ?\n+\t\t\t\tnumber_of_jobs_available : limit;\n+\tCAAM_JR_DP_DEBUG(\n+\t\t\"Jr[%p] pi[%d] ci[%d].limit =%d Available=%d.Jobs to notify=%d\",\n+\t\tjob_ring, job_ring->pidx, job_ring->cidx,\n+\t\tlimit, number_of_jobs_available, jobs_no_to_notify);\n+\n+\trte_smp_rmb();\n+\n+\twhile (jobs_no_to_notify > notified_descs_no) {\n+\t\tstatic uint64_t false_alarm;\n+\t\tstatic uint64_t real_poll;\n+\n+\t\t/* Get job status here */\n+\t\tsec_error_code = job_ring->output_ring[job_ring->cidx].status;\n+\t\t/* Get completed descriptor */\n+\t\ttemp_addr = &(job_ring->output_ring[job_ring->cidx].desc);\n+\t\tcurrent_desc_addr = (phys_addr_t)sec_read_addr(temp_addr);\n+\n+\t\treal_poll++;\n+\t\t/* todo check if it is false alarm no desc present */\n+\t\tif (!current_desc_addr) {\n+\t\t\tfalse_alarm++;\n+\t\t\tprintf(\"false alarm %\" PRIu64 \"real %\" PRIu64\n+\t\t\t\t\" sec_err =0x%x cidx Index =0%d\\n\",\n+\t\t\t\tfalse_alarm, real_poll,\n+\t\t\t\tsec_error_code, job_ring->cidx);\n+\t\t\trte_panic(\"CAAM JR descriptor NULL\");\n+\t\t\treturn notified_descs_no;\n+\t\t}\n+\t\tcurrent_desc = (struct job_descriptor *)\n+\t\t\t\tcaam_jr_dma_ptov(current_desc_addr);\n+\t\t/* now increment the consumer index for the current job ring,\n+\t\t * AFTER saving job in temporary location!\n+\t\t */\n+\t\tjob_ring->cidx = SEC_CIRCULAR_COUNTER(job_ring->cidx,\n+\t\t\t\t SEC_JOB_RING_SIZE);\n+\t\t/* Signal that the job has been processed and the slot is free*/\n+\t\thw_remove_entries(job_ring, 1);\n+\t\t/*TODO for multiple ops, packets*/\n+\t\tctx = container_of(current_desc, struct caam_jr_op_ctx, jobdes);\n+\t\tif (unlikely(sec_error_code)) {\n+\t\t\tCAAM_JR_ERR(\"desc at cidx %d generated error 0x%x\\n\",\n+\t\t\t\tjob_ring->cidx, sec_error_code);\n+\t\t\thw_handle_job_ring_error(job_ring, sec_error_code);\n+\t\t\t//todo improve with exact errors\n+\t\t\tctx->op->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\tjr_qp->rx_errs++;\n+\t\t} else {\n+\t\t\tctx->op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+#ifdef RTE_LIBRTE_PMD_CAAM_JR_DEBUG\n+\t\t\tif (ctx->op->sym->m_dst) {\n+\t\t\t\trte_hexdump(stdout, \"PROCESSED\",\n+\t\t\t\trte_pktmbuf_mtod(ctx->op->sym->m_dst, void *),\n+\t\t\t\trte_pktmbuf_data_len(ctx->op->sym->m_dst));\n+\t\t\t} else {\n+\t\t\t\trte_hexdump(stdout, \"PROCESSED\",\n+\t\t\t\trte_pktmbuf_mtod(ctx->op->sym->m_src, void *),\n+\t\t\t\trte_pktmbuf_data_len(ctx->op->sym->m_src));\n+\t\t\t}\n+#endif\n+\t\t}\n+\t\tif (ctx->op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n+\t\t\tstruct ip *ip4_hdr;\n+\n+\t\t\tif (ctx->op->sym->m_dst) {\n+\t\t\t\t/*TODO check for ip header or other*/\n+\t\t\t\tip4_hdr = (struct ip *)rte_pktmbuf_mtod(ctx->op->sym->m_dst, char*);\n+\t\t\t\tctx->op->sym->m_dst->pkt_len =\n+\t\t\t\t\trte_be_to_cpu_16(ip4_hdr->ip_len);\n+\t\t\t\tctx->op->sym->m_dst->data_len =\n+\t\t\t\t\trte_be_to_cpu_16(ip4_hdr->ip_len);\n+\t\t\t} else {\n+\t\t\t\tip4_hdr = (struct ip *)rte_pktmbuf_mtod(ctx->op->sym->m_src, char*);\n+\t\t\t\tctx->op->sym->m_src->pkt_len =\n+\t\t\t\t\trte_be_to_cpu_16(ip4_hdr->ip_len);\n+\t\t\t\tctx->op->sym->m_src->data_len =\n+\t\t\t\t\trte_be_to_cpu_16(ip4_hdr->ip_len);\n+\t\t\t}\n+\t\t}\n+\t\t*ops = ctx->op;\n+\t\tcaam_jr_op_ending(ctx);\n+\t\tops++;\n+\t\tnotified_descs_no++;\n+\t}\n+\treturn notified_descs_no;\n+}\n+\n+static uint16_t\n+caam_jr_dequeue_burst(void *qp, struct rte_crypto_op **ops,\n+\t\t uint16_t nb_ops)\n+{\n+\tstruct caam_jr_qp *jr_qp = (struct caam_jr_qp *)qp;\n+\tstruct sec_job_ring_t *ring = jr_qp->ring;\n+\tint num_rx;\n+\tint ret;\n+\n+\tCAAM_JR_DP_DEBUG(\"Jr[%p]Polling. limit[%d]\", ring, nb_ops);\n+\n+\t/* Poll job ring\n+\t * If nb_ops < 0 -> poll JR until no more notifications are available.\n+\t * If nb_ops > 0 -> poll JR until limit is reached.\n+\t */\n+\n+\t/* Run hw poll job ring */\n+\tnum_rx = hw_poll_job_ring(ring, ops, nb_ops, jr_qp);\n+\tif (num_rx < 0) {\n+\t\tCAAM_JR_ERR(\"Error polling SEC engine (%d)\", num_rx);\n+\t\treturn 0;\n+\t}\n+\n+\tCAAM_JR_DP_DEBUG(\"Jr[%p].Jobs notified[%d]. \", ring, num_rx);\n+\n+\tif (ring->jr_mode == SEC_NOTIFICATION_TYPE_NAPI) {\n+\t\tif (num_rx < nb_ops) {\n+\t\t\tret = caam_jr_enable_irqs(ring->irq_fd);\n+\t\t\tSEC_ASSERT(ret == 0, ret,\n+\t\t\t\"Failed to enable irqs for job ring %p\", ring);\n+\t\t}\n+\t} else if (ring->jr_mode == SEC_NOTIFICATION_TYPE_IRQ) {\n+\n+\t\t/* Always enable IRQ generation when in pure IRQ mode */\n+\t\tret = caam_jr_enable_irqs(ring->irq_fd);\n+\t\tSEC_ASSERT(ret == 0, ret,\n+\t\t\t\"Failed to enable irqs for job ring %p\", ring);\n+\t}\n+\n+\tjr_qp->rx_pkts += num_rx;\n+\n+\treturn num_rx;\n+}\n+\n+\n+static inline struct caam_jr_op_ctx *\n+build_cipher_only_sg(struct rte_crypto_op *op, struct caam_jr_session *ses)\n+{\n+\tstruct rte_crypto_sym_op *sym = op->sym;\n+\tstruct rte_mbuf *mbuf = sym->m_src;\n+\tstruct caam_jr_op_ctx *ctx;\n+\tstruct sec4_sg_entry *sg, *in_sg;\n+\tint length;\n+\tstruct sec_cdb *cdb;\n+\tuint64_t sdesc_offset;\n+\tuint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,\n+\t\t\tses->iv.offset);\n+\tstruct sec_job_descriptor_t *jobdescr;\n+\tuint8_t reg_segs;\n+\n+\tif (sym->m_dst) {\n+\t\tmbuf = sym->m_dst;\n+\t\treg_segs = mbuf->nb_segs + sym->m_src->nb_segs + 2;\n+\t} else {\n+\t\tmbuf = sym->m_src;\n+\t\treg_segs = mbuf->nb_segs * 2 + 2;\n+\t}\n+\n+\tif (reg_segs > MAX_SG_ENTRIES) {\n+\t\tCAAM_JR_DP_ERR(\"Cipher: Max sec segs supported is %d\",\n+\t\t\t\tMAX_SG_ENTRIES);\n+\t\treturn NULL;\n+\t}\n+\n+\tctx = caam_jr_alloc_ctx(ses);\n+\tif (!ctx)\n+\t\treturn NULL;\n+\n+\tctx->op = op;\n+\tcdb = ses->cdb;\n+\tsdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);\n+\n+\tjobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;\n+\n+\tSEC_JD_INIT(jobdescr);\n+\tSEC_JD_SET_SD(jobdescr,\n+\t\t(phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,\n+\t\tcdb->sh_hdr.hi.field.idlen);\n+\n+#ifdef RTE_LIBRTE_PMD_CAAM_JR_DEBUG\n+\tCAAM_JR_INFO(\"mbuf offset =%d, cipher offset = %d, length =%d+%d\",\n+\t\t\tsym->m_src->data_off, sym->cipher.data.offset,\n+\t\t\tsym->cipher.data.length, ses->iv.length);\n+#endif\n+\t/* output */\n+\tif (sym->m_dst)\n+\t\tmbuf = sym->m_dst;\n+\telse\n+\t\tmbuf = sym->m_src;\n+\n+\tsg = &ctx->sg[0];\n+\tlength = sym->cipher.data.length;\n+\n+\tsg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf)\n+\t\t+ sym->cipher.data.offset);\n+\tsg->len = cpu_to_caam32(mbuf->data_len - sym->cipher.data.offset);\n+\n+\t/* Successive segs */\n+\tmbuf = mbuf->next;\n+\twhile (mbuf) {\n+\t\tsg++;\n+\t\tsg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf));\n+\t\tsg->len = cpu_to_caam32(mbuf->data_len);\n+\t\tmbuf = mbuf->next;\n+\t}\n+\t/* last element*/\n+\tsg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);\n+\n+\tSEC_JD_SET_OUT_PTR(jobdescr,\n+\t\t\t(uint64_t)caam_jr_vtop_ctx(ctx, &ctx->sg[0]), 0,\n+\t\t\tlength);\n+\t/*enabling sg bit */\n+\t(jobdescr)->seq_out.command.word |= 0x01000000;\n+\n+\t/*input */\n+\tsg++;\n+\tmbuf = sym->m_src;\n+\tin_sg = sg;\n+\n+\tlength = sym->cipher.data.length + ses->iv.length;\n+\n+\t/* IV */\n+\tsg->ptr = cpu_to_caam64(caam_jr_dma_vtop(IV_ptr));\n+\tsg->len = cpu_to_caam32(ses->iv.length);\n+\n+\t/* 1st seg */\n+\tsg++;\n+\tsg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf)\n+\t\t\t\t+ sym->cipher.data.offset);\n+\tsg->len = cpu_to_caam32(mbuf->data_len - sym->cipher.data.offset);\n+\n+\t/* Successive segs */\n+\tmbuf = mbuf->next;\n+\twhile (mbuf) {\n+\t\tsg++;\n+\t\tsg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf));\n+\t\tsg->len = cpu_to_caam32(mbuf->data_len);\n+\t\tmbuf = mbuf->next;\n+\t}\n+\t/* last element*/\n+\tsg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);\n+\n+\n+\tSEC_JD_SET_IN_PTR(jobdescr, (uint64_t)caam_jr_vtop_ctx(ctx, in_sg), 0,\n+\t\t\t\tlength);\n+\t/*enabling sg bit */\n+\t(jobdescr)->seq_in.command.word |= 0x01000000;\n+\n+\treturn ctx;\n+}\n+\n+static inline struct caam_jr_op_ctx *\n+build_cipher_only(struct rte_crypto_op *op, struct caam_jr_session *ses)\n+{\n+\tstruct rte_crypto_sym_op *sym = op->sym;\n+\tstruct caam_jr_op_ctx *ctx;\n+\tstruct sec4_sg_entry *sg;\n+\trte_iova_t src_start_addr, dst_start_addr;\n+\tstruct sec_cdb *cdb;\n+\tuint64_t sdesc_offset;\n+\tuint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,\n+\t\t\tses->iv.offset);\n+\tstruct sec_job_descriptor_t *jobdescr;\n+\n+\tctx = caam_jr_alloc_ctx(ses);\n+\tif (!ctx)\n+\t\treturn NULL;\n+\n+\tctx->op = op;\n+\tcdb = ses->cdb;\n+\tsdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);\n+\n+\tsrc_start_addr = rte_pktmbuf_iova(sym->m_src);\n+\tif (sym->m_dst)\n+\t\tdst_start_addr = rte_pktmbuf_iova(sym->m_dst);\n+\telse\n+\t\tdst_start_addr = src_start_addr;\n+\n+\tjobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;\n+\n+\tSEC_JD_INIT(jobdescr);\n+\tSEC_JD_SET_SD(jobdescr,\n+\t\t(phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,\n+\t\tcdb->sh_hdr.hi.field.idlen);\n+\n+#ifdef RTE_LIBRTE_PMD_CAAM_JR_DEBUG\n+\tCAAM_JR_INFO(\"mbuf offset =%d, cipher offset = %d, length =%d+%d\",\n+\t\t\tsym->m_src->data_off, sym->cipher.data.offset,\n+\t\t\tsym->cipher.data.length, ses->iv.length);\n+#endif\n+\t/* output */\n+\tSEC_JD_SET_OUT_PTR(jobdescr, (uint64_t)dst_start_addr,\n+\t\t\tsym->cipher.data.offset,\n+\t\t\tsym->cipher.data.length + ses->iv.length);\n+\n+\t/*input */\n+\tsg = &ctx->sg[0];\n+\tSEC_JD_SET_IN_PTR(jobdescr, (uint64_t)caam_jr_vtop_ctx(ctx, sg), 0,\n+\t\t\t\tsym->cipher.data.length + ses->iv.length);\n+\t/*enabling sg bit */\n+\t(jobdescr)->seq_in.command.word |= 0x01000000;\n+\n+\tsg->ptr = cpu_to_caam64(caam_jr_dma_vtop(IV_ptr));\n+\tsg->len = cpu_to_caam32(ses->iv.length);\n+\n+\tsg = &ctx->sg[1];\n+\tsg->ptr = cpu_to_caam64(src_start_addr + sym->cipher.data.offset);\n+\tsg->len = cpu_to_caam32(sym->cipher.data.length);\n+\t/* last element*/\n+\tsg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);\n+\n+\treturn ctx;\n+}\n+\n+static int\n+caam_jr_enqueue_op(struct rte_crypto_op *op, struct caam_jr_qp *qp)\n+{\n+\tstruct sec_job_ring_t *ring = qp->ring;\n+\tstruct caam_jr_session *ses;\n+\tstruct caam_jr_op_ctx *ctx = NULL;\n+\tstruct sec_job_descriptor_t *jobdescr __rte_unused;\n+\n+\tswitch (op->sess_type) {\n+\tcase RTE_CRYPTO_OP_WITH_SESSION:\n+\t\tses = (struct caam_jr_session *)\n+\t\tget_sym_session_private_data(op->sym->session,\n+\t\t\t\t\tcryptodev_driver_id);\n+\t\tbreak;\n+\tdefault:\n+\t\tCAAM_JR_DP_ERR(\"sessionless crypto op not supported\");\n+\t\tqp->tx_errs++;\n+\t\treturn -1;\n+\t}\n+\n+\tif (unlikely(!ses->qp || ses->qp != qp)) {\n+\t\tCAAM_JR_DP_DEBUG(\"Old:sess->qp=%p New qp = %p\\n\", ses->qp, qp);\n+\t\tses->qp = qp;\n+\t\tcaam_jr_prep_cdb(ses);\n+\t}\n+\n+\tif (rte_pktmbuf_is_contiguous(op->sym->m_src)) {\n+\t\tif (is_cipher_only(ses))\n+\t\t\tctx = build_cipher_only(op, ses);\n+\t} else {\n+\t\tif (is_cipher_only(ses))\n+\t\t\tctx = build_cipher_only_sg(op, ses);\n+\t}\n+\tif (unlikely(!ctx)) {\n+\t\tqp->tx_errs++;\n+\t\tCAAM_JR_ERR(\"not supported sec op\");\n+\t\treturn -1;\n+\t}\n+#ifdef RTE_LIBRTE_PMD_CAAM_JR_DEBUG\n+\tif (is_decode(ses))\n+\t\trte_hexdump(stdout, \"DECODE\",\n+\t\t\trte_pktmbuf_mtod(op->sym->m_src, void *),\n+\t\t\trte_pktmbuf_data_len(op->sym->m_src));\n+\telse\n+\t\trte_hexdump(stdout, \"ENCODE\",\n+\t\t\trte_pktmbuf_mtod(op->sym->m_src, void *),\n+\t\t\trte_pktmbuf_data_len(op->sym->m_src));\n+\n+\tprintf(\"\\n JD before conversion\\n\");\n+\tfor (int i = 0; i < 12; i++)\n+\t\tprintf(\"\\n 0x%08x\", ctx->jobdes.desc[i]);\n+#endif\n+\n+\tCAAM_JR_DP_DEBUG(\"Jr[%p] pi[%d] ci[%d].Before sending desc\",\n+\t\t ring, ring->pidx, ring->cidx);\n+\n+\t/* todo - do we want to retry */\n+\tif (SEC_JOB_RING_IS_FULL(ring->pidx, ring->cidx,\n+\t\t\t SEC_JOB_RING_SIZE, SEC_JOB_RING_SIZE)) {\n+\t\tCAAM_JR_DP_DEBUG(\"Ring FULL Jr[%p] pi[%d] ci[%d].Size = %d\",\n+\t\t\t ring, ring->pidx, ring->cidx, SEC_JOB_RING_SIZE);\n+\t\tcaam_jr_op_ending(ctx);\n+\t\tqp->tx_ring_full++;\n+\t\treturn -EBUSY;\n+\t}\n+\n+#if CORE_BYTE_ORDER != CAAM_BYTE_ORDER\n+\tjobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;\n+\n+\tjobdescr->deschdr.command.word =\n+\t\tcpu_to_caam32(jobdescr->deschdr.command.word);\n+\tjobdescr->sd_ptr = cpu_to_caam64(jobdescr->sd_ptr);\n+\tjobdescr->seq_out.command.word =\n+\t\tcpu_to_caam32(jobdescr->seq_out.command.word);\n+\tjobdescr->seq_out_ptr = cpu_to_caam64(jobdescr->seq_out_ptr);\n+\tjobdescr->out_ext_length = cpu_to_caam32(jobdescr->out_ext_length);\n+\tjobdescr->seq_in.command.word =\n+\t\tcpu_to_caam32(jobdescr->seq_in.command.word);\n+\tjobdescr->seq_in_ptr = cpu_to_caam64(jobdescr->seq_in_ptr);\n+\tjobdescr->in_ext_length = cpu_to_caam32(jobdescr->in_ext_length);\n+\tjobdescr->load_dpovrd.command.word =\n+\t\tcpu_to_caam32(jobdescr->load_dpovrd.command.word);\n+\tjobdescr->dpovrd = cpu_to_caam32(jobdescr->dpovrd);\n+#endif\n+\n+\t/* Set ptr in input ring to current descriptor\t*/\n+\tsec_write_addr(&ring->input_ring[ring->pidx],\n+\t\t\t(phys_addr_t)caam_jr_vtop_ctx(ctx, ctx->jobdes.desc));\n+\trte_smp_wmb();\n+\n+\t/* Notify HW that a new job is enqueued */\n+\thw_enqueue_desc_on_job_ring(ring);\n+\n+\t/* increment the producer index for the current job ring */\n+\tring->pidx = SEC_CIRCULAR_COUNTER(ring->pidx, SEC_JOB_RING_SIZE);\n+\n+\treturn 0;\n+}\n+\n+static uint16_t\n+caam_jr_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n+\t\t uint16_t nb_ops)\n+{\n+\t/* Function to transmit the frames to given device and queuepair */\n+\tuint32_t loop;\n+\tint32_t ret;\n+\tstruct caam_jr_qp *jr_qp = (struct caam_jr_qp *)qp;\n+\tuint16_t num_tx = 0;\n+\t/*Prepare each packet which is to be sent*/\n+\tfor (loop = 0; loop < nb_ops; loop++) {\n+\t\tret = caam_jr_enqueue_op(ops[loop], jr_qp);\n+\t\tif (!ret)\n+\t\t\tnum_tx++;\n+\t}\n+\n+\tjr_qp->tx_pkts += num_tx;\n+\n+\treturn num_tx;\n+}\n+\n /* Release queue pair */\n static int\n caam_jr_queue_pair_release(struct rte_cryptodev *dev,\n@@ -642,8 +1259,8 @@ caam_jr_dev_init(const char *name,\n \tdev->dev_ops = &caam_jr_ops;\n \n \t/* register rx/tx burst functions for data path */\n-\tdev->dequeue_burst = NULL;\n-\tdev->enqueue_burst = NULL;\n+\tdev->dequeue_burst = caam_jr_dequeue_burst;\n+\tdev->enqueue_burst = caam_jr_enqueue_burst;\n \tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\ndiff --git a/drivers/crypto/caam_jr/caam_jr_desc.h b/drivers/crypto/caam_jr/caam_jr_desc.h\nnew file mode 100644\nindex 000000000..47c3adf72\n--- /dev/null\n+++ b/drivers/crypto/caam_jr/caam_jr_desc.h\n@@ -0,0 +1,289 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2017-2018 NXP\n+ */\n+\n+#ifndef CAAM_JR_DESC_H\n+#define CAAM_JR_DESC_H\n+\n+#define CMD_HDR_CTYPE_SD\t\t0x16\n+#define CMD_HDR_CTYPE_JD\t\t0x17\n+\n+/* The maximum size of a SEC descriptor, in WORDs (32 bits). */\n+#define MAX_DESC_SIZE_WORDS 64\n+\n+/*\n+ * Macros manipulating descriptors\n+ */\n+/* Macro for setting the SD pointer in a JD. Common for all protocols\n+ * supported by the SEC driver.\n+ */\n+#define SEC_JD_SET_SD(descriptor, ptr, len)\t {\t \\\n+\t(descriptor)->sd_ptr = (ptr);\t\t\t \\\n+\t(descriptor)->deschdr.command.jd.shr_desc_len = (len); \\\n+}\n+\n+/* Macro for setting a pointer to the job which this descriptor processes.\n+ * It eases the lookup procedure for identifying the descriptor that has\n+ * completed.\n+ */\n+#define SEC_JD_SET_JOB_PTR(descriptor, ptr) \\\n+\t((descriptor)->job_ptr = (ptr))\n+\n+/* Macro for setting up a JD. The structure of the JD is common across all\n+ * supported protocols, thus its structure is identical.\n+ */\n+#define SEC_JD_INIT(descriptor)\t ({ \\\n+\t/* CTYPE = job descriptor\t\t\t \\\n+\t * RSMS, DNR = 0\n+\t * ONE = 1\n+\t * Start Index = 0\n+\t * ZRO,TD, MTD = 0\n+\t * SHR = 1 (there's a shared descriptor referenced\n+\t *\t by this job descriptor,pointer in next word)\n+\t * REO = 1 (execute job descr. first, shared descriptor\n+\t *\t after)\n+\t * SHARE = DEFER\n+\t * Descriptor Length = 0 ( to be completed @ runtime )\n+\t */\t\t\t\t\t\t \\\n+\t(descriptor)->deschdr.command.word = 0xB0801C0D;\t\\\n+\t/*\n+\t * CTYPE = SEQ OUT command * Scater Gather Flag = 0\n+\t * (can be updated @ runtime) PRE = 0 * EXT = 1\n+\t * (data length is in next word, following the * command)\n+\t * RTO = 0\n+\t */\t\t\t\t\t\t\t\\\n+\t(descriptor)->seq_out.command.word = 0xF8400000; /**/ \\\n+\t/*\n+\t * CTYPE = SEQ IN command\n+\t * Scater Gather Flag = 0 (can be updated @ runtime)\n+\t * PRE = 0\n+\t * EXT = 1 ( data length is in next word, following the\n+\t *\t command)\n+\t * RTO = 0\n+\t */\t\t\t\t\t\t\t\\\n+\t(descriptor)->seq_in.command.word = 0xF0400000; /**/\t\\\n+\t/*\n+\t * In order to be compatible with QI scenarios, the DPOVRD value\n+\t * loaded must be formated like this:\n+\t * DPOVRD_EN (1b) | Res| DPOVRD Value (right aligned).\n+\t */\t\t\t\t\t\t\t\\\n+\t(descriptor)->load_dpovrd.command.word = 0x16870004;\t\\\n+\t/* By default, DPOVRD mechanism is disabled, thus the value to be\n+\t * LOAD-ed through the above descriptor command will be 0x0000_0000.\n+\t */\t\t\t\t\t\t\t\\\n+\t(descriptor)->dpovrd = 0x00000000;\t\t \\\n+})\n+\n+/* Macro for setting the pointer to the input buffer in the JD, according to\n+ * the parameters set by the user in the ::sec_packet_t structure.\n+ */\n+#define SEC_JD_SET_IN_PTR(descriptor, phys_addr, offset, length) { \\\n+\t(descriptor)->seq_in_ptr = (phys_addr) + (offset);\t \\\n+\t(descriptor)->in_ext_length = (length);\t\t\t \\\n+}\n+\n+/* Macro for setting the pointer to the output buffer in the JD, according to\n+ * the parameters set by the user in the ::sec_packet_t structure.\n+ */\n+#define SEC_JD_SET_OUT_PTR(descriptor, phys_addr, offset, length) { \\\n+\t(descriptor)->seq_out_ptr = (phys_addr) + (offset);\t \\\n+\t(descriptor)->out_ext_length = (length);\t\t\t\\\n+}\n+\n+/* Macro for setting the Scatter-Gather flag in the SEQ IN command. Used in\n+ * case the input buffer is split in multiple buffers, according to the user\n+ * specification.\n+ */\n+#define SEC_JD_SET_SG_IN(descriptor) \\\n+\t((descriptor)->seq_in.command.field.sgf = 1)\n+\n+/* Macro for setting the Scatter-Gather flag in the SEQ OUT command. Used in\n+ * case the output buffer is split in multiple buffers, according to the user\n+ * specification.\n+ */\n+#define SEC_JD_SET_SG_OUT(descriptor) \\\n+\t((descriptor)->seq_out.command.field.sgf = 1)\n+\n+#define SEC_JD_SET_DPOVRD(descriptor) \\\n+\n+/* Macro for retrieving a descriptor's length. Works for both SD and JD. */\n+#define SEC_GET_DESC_LEN(descriptor)\t\t\t\t\t\\\n+\t(((struct descriptor_header_s *)(descriptor))->command.sd.ctype == \\\n+\tCMD_HDR_CTYPE_SD ? ((struct descriptor_header_s *) \\\n+\t(descriptor))->command.sd.desclen :\t\\\n+\t((struct descriptor_header_s *)(descriptor))->command.jd.desclen)\n+\n+/* Helper macro for dumping the hex representation of a descriptor */\n+#define SEC_DUMP_DESC(descriptor) {\t\t\t\t\t\\\n+\tint __i;\t\t\t\t\t\t\t\\\n+\tCAAM_JR_INFO(\"Des@ 0x%08x\\n\", (uint32_t)((uint32_t *)(descriptor)));\\\n+\tfor (__i = 0;\t\t\t\t\t\t\\\n+\t\t__i < SEC_GET_DESC_LEN(descriptor);\t\t\t\\\n+\t\t__i++) {\t\t\t\t\t\t\\\n+\t\tprintf(\"0x%08x: 0x%08x\\n\",\t\t\t\\\n+\t\t\t(uint32_t)(((uint32_t *)(descriptor)) + __i),\t\\\n+\t\t\t*(((uint32_t *)(descriptor)) + __i));\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+}\n+/* Union describing a descriptor header.\n+ */\n+struct descriptor_header_s {\n+\tunion {\n+\t\tuint32_t word;\n+\t\tstruct {\n+\t\t\t/* 4 */ unsigned int ctype:5;\n+\t\t\t/* 5 */ unsigned int res1:2;\n+\t\t\t/* 7 */ unsigned int dnr:1;\n+\t\t\t/* 8 */ unsigned int one:1;\n+\t\t\t/* 9 */ unsigned int res2:1;\n+\t\t\t/* 10 */ unsigned int start_idx:6;\n+\t\t\t/* 16 */ unsigned int res3:2;\n+\t\t\t/* 18 */ unsigned int cif:1;\n+\t\t\t/* 19 */ unsigned int sc:1;\n+\t\t\t/* 20 */ unsigned int pd:1;\n+\t\t\t/* 21 */ unsigned int res4:1;\n+\t\t\t/* 22 */ unsigned int share:2;\n+\t\t\t/* 24 */ unsigned int res5:2;\n+\t\t\t/* 26 */ unsigned int desclen:6;\n+\t\t} sd;\n+\t\tstruct {\n+\t\t\t/* TODO only below struct members are corrected,\n+\t\t\t * all others also need to be reversed please verify it\n+\t\t\t */\n+\t\t\t/* 0 */ unsigned int desclen:7;\n+\t\t\t/* 7 */ unsigned int res4:1;\n+\t\t\t/* 8 */ unsigned int share:3;\n+\t\t\t/* 11 */ unsigned int reo:1;\n+\t\t\t/* 12 */ unsigned int shr:1;\n+\t\t\t/* 13 */ unsigned int mtd:1;\n+\t\t\t/* 14 */ unsigned int td:1;\n+\t\t\t/* 15 */ unsigned int zero:1;\n+\t\t\t/* 16 */ unsigned int shr_desc_len:6;\n+\t\t\t/* 22 */ unsigned int res2:1;\n+\t\t\t/* 23 */ unsigned int one:1;\n+\t\t\t/* 24 */ unsigned int dnr:1;\n+\t\t\t/* 25 */ unsigned int rsms:1;\n+\t\t\t/* 26 */ unsigned int res1:1;\n+\t\t\t/* 27 */ unsigned int ctype:5;\n+\t\t} jd;\n+\t} __rte_packed command;\n+} __rte_packed;\n+\n+/* Union describing a KEY command in a descriptor.\n+ */\n+struct key_command_s {\n+\tunion {\n+\t\tuint32_t word;\n+\t\tstruct {\n+\t\t\tunsigned int ctype:5;\n+\t\t\tunsigned int cls:2;\n+\t\t\tunsigned int sgf:1;\n+\t\t\tunsigned int imm:1;\n+\t\t\tunsigned int enc:1;\n+\t\t\tunsigned int nwb:1;\n+\t\t\tunsigned int ekt:1;\n+\t\t\tunsigned int kdest:4;\n+\t\t\tunsigned int tk:1;\n+\t\t\tunsigned int rsvd1:5;\n+\t\t\tunsigned int length:10;\n+\t\t} __rte_packed field;\n+\t} __rte_packed command;\n+} __rte_packed;\n+\n+/* Union describing a PROTOCOL command\n+ * in a descriptor.\n+ */\n+struct protocol_operation_command_s {\n+\tunion {\n+\t\tuint32_t word;\n+\t\tstruct {\n+\t\t\tunsigned int ctype:5;\n+\t\t\tunsigned int optype:3;\n+\t\t\tunsigned char protid;\n+\t\t\tunsigned short protinfo;\n+\t\t} __rte_packed field;\n+\t} __rte_packed command;\n+} __rte_packed;\n+\n+/* Union describing a SEQIN command in a\n+ * descriptor.\n+ */\n+struct seq_in_command_s {\n+\tunion {\n+\t\tuint32_t word;\n+\t\tstruct {\n+\t\t\tunsigned int ctype:5;\n+\t\t\tunsigned int res1:1;\n+\t\t\tunsigned int inl:1;\n+\t\t\tunsigned int sgf:1;\n+\t\t\tunsigned int pre:1;\n+\t\t\tunsigned int ext:1;\n+\t\t\tunsigned int rto:1;\n+\t\t\tunsigned int rjd:1;\n+\t\t\tunsigned int res2:4;\n+\t\t\tunsigned int length:16;\n+\t\t} field;\n+\t} __rte_packed command;\n+} __rte_packed;\n+\n+/* Union describing a SEQOUT command in a\n+ * descriptor.\n+ */\n+struct seq_out_command_s {\n+\tunion {\n+\t\tuint32_t word;\n+\t\tstruct {\n+\t\t\tunsigned int ctype:5;\n+\t\t\tunsigned int res1:2;\n+\t\t\tunsigned int sgf:1;\n+\t\t\tunsigned int pre:1;\n+\t\t\tunsigned int ext:1;\n+\t\t\tunsigned int rto:1;\n+\t\t\tunsigned int res2:5;\n+\t\t\tunsigned int length:16;\n+\t\t} field;\n+\t} __rte_packed command;\n+} __rte_packed;\n+\n+struct load_command_s {\n+\tunion {\n+\t\tuint32_t word;\n+\t\tstruct {\n+\t\t\tunsigned int ctype:5;\n+\t\t\tunsigned int class:2;\n+\t\t\tunsigned int sgf:1;\n+\t\t\tunsigned int imm:1;\n+\t\t\tunsigned int dst:7;\n+\t\t\tunsigned char offset;\n+\t\t\tunsigned char length;\n+\t\t} fields;\n+\t} __rte_packed command;\n+} __rte_packed;\n+\n+/* Structure encompassing a general shared descriptor of maximum\n+ * size (64 WORDs). Usually, other specific shared descriptor structures\n+ * will be type-casted to this one\n+ * this one.\n+ */\n+struct sec_sd_t {\n+\tuint32_t rsvd[MAX_DESC_SIZE_WORDS];\n+} __attribute__((packed, aligned(64)));\n+\n+/* Structure encompassing a job descriptor which processes\n+ * a single packet from a context. The job descriptor references\n+ * a shared descriptor from a SEC context.\n+ */\n+struct sec_job_descriptor_t {\n+\tstruct descriptor_header_s deschdr;\n+\tdma_addr_t sd_ptr;\n+\tstruct seq_out_command_s seq_out;\n+\tdma_addr_t seq_out_ptr;\n+\tuint32_t out_ext_length;\n+\tstruct seq_in_command_s seq_in;\n+\tdma_addr_t seq_in_ptr;\n+\tuint32_t in_ext_length;\n+\tstruct load_command_s load_dpovrd;\n+\tuint32_t dpovrd;\n+} __attribute__((packed, aligned(64)));\n+\n+#endif\n", "prefixes": [ "07/10" ] }