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{
    "id": 44482,
    "url": "http://patches.dpdk.org/api/patches/44482/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536572016-18134-14-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1536572016-18134-14-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1536572016-18134-14-git-send-email-arybchenko@solarflare.com",
    "date": "2018-09-10T09:33:12",
    "name": "[13/37] net/sfc/base: refactor monitors support",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "9a00e8c6083de50024a61b21f63581efed1b4d3c",
    "submitter": {
        "id": 607,
        "url": "http://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536572016-18134-14-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [
        {
            "id": 1244,
            "url": "http://patches.dpdk.org/api/series/1244/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1244",
            "date": "2018-09-10T09:33:01",
            "name": "net/sfc: update base driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/1244/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/44482/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/44482/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 61E3F5F28;\n\tMon, 10 Sep 2018 11:34:21 +0200 (CEST)",
            "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 578654CA0\n\tfor <dev@dpdk.org>; Mon, 10 Sep 2018 11:33:52 +0200 (CEST)",
            "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t7993E780055 for <dev@dpdk.org>; Mon, 10 Sep 2018 09:33:51 +0000 (UTC)",
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        ],
        "X-Virus-Scanned": "Proofpoint Essentials engine",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "CC": "Martin Harvey <mharvey@solarflare.com>",
        "Date": "Mon, 10 Sep 2018 10:33:12 +0100",
        "Message-ID": "<1536572016-18134-14-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1536572016-18134-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1536572016-18134-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.5.1010-24084.005",
        "X-TM-AS-Result": "No-11.710200-4.000000-10",
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        "X-MDID": "1536572032-ZsMzxJGhVhBb",
        "Subject": "[dpdk-dev] [PATCH 13/37] net/sfc/base: refactor monitors support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Martin Harvey <mharvey@solarflare.com>\n\nRemove obsolete monitor types since Falcon SFN4000 series adapters\nno longer supported by libefx.\nRename MCDI monitors to be consistent with YML.\nThe code may be simplified and generalized since only MCDI monitors\nremain.\n\nSigned-off-by: Martin Harvey <mharvey@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/efx.h      | 158 ++++----\n drivers/net/sfc/base/efx_mon.c  | 623 ++++++++++++++++++++++++++++----\n drivers/net/sfc/base/mcdi_mon.c | 187 ++--------\n 3 files changed, 695 insertions(+), 273 deletions(-)",
    "diff": "diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex 4c8983387..ffb6aad94 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -662,77 +662,74 @@ efx_mon_init(\n #define\tEFX_MON_STATS_PAGE_SIZE 0x100\n #define\tEFX_MON_MASK_ELEMENT_SIZE 32\n \n-/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */\n+/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */\n typedef enum efx_mon_stat_e {\n-\tEFX_MON_STAT_2_5V,\n-\tEFX_MON_STAT_VCCP1,\n-\tEFX_MON_STAT_VCC,\n-\tEFX_MON_STAT_5V,\n-\tEFX_MON_STAT_12V,\n-\tEFX_MON_STAT_VCCP2,\n-\tEFX_MON_STAT_EXT_TEMP,\n-\tEFX_MON_STAT_INT_TEMP,\n-\tEFX_MON_STAT_AIN1,\n-\tEFX_MON_STAT_AIN2,\n-\tEFX_MON_STAT_INT_COOLING,\n-\tEFX_MON_STAT_EXT_COOLING,\n-\tEFX_MON_STAT_1V,\n-\tEFX_MON_STAT_1_2V,\n-\tEFX_MON_STAT_1_8V,\n-\tEFX_MON_STAT_3_3V,\n-\tEFX_MON_STAT_1_2VA,\n-\tEFX_MON_STAT_VREF,\n-\tEFX_MON_STAT_VAOE,\n+\tEFX_MON_STAT_CONTROLLER_TEMP,\n+\tEFX_MON_STAT_PHY_COMMON_TEMP,\n+\tEFX_MON_STAT_CONTROLLER_COOLING,\n+\tEFX_MON_STAT_PHY0_TEMP,\n+\tEFX_MON_STAT_PHY0_COOLING,\n+\tEFX_MON_STAT_PHY1_TEMP,\n+\tEFX_MON_STAT_PHY1_COOLING,\n+\tEFX_MON_STAT_IN_1V0,\n+\tEFX_MON_STAT_IN_1V2,\n+\tEFX_MON_STAT_IN_1V8,\n+\tEFX_MON_STAT_IN_2V5,\n+\tEFX_MON_STAT_IN_3V3,\n+\tEFX_MON_STAT_IN_12V0,\n+\tEFX_MON_STAT_IN_1V2A,\n+\tEFX_MON_STAT_IN_VREF,\n+\tEFX_MON_STAT_OUT_VAOE,\n \tEFX_MON_STAT_AOE_TEMP,\n \tEFX_MON_STAT_PSU_AOE_TEMP,\n \tEFX_MON_STAT_PSU_TEMP,\n-\tEFX_MON_STAT_FAN0,\n-\tEFX_MON_STAT_FAN1,\n-\tEFX_MON_STAT_FAN2,\n-\tEFX_MON_STAT_FAN3,\n-\tEFX_MON_STAT_FAN4,\n-\tEFX_MON_STAT_VAOE_IN,\n-\tEFX_MON_STAT_IAOE,\n-\tEFX_MON_STAT_IAOE_IN,\n+\tEFX_MON_STAT_FAN_0,\n+\tEFX_MON_STAT_FAN_1,\n+\tEFX_MON_STAT_FAN_2,\n+\tEFX_MON_STAT_FAN_3,\n+\tEFX_MON_STAT_FAN_4,\n+\tEFX_MON_STAT_IN_VAOE,\n+\tEFX_MON_STAT_OUT_IAOE,\n+\tEFX_MON_STAT_IN_IAOE,\n \tEFX_MON_STAT_NIC_POWER,\n-\tEFX_MON_STAT_0_9V,\n-\tEFX_MON_STAT_I0_9V,\n-\tEFX_MON_STAT_I1_2V,\n-\tEFX_MON_STAT_0_9V_ADC,\n-\tEFX_MON_STAT_INT_TEMP2,\n-\tEFX_MON_STAT_VREG_TEMP,\n-\tEFX_MON_STAT_VREG_0_9V_TEMP,\n-\tEFX_MON_STAT_VREG_1_2V_TEMP,\n-\tEFX_MON_STAT_INT_VPTAT,\n-\tEFX_MON_STAT_INT_ADC_TEMP,\n-\tEFX_MON_STAT_EXT_VPTAT,\n-\tEFX_MON_STAT_EXT_ADC_TEMP,\n+\tEFX_MON_STAT_IN_0V9,\n+\tEFX_MON_STAT_IN_I0V9,\n+\tEFX_MON_STAT_IN_I1V2,\n+\tEFX_MON_STAT_IN_0V9_ADC,\n+\tEFX_MON_STAT_CONTROLLER_2_TEMP,\n+\tEFX_MON_STAT_VREG_INTERNAL_TEMP,\n+\tEFX_MON_STAT_VREG_0V9_TEMP,\n+\tEFX_MON_STAT_VREG_1V2_TEMP,\n+\tEFX_MON_STAT_CONTROLLER_VPTAT,\n+\tEFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,\n+\tEFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,\n+\tEFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,\n \tEFX_MON_STAT_AMBIENT_TEMP,\n \tEFX_MON_STAT_AIRFLOW,\n \tEFX_MON_STAT_VDD08D_VSS08D_CSR,\n \tEFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,\n \tEFX_MON_STAT_HOTPOINT_TEMP,\n-\tEFX_MON_STAT_PHY_POWER_SWITCH_PORT0,\n-\tEFX_MON_STAT_PHY_POWER_SWITCH_PORT1,\n+\tEFX_MON_STAT_PHY_POWER_PORT0,\n+\tEFX_MON_STAT_PHY_POWER_PORT1,\n \tEFX_MON_STAT_MUM_VCC,\n-\tEFX_MON_STAT_0V9_A,\n-\tEFX_MON_STAT_I0V9_A,\n-\tEFX_MON_STAT_0V9_A_TEMP,\n-\tEFX_MON_STAT_0V9_B,\n-\tEFX_MON_STAT_I0V9_B,\n-\tEFX_MON_STAT_0V9_B_TEMP,\n+\tEFX_MON_STAT_IN_0V9_A,\n+\tEFX_MON_STAT_IN_I0V9_A,\n+\tEFX_MON_STAT_VREG_0V9_A_TEMP,\n+\tEFX_MON_STAT_IN_0V9_B,\n+\tEFX_MON_STAT_IN_I0V9_B,\n+\tEFX_MON_STAT_VREG_0V9_B_TEMP,\n \tEFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,\n-\tEFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,\n+\tEFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,\n \tEFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,\n-\tEFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,\n+\tEFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,\n \tEFX_MON_STAT_CONTROLLER_MASTER_VPTAT,\n \tEFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,\n-\tEFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,\n-\tEFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,\n+\tEFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,\n+\tEFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,\n \tEFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,\n \tEFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,\n-\tEFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,\n-\tEFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,\n+\tEFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,\n+\tEFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,\n \tEFX_MON_STAT_SODIMM_VOUT,\n \tEFX_MON_STAT_SODIMM_0_TEMP,\n \tEFX_MON_STAT_SODIMM_1_TEMP,\n@@ -741,12 +738,12 @@ typedef enum efx_mon_stat_e {\n \tEFX_MON_STAT_CONTROLLER_TDIODE_TEMP,\n \tEFX_MON_STAT_BOARD_FRONT_TEMP,\n \tEFX_MON_STAT_BOARD_BACK_TEMP,\n-\tEFX_MON_STAT_I1V8,\n-\tEFX_MON_STAT_I2V5,\n-\tEFX_MON_STAT_I3V3,\n-\tEFX_MON_STAT_I12V0,\n-\tEFX_MON_STAT_1_3V,\n-\tEFX_MON_STAT_I1V3,\n+\tEFX_MON_STAT_IN_I1V8,\n+\tEFX_MON_STAT_IN_I2V5,\n+\tEFX_MON_STAT_IN_I3V3,\n+\tEFX_MON_STAT_IN_I12V0,\n+\tEFX_MON_STAT_IN_1V3,\n+\tEFX_MON_STAT_IN_I1V3,\n \tEFX_MON_NSTATS\n } efx_mon_stat_t;\n \n@@ -760,11 +757,33 @@ typedef enum efx_mon_stat_state_e {\n \tEFX_MON_STAT_STATE_NO_READING = 4,\n } efx_mon_stat_state_t;\n \n+typedef enum efx_mon_stat_unit_e {\n+\tEFX_MON_STAT_UNIT_UNKNOWN = 0,\n+\tEFX_MON_STAT_UNIT_BOOL,\n+\tEFX_MON_STAT_UNIT_TEMP_C,\n+\tEFX_MON_STAT_UNIT_VOLTAGE_MV,\n+\tEFX_MON_STAT_UNIT_CURRENT_MA,\n+\tEFX_MON_STAT_UNIT_POWER_W,\n+\tEFX_MON_STAT_UNIT_RPM,\n+\tEFX_MON_NUNITS\n+} efx_mon_stat_unit_t;\n+\n typedef struct efx_mon_stat_value_s {\n-\tuint16_t\temsv_value;\n-\tuint16_t\temsv_state;\n+\tuint16_t\t\temsv_value;\n+\tefx_mon_stat_state_t\temsv_state;\n+\tefx_mon_stat_unit_t\temsv_unit;\n } efx_mon_stat_value_t;\n \n+typedef enum efx_mon_stat_portmask_e {\n+\tEFX_MON_STAT_PORTMAP_NONE = 0,\n+\tEFX_MON_STAT_PORTMAP_PORT0 = 1,\n+\tEFX_MON_STAT_PORTMAP_PORT1 = 2,\n+\tEFX_MON_STAT_PORTMAP_PORT2 = 3,\n+\tEFX_MON_STAT_PORTMAP_PORT3 = 4,\n+\tEFX_MON_STAT_PORTMAP_ALL = (-1),\n+\tEFX_MON_STAT_PORTMAP_UNKNOWN = (-2)\n+} efx_mon_stat_portmask_t;\n+\n #if EFSYS_OPT_NAMES\n \n extern\t\t\t\t\tconst char *\n@@ -774,6 +793,21 @@ efx_mon_stat_name(\n \n #endif\t/* EFSYS_OPT_NAMES */\n \n+extern\t__checkReturn\t\t\tboolean_t\n+efx_mon_mcdi_to_efx_stat(\n+\t__in\t\t\t\tint mcdi_index,\n+\t__out\t\t\t\tefx_mon_stat_t *statp);\n+\n+extern\t__checkReturn\t\t\tboolean_t\n+efx_mon_get_stat_unit(\n+\t__in\t\t\t\tefx_mon_stat_t stat,\n+\t__out\t\t\t\tefx_mon_stat_unit_t *unitp);\n+\n+extern\t__checkReturn\t\t\tboolean_t\n+efx_mon_get_stat_portmap(\n+\t__in\t\t\t\tefx_mon_stat_t stat,\n+\t__out\t\t\t\tefx_mon_stat_portmask_t *maskp);\n+\n extern\t__checkReturn\t\t\tefx_rc_t\n efx_mon_stats_update(\n \t__in\t\t\t\tefx_nic_t *enp,\ndiff --git a/drivers/net/sfc/base/efx_mon.c b/drivers/net/sfc/base/efx_mon.c\nindex 9fc268ec1..34689921d 100644\n--- a/drivers/net/sfc/base/efx_mon.c\n+++ b/drivers/net/sfc/base/efx_mon.c\n@@ -99,77 +99,74 @@ efx_mon_init(\n \n #if EFSYS_OPT_NAMES\n \n-/* START MKCONFIG GENERATED MonitorStatNamesBlock 8150a068198c0f96 */\n+/* START MKCONFIG GENERATED MonitorStatNamesBlock 277c17eda1a6d1a4 */\n static const char * const __mon_stat_name[] = {\n-\t\"value_2_5v\",\n-\t\"value_vccp1\",\n-\t\"value_vcc\",\n-\t\"value_5v\",\n-\t\"value_12v\",\n-\t\"value_vccp2\",\n-\t\"value_ext_temp\",\n-\t\"value_int_temp\",\n-\t\"value_ain1\",\n-\t\"value_ain2\",\n+\t\"controller_temp\",\n+\t\"phy_common_temp\",\n \t\"controller_cooling\",\n-\t\"ext_cooling\",\n-\t\"1v\",\n-\t\"1_2v\",\n-\t\"1_8v\",\n-\t\"3_3v\",\n-\t\"1_2va\",\n-\t\"vref\",\n-\t\"vaoe\",\n-\t\"aoe_temperature\",\n-\t\"psu_aoe_temperature\",\n-\t\"psu_temperature\",\n-\t\"fan0\",\n-\t\"fan1\",\n-\t\"fan2\",\n-\t\"fan3\",\n-\t\"fan4\",\n-\t\"vaoe_in\",\n-\t\"iaoe\",\n-\t\"iaoe_in\",\n+\t\"phy0_temp\",\n+\t\"phy0_cooling\",\n+\t\"phy1_temp\",\n+\t\"phy1_cooling\",\n+\t\"in_1v0\",\n+\t\"in_1v2\",\n+\t\"in_1v8\",\n+\t\"in_2v5\",\n+\t\"in_3v3\",\n+\t\"in_12v0\",\n+\t\"in_1v2a\",\n+\t\"in_vref\",\n+\t\"out_vaoe\",\n+\t\"aoe_temp\",\n+\t\"psu_aoe_temp\",\n+\t\"psu_temp\",\n+\t\"fan_0\",\n+\t\"fan_1\",\n+\t\"fan_2\",\n+\t\"fan_3\",\n+\t\"fan_4\",\n+\t\"in_vaoe\",\n+\t\"out_iaoe\",\n+\t\"in_iaoe\",\n \t\"nic_power\",\n-\t\"0_9v\",\n-\t\"i0_9v\",\n-\t\"i1_2v\",\n-\t\"0_9v_adc\",\n-\t\"controller_temperature2\",\n-\t\"vreg_temperature\",\n-\t\"vreg_0_9v_temperature\",\n-\t\"vreg_1_2v_temperature\",\n-\t\"int_vptat\",\n-\t\"controller_internal_adc_temperature\",\n-\t\"ext_vptat\",\n-\t\"controller_external_adc_temperature\",\n-\t\"ambient_temperature\",\n+\t\"in_0v9\",\n+\t\"in_i0v9\",\n+\t\"in_i1v2\",\n+\t\"in_0v9_adc\",\n+\t\"controller_2_temp\",\n+\t\"vreg_internal_temp\",\n+\t\"vreg_0v9_temp\",\n+\t\"vreg_1v2_temp\",\n+\t\"controller_vptat\",\n+\t\"controller_internal_temp\",\n+\t\"controller_vptat_extadc\",\n+\t\"controller_internal_temp_extadc\",\n+\t\"ambient_temp\",\n \t\"airflow\",\n \t\"vdd08d_vss08d_csr\",\n \t\"vdd08d_vss08d_csr_extadc\",\n-\t\"hotpoint_temperature\",\n-\t\"phy_power_switch_port0\",\n-\t\"phy_power_switch_port1\",\n+\t\"hotpoint_temp\",\n+\t\"phy_power_port0\",\n+\t\"phy_power_port1\",\n \t\"mum_vcc\",\n-\t\"0v9_a\",\n-\t\"i0v9_a\",\n-\t\"0v9_a_temp\",\n-\t\"0v9_b\",\n-\t\"i0v9_b\",\n-\t\"0v9_b_temp\",\n+\t\"in_0v9_a\",\n+\t\"in_i0v9_a\",\n+\t\"vreg_0v9_a_temp\",\n+\t\"in_0v9_b\",\n+\t\"in_i0v9_b\",\n+\t\"vreg_0v9_b_temp\",\n \t\"ccom_avreg_1v2_supply\",\n-\t\"ccom_avreg_1v2_supply_ext_adc\",\n+\t\"ccom_avreg_1v2_supply_extadc\",\n \t\"ccom_avreg_1v8_supply\",\n-\t\"ccom_avreg_1v8_supply_ext_adc\",\n+\t\"ccom_avreg_1v8_supply_extadc\",\n \t\"controller_master_vptat\",\n \t\"controller_master_internal_temp\",\n-\t\"controller_master_vptat_ext_adc\",\n-\t\"controller_master_internal_temp_ext_adc\",\n+\t\"controller_master_vptat_extadc\",\n+\t\"controller_master_internal_temp_extadc\",\n \t\"controller_slave_vptat\",\n \t\"controller_slave_internal_temp\",\n-\t\"controller_slave_vptat_ext_adc\",\n-\t\"controller_slave_internal_temp_ext_adc\",\n+\t\"controller_slave_vptat_extadc\",\n+\t\"controller_slave_internal_temp_extadc\",\n \t\"sodimm_vout\",\n \t\"sodimm_0_temp\",\n \t\"sodimm_1_temp\",\n@@ -178,16 +175,514 @@ static const char * const __mon_stat_name[] = {\n \t\"controller_tdiode_temp\",\n \t\"board_front_temp\",\n \t\"board_back_temp\",\n-\t\"i1v8\",\n-\t\"i2v5\",\n-\t\"i3v3\",\n-\t\"i12v0\",\n-\t\"1v3\",\n-\t\"i1v3\",\n+\t\"in_i1v8\",\n+\t\"in_i2v5\",\n+\t\"in_i3v3\",\n+\t\"in_i12v0\",\n+\t\"in_1v3\",\n+\t\"in_i1v3\",\n };\n \n /* END MKCONFIG GENERATED MonitorStatNamesBlock */\n \n+/* START MKCONFIG GENERATED MonitorMcdiMappingBlock 362875db87a4e7da */\n+\t__checkReturn\t\t\tboolean_t\n+efx_mon_mcdi_to_efx_stat(\n+\t__in\t\t\t\tint mcdi_index,\n+\t__out\t\t\t\tefx_mon_stat_t *statp)\n+{\n+\n+\tif ((mcdi_index % (MC_CMD_SENSOR_PAGE0_NEXT + 1)) ==\n+\t    MC_CMD_SENSOR_PAGE0_NEXT) {\n+\t\t*statp = EFX_MON_NSTATS;\n+\t\treturn (B_FALSE);\n+\t}\n+\n+\tswitch (mcdi_index) {\n+\tcase MC_CMD_SENSOR_IN_I0V9:\n+\t\t*statp = EFX_MON_STAT_IN_I0V9;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PSU_TEMP:\n+\t\t*statp = EFX_MON_STAT_PSU_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_FAN_2:\n+\t\t*statp = EFX_MON_STAT_FAN_2;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_BOARD_BACK_TEMP:\n+\t\t*statp = EFX_MON_STAT_BOARD_BACK_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_1V3:\n+\t\t*statp = EFX_MON_STAT_IN_1V3;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_TDIODE_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_2V5:\n+\t\t*statp = EFX_MON_STAT_IN_2V5;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY_COMMON_TEMP:\n+\t\t*statp = EFX_MON_STAT_PHY_COMMON_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY1_TEMP:\n+\t\t*statp = EFX_MON_STAT_PHY1_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_VREG_INTERNAL_TEMP:\n+\t\t*statp = EFX_MON_STAT_VREG_INTERNAL_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_1V0:\n+\t\t*statp = EFX_MON_STAT_IN_1V0;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_FAN_1:\n+\t\t*statp = EFX_MON_STAT_FAN_1;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_1V2:\n+\t\t*statp = EFX_MON_STAT_IN_1V2;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_FAN_3:\n+\t\t*statp = EFX_MON_STAT_FAN_3;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_1V2A:\n+\t\t*statp = EFX_MON_STAT_IN_1V2A;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_SODIMM_0_TEMP:\n+\t\t*statp = EFX_MON_STAT_SODIMM_0_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_1V8:\n+\t\t*statp = EFX_MON_STAT_IN_1V8;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_VREF:\n+\t\t*statp = EFX_MON_STAT_IN_VREF;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_SODIMM_VOUT:\n+\t\t*statp = EFX_MON_STAT_SODIMM_VOUT;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY:\n+\t\t*statp = EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I1V2:\n+\t\t*statp = EFX_MON_STAT_IN_I1V2;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I1V3:\n+\t\t*statp = EFX_MON_STAT_IN_I1V3;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_AIRFLOW:\n+\t\t*statp = EFX_MON_STAT_AIRFLOW;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_HOTPOINT_TEMP:\n+\t\t*statp = EFX_MON_STAT_HOTPOINT_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_VDD08D_VSS08D_CSR:\n+\t\t*statp = EFX_MON_STAT_VDD08D_VSS08D_CSR;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_AOE_TEMP:\n+\t\t*statp = EFX_MON_STAT_AOE_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I1V8:\n+\t\t*statp = EFX_MON_STAT_IN_I1V8;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I2V5:\n+\t\t*statp = EFX_MON_STAT_IN_I2V5;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY1_COOLING:\n+\t\t*statp = EFX_MON_STAT_PHY1_COOLING;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_0V9_ADC:\n+\t\t*statp = EFX_MON_STAT_IN_0V9_ADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_VREG_0V9_A_TEMP:\n+\t\t*statp = EFX_MON_STAT_VREG_0V9_A_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_MASTER_VPTAT;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY0_VCC:\n+\t\t*statp = EFX_MON_STAT_PHY0_VCC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY0_COOLING:\n+\t\t*statp = EFX_MON_STAT_PHY0_COOLING;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PSU_AOE_TEMP:\n+\t\t*statp = EFX_MON_STAT_PSU_AOE_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_VREG_0V9_TEMP:\n+\t\t*statp = EFX_MON_STAT_VREG_0V9_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I0V9_A:\n+\t\t*statp = EFX_MON_STAT_IN_I0V9_A;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I3V3:\n+\t\t*statp = EFX_MON_STAT_IN_I3V3;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_BOARD_FRONT_TEMP:\n+\t\t*statp = EFX_MON_STAT_BOARD_FRONT_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_OUT_VAOE:\n+\t\t*statp = EFX_MON_STAT_OUT_VAOE;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC:\n+\t\t*statp = EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I12V0:\n+\t\t*statp = EFX_MON_STAT_IN_I12V0;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY_POWER_PORT1:\n+\t\t*statp = EFX_MON_STAT_PHY_POWER_PORT1;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY_POWER_PORT0:\n+\t\t*statp = EFX_MON_STAT_PHY_POWER_PORT0;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_TEMP:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_IAOE:\n+\t\t*statp = EFX_MON_STAT_IN_IAOE;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_VAOE:\n+\t\t*statp = EFX_MON_STAT_IN_VAOE;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY:\n+\t\t*statp = EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY1_VCC:\n+\t\t*statp = EFX_MON_STAT_PHY1_VCC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_COOLING:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_COOLING;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_AMBIENT_TEMP:\n+\t\t*statp = EFX_MON_STAT_AMBIENT_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_3V3:\n+\t\t*statp = EFX_MON_STAT_IN_3V3;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_PHY0_TEMP:\n+\t\t*statp = EFX_MON_STAT_PHY0_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_SODIMM_1_TEMP:\n+\t\t*statp = EFX_MON_STAT_SODIMM_1_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_MUM_VCC:\n+\t\t*statp = EFX_MON_STAT_MUM_VCC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_VREG_0V9_B_TEMP:\n+\t\t*statp = EFX_MON_STAT_VREG_0V9_B_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_FAN_4:\n+\t\t*statp = EFX_MON_STAT_FAN_4;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_2_TEMP:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_2_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_0V9_A:\n+\t\t*statp = EFX_MON_STAT_IN_0V9_A;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_0V9:\n+\t\t*statp = EFX_MON_STAT_IN_0V9;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_I0V9_B:\n+\t\t*statp = EFX_MON_STAT_IN_I0V9_B;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_NIC_POWER:\n+\t\t*statp = EFX_MON_STAT_NIC_POWER;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_12V0:\n+\t\t*statp = EFX_MON_STAT_IN_12V0;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_OUT_IAOE:\n+\t\t*statp = EFX_MON_STAT_OUT_IAOE;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_VPTAT:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_VPTAT;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP:\n+\t\t*statp = EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_FAN_0:\n+\t\t*statp = EFX_MON_STAT_FAN_0;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_VREG_1V2_TEMP:\n+\t\t*statp = EFX_MON_STAT_VREG_1V2_TEMP;\n+\t\tbreak;\n+\tcase MC_CMD_SENSOR_IN_0V9_B:\n+\t\t*statp = EFX_MON_STAT_IN_0V9_B;\n+\t\tbreak;\n+\tdefault:\n+\t\t*statp = EFX_MON_NSTATS;\n+\t\tbreak;\n+\t};\n+\n+\tif (*statp == EFX_MON_NSTATS)\n+\t\tgoto fail1;\n+\n+\treturn (B_TRUE);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, boolean_t, B_TRUE);\n+\treturn (B_FALSE);\n+};\n+\n+/* END MKCONFIG GENERATED MonitorMcdiMappingBlock */\n+\n+/* START MKCONFIG GENERATED MonitorStatisticUnitsBlock 2d447c656cc2d01d */\n+\t__checkReturn\t\t\tboolean_t\n+efx_mon_get_stat_unit(\n+\t__in\t\t\t\tefx_mon_stat_t stat,\n+\t__out\t\t\t\tefx_mon_stat_unit_t *unitp)\n+{\n+\tswitch (stat) {\n+\tcase EFX_MON_STAT_IN_1V0:\n+\tcase EFX_MON_STAT_IN_1V2:\n+\tcase EFX_MON_STAT_IN_1V8:\n+\tcase EFX_MON_STAT_IN_2V5:\n+\tcase EFX_MON_STAT_IN_3V3:\n+\tcase EFX_MON_STAT_IN_12V0:\n+\tcase EFX_MON_STAT_IN_1V2A:\n+\tcase EFX_MON_STAT_IN_VREF:\n+\tcase EFX_MON_STAT_OUT_VAOE:\n+\tcase EFX_MON_STAT_IN_VAOE:\n+\tcase EFX_MON_STAT_IN_0V9:\n+\tcase EFX_MON_STAT_IN_0V9_ADC:\n+\tcase EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC:\n+\tcase EFX_MON_STAT_VDD08D_VSS08D_CSR:\n+\tcase EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC:\n+\tcase EFX_MON_STAT_MUM_VCC:\n+\tcase EFX_MON_STAT_IN_0V9_A:\n+\tcase EFX_MON_STAT_IN_0V9_B:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_VPTAT:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC:\n+\tcase EFX_MON_STAT_SODIMM_VOUT:\n+\tcase EFX_MON_STAT_PHY0_VCC:\n+\tcase EFX_MON_STAT_PHY1_VCC:\n+\tcase EFX_MON_STAT_IN_1V3:\n+\t\t*unitp = EFX_MON_STAT_UNIT_VOLTAGE_MV;\n+\t\tbreak;\n+\tcase EFX_MON_STAT_CONTROLLER_TEMP:\n+\tcase EFX_MON_STAT_PHY_COMMON_TEMP:\n+\tcase EFX_MON_STAT_PHY0_TEMP:\n+\tcase EFX_MON_STAT_PHY1_TEMP:\n+\tcase EFX_MON_STAT_AOE_TEMP:\n+\tcase EFX_MON_STAT_PSU_AOE_TEMP:\n+\tcase EFX_MON_STAT_PSU_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_2_TEMP:\n+\tcase EFX_MON_STAT_VREG_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_VREG_0V9_TEMP:\n+\tcase EFX_MON_STAT_VREG_1V2_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_VPTAT:\n+\tcase EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC:\n+\tcase EFX_MON_STAT_AMBIENT_TEMP:\n+\tcase EFX_MON_STAT_HOTPOINT_TEMP:\n+\tcase EFX_MON_STAT_VREG_0V9_A_TEMP:\n+\tcase EFX_MON_STAT_VREG_0V9_B_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC:\n+\tcase EFX_MON_STAT_SODIMM_0_TEMP:\n+\tcase EFX_MON_STAT_SODIMM_1_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_TDIODE_TEMP:\n+\tcase EFX_MON_STAT_BOARD_FRONT_TEMP:\n+\tcase EFX_MON_STAT_BOARD_BACK_TEMP:\n+\t\t*unitp = EFX_MON_STAT_UNIT_TEMP_C;\n+\t\tbreak;\n+\tcase EFX_MON_STAT_CONTROLLER_COOLING:\n+\tcase EFX_MON_STAT_PHY0_COOLING:\n+\tcase EFX_MON_STAT_PHY1_COOLING:\n+\tcase EFX_MON_STAT_AIRFLOW:\n+\tcase EFX_MON_STAT_PHY_POWER_PORT0:\n+\tcase EFX_MON_STAT_PHY_POWER_PORT1:\n+\t\t*unitp = EFX_MON_STAT_UNIT_BOOL;\n+\t\tbreak;\n+\tcase EFX_MON_STAT_NIC_POWER:\n+\t\t*unitp = EFX_MON_STAT_UNIT_POWER_W;\n+\t\tbreak;\n+\tcase EFX_MON_STAT_OUT_IAOE:\n+\tcase EFX_MON_STAT_IN_IAOE:\n+\tcase EFX_MON_STAT_IN_I0V9:\n+\tcase EFX_MON_STAT_IN_I1V2:\n+\tcase EFX_MON_STAT_IN_I0V9_A:\n+\tcase EFX_MON_STAT_IN_I0V9_B:\n+\tcase EFX_MON_STAT_IN_I1V8:\n+\tcase EFX_MON_STAT_IN_I2V5:\n+\tcase EFX_MON_STAT_IN_I3V3:\n+\tcase EFX_MON_STAT_IN_I12V0:\n+\tcase EFX_MON_STAT_IN_I1V3:\n+\t\t*unitp = EFX_MON_STAT_UNIT_CURRENT_MA;\n+\t\tbreak;\n+\tcase EFX_MON_STAT_FAN_0:\n+\tcase EFX_MON_STAT_FAN_1:\n+\tcase EFX_MON_STAT_FAN_2:\n+\tcase EFX_MON_STAT_FAN_3:\n+\tcase EFX_MON_STAT_FAN_4:\n+\t\t*unitp = EFX_MON_STAT_UNIT_RPM;\n+\t\tbreak;\n+\tdefault:\n+\t\t*unitp = EFX_MON_STAT_UNIT_UNKNOWN;\n+\t\tbreak;\n+\t};\n+\n+\tif (*unitp == EFX_MON_STAT_UNIT_UNKNOWN)\n+\t\tgoto fail1;\n+\n+\treturn (B_TRUE);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, boolean_t, B_TRUE);\n+\treturn (B_FALSE);\n+};\n+\n+/* END MKCONFIG GENERATED MonitorStatisticUnitsBlock */\n+\n+/* START MKCONFIG GENERATED MonitorStatisticPortsBlock 1719b751d842534f */\n+\t__checkReturn\t\t\tboolean_t\n+efx_mon_get_stat_portmap(\n+\t__in\t\t\t\tefx_mon_stat_t stat,\n+\t__out\t\t\t\tefx_mon_stat_portmask_t *maskp)\n+{\n+\n+\tswitch (stat) {\n+\tcase EFX_MON_STAT_PHY1_TEMP:\n+\tcase EFX_MON_STAT_PHY1_COOLING:\n+\tcase EFX_MON_STAT_PHY_POWER_PORT1:\n+\t\t*maskp = EFX_MON_STAT_PORTMAP_PORT1;\n+\t\tbreak;\n+\tcase EFX_MON_STAT_CONTROLLER_TEMP:\n+\tcase EFX_MON_STAT_PHY_COMMON_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_COOLING:\n+\tcase EFX_MON_STAT_IN_1V0:\n+\tcase EFX_MON_STAT_IN_1V2:\n+\tcase EFX_MON_STAT_IN_1V8:\n+\tcase EFX_MON_STAT_IN_2V5:\n+\tcase EFX_MON_STAT_IN_3V3:\n+\tcase EFX_MON_STAT_IN_12V0:\n+\tcase EFX_MON_STAT_IN_1V2A:\n+\tcase EFX_MON_STAT_IN_VREF:\n+\tcase EFX_MON_STAT_OUT_VAOE:\n+\tcase EFX_MON_STAT_AOE_TEMP:\n+\tcase EFX_MON_STAT_PSU_AOE_TEMP:\n+\tcase EFX_MON_STAT_PSU_TEMP:\n+\tcase EFX_MON_STAT_FAN_0:\n+\tcase EFX_MON_STAT_FAN_1:\n+\tcase EFX_MON_STAT_FAN_2:\n+\tcase EFX_MON_STAT_FAN_3:\n+\tcase EFX_MON_STAT_FAN_4:\n+\tcase EFX_MON_STAT_IN_VAOE:\n+\tcase EFX_MON_STAT_OUT_IAOE:\n+\tcase EFX_MON_STAT_IN_IAOE:\n+\tcase EFX_MON_STAT_NIC_POWER:\n+\tcase EFX_MON_STAT_IN_0V9:\n+\tcase EFX_MON_STAT_IN_I0V9:\n+\tcase EFX_MON_STAT_IN_I1V2:\n+\tcase EFX_MON_STAT_IN_0V9_ADC:\n+\tcase EFX_MON_STAT_CONTROLLER_2_TEMP:\n+\tcase EFX_MON_STAT_VREG_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_VREG_0V9_TEMP:\n+\tcase EFX_MON_STAT_VREG_1V2_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_VPTAT:\n+\tcase EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC:\n+\tcase EFX_MON_STAT_AMBIENT_TEMP:\n+\tcase EFX_MON_STAT_AIRFLOW:\n+\tcase EFX_MON_STAT_VDD08D_VSS08D_CSR:\n+\tcase EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC:\n+\tcase EFX_MON_STAT_HOTPOINT_TEMP:\n+\tcase EFX_MON_STAT_MUM_VCC:\n+\tcase EFX_MON_STAT_IN_0V9_A:\n+\tcase EFX_MON_STAT_IN_I0V9_A:\n+\tcase EFX_MON_STAT_VREG_0V9_A_TEMP:\n+\tcase EFX_MON_STAT_IN_0V9_B:\n+\tcase EFX_MON_STAT_IN_I0V9_B:\n+\tcase EFX_MON_STAT_VREG_0V9_B_TEMP:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY:\n+\tcase EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_VPTAT:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC:\n+\tcase EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC:\n+\tcase EFX_MON_STAT_SODIMM_VOUT:\n+\tcase EFX_MON_STAT_SODIMM_0_TEMP:\n+\tcase EFX_MON_STAT_SODIMM_1_TEMP:\n+\tcase EFX_MON_STAT_PHY0_VCC:\n+\tcase EFX_MON_STAT_PHY1_VCC:\n+\tcase EFX_MON_STAT_CONTROLLER_TDIODE_TEMP:\n+\tcase EFX_MON_STAT_BOARD_FRONT_TEMP:\n+\tcase EFX_MON_STAT_BOARD_BACK_TEMP:\n+\tcase EFX_MON_STAT_IN_I1V8:\n+\tcase EFX_MON_STAT_IN_I2V5:\n+\tcase EFX_MON_STAT_IN_I3V3:\n+\tcase EFX_MON_STAT_IN_I12V0:\n+\tcase EFX_MON_STAT_IN_1V3:\n+\tcase EFX_MON_STAT_IN_I1V3:\n+\t\t*maskp = EFX_MON_STAT_PORTMAP_ALL;\n+\t\tbreak;\n+\tcase EFX_MON_STAT_PHY0_TEMP:\n+\tcase EFX_MON_STAT_PHY0_COOLING:\n+\tcase EFX_MON_STAT_PHY_POWER_PORT0:\n+\t\t*maskp = EFX_MON_STAT_PORTMAP_PORT0;\n+\t\tbreak;\n+\tdefault:\n+\t\t*maskp = EFX_MON_STAT_PORTMAP_UNKNOWN;\n+\t\tbreak;\n+\t};\n+\n+\tif (*maskp == EFX_MON_STAT_PORTMAP_UNKNOWN)\n+\t\tgoto fail1;\n+\n+\treturn (B_TRUE);\n+\n+fail1:\n+\tEFSYS_PROBE1(fail1, boolean_t, B_TRUE);\n+\treturn (B_FALSE);\n+};\n+\n+/* END MKCONFIG GENERATED MonitorStatisticPortsBlock */\n+\n extern\t\t\t\t\tconst char *\n efx_mon_stat_name(\n \t__in\t\t\t\tefx_nic_t *enp,\ndiff --git a/drivers/net/sfc/base/mcdi_mon.c b/drivers/net/sfc/base/mcdi_mon.c\nindex 8c0b6f0d9..93e6b1e35 100644\n--- a/drivers/net/sfc/base/mcdi_mon.c\n+++ b/drivers/net/sfc/base/mcdi_mon.c\n@@ -12,136 +12,9 @@\n \n #if EFSYS_OPT_MON_STATS\n \n-#define\tMCDI_MON_NEXT_PAGE  ((uint16_t)0xfffe)\n-#define\tMCDI_MON_INVALID_SENSOR ((uint16_t)0xfffd)\n-#define\tMCDI_MON_PAGE_SIZE 0x20\n-\n-/* Bitmasks of valid port(s) for each sensor */\n-#define\tMCDI_MON_PORT_NONE\t(0x00)\n-#define\tMCDI_MON_PORT_P1\t(0x01)\n-#define\tMCDI_MON_PORT_P2\t(0x02)\n-#define\tMCDI_MON_PORT_P3\t(0x04)\n-#define\tMCDI_MON_PORT_P4\t(0x08)\n-#define\tMCDI_MON_PORT_Px\t(0xFFFF)\n-\n /* Get port mask from one-based MCDI port number */\n #define\tMCDI_MON_PORT_MASK(_emip) (1U << ((_emip)->emi_port - 1))\n \n-/* Entry for MCDI sensor in sensor map */\n-#define\tSTAT(portmask, stat)\t\\\n-\t{ (MCDI_MON_PORT_##portmask), (EFX_MON_STAT_##stat) }\n-\n-/* Entry for sensor next page flag in sensor map */\n-#define\tSTAT_NEXT_PAGE()\t\\\n-\t{ MCDI_MON_PORT_NONE, MCDI_MON_NEXT_PAGE }\n-\n-/* Placeholder for gaps in the array */\n-#define\tSTAT_NO_SENSOR()\t\\\n-\t{ MCDI_MON_PORT_NONE, MCDI_MON_INVALID_SENSOR }\n-\n-/* Map from MC sensors to monitor statistics */\n-static const struct mcdi_sensor_map_s {\n-\tuint16_t\tmsm_port_mask;\n-\tuint16_t\tmsm_stat;\n-} mcdi_sensor_map[] = {\n-\t/* Sensor page 0\t\tMC_CMD_SENSOR_xxx */\n-\tSTAT(Px, INT_TEMP),\t\t/* 0x00 CONTROLLER_TEMP */\n-\tSTAT(Px, EXT_TEMP),\t\t/* 0x01 PHY_COMMON_TEMP */\n-\tSTAT(Px, INT_COOLING),\t\t/* 0x02 CONTROLLER_COOLING */\n-\tSTAT(P1, EXT_TEMP),\t\t/* 0x03 PHY0_TEMP */\n-\tSTAT(P1, EXT_COOLING),\t\t/* 0x04 PHY0_COOLING */\n-\tSTAT(P2, EXT_TEMP),\t\t/* 0x05 PHY1_TEMP */\n-\tSTAT(P2, EXT_COOLING),\t\t/* 0x06 PHY1_COOLING */\n-\tSTAT(Px, 1V),\t\t\t/* 0x07 IN_1V0 */\n-\tSTAT(Px, 1_2V),\t\t\t/* 0x08 IN_1V2 */\n-\tSTAT(Px, 1_8V),\t\t\t/* 0x09 IN_1V8 */\n-\tSTAT(Px, 2_5V),\t\t\t/* 0x0a IN_2V5 */\n-\tSTAT(Px, 3_3V),\t\t\t/* 0x0b IN_3V3 */\n-\tSTAT(Px, 12V),\t\t\t/* 0x0c IN_12V0 */\n-\tSTAT(Px, 1_2VA),\t\t/* 0x0d IN_1V2A */\n-\tSTAT(Px, VREF),\t\t\t/* 0x0e IN_VREF */\n-\tSTAT(Px, VAOE),\t\t\t/* 0x0f OUT_VAOE */\n-\tSTAT(Px, AOE_TEMP),\t\t/* 0x10 AOE_TEMP */\n-\tSTAT(Px, PSU_AOE_TEMP),\t\t/* 0x11 PSU_AOE_TEMP */\n-\tSTAT(Px, PSU_TEMP),\t\t/* 0x12 PSU_TEMP */\n-\tSTAT(Px, FAN0),\t\t\t/* 0x13 FAN_0 */\n-\tSTAT(Px, FAN1),\t\t\t/* 0x14 FAN_1 */\n-\tSTAT(Px, FAN2),\t\t\t/* 0x15 FAN_2 */\n-\tSTAT(Px, FAN3),\t\t\t/* 0x16 FAN_3 */\n-\tSTAT(Px, FAN4),\t\t\t/* 0x17 FAN_4 */\n-\tSTAT(Px, VAOE_IN),\t\t/* 0x18 IN_VAOE */\n-\tSTAT(Px, IAOE),\t\t\t/* 0x19 OUT_IAOE */\n-\tSTAT(Px, IAOE_IN),\t\t/* 0x1a IN_IAOE */\n-\tSTAT(Px, NIC_POWER),\t\t/* 0x1b NIC_POWER */\n-\tSTAT(Px, 0_9V),\t\t\t/* 0x1c IN_0V9 */\n-\tSTAT(Px, I0_9V),\t\t/* 0x1d IN_I0V9 */\n-\tSTAT(Px, I1_2V),\t\t/* 0x1e IN_I1V2 */\n-\tSTAT_NEXT_PAGE(),\t\t/* 0x1f Next page flag (not a sensor) */\n-\n-\t/* Sensor page 1\t\tMC_CMD_SENSOR_xxx */\n-\tSTAT(Px, 0_9V_ADC),\t\t/* 0x20 IN_0V9_ADC */\n-\tSTAT(Px, INT_TEMP2),\t\t/* 0x21 CONTROLLER_2_TEMP */\n-\tSTAT(Px, VREG_TEMP),\t\t/* 0x22 VREG_INTERNAL_TEMP */\n-\tSTAT(Px, VREG_0_9V_TEMP),\t/* 0x23 VREG_0V9_TEMP */\n-\tSTAT(Px, VREG_1_2V_TEMP),\t/* 0x24 VREG_1V2_TEMP */\n-\tSTAT(Px, INT_VPTAT),\t\t/* 0x25 CTRLR. VPTAT */\n-\tSTAT(Px, INT_ADC_TEMP),\t\t/* 0x26 CTRLR. INTERNAL_TEMP */\n-\tSTAT(Px, EXT_VPTAT),\t\t/* 0x27 CTRLR. VPTAT_EXTADC */\n-\tSTAT(Px, EXT_ADC_TEMP),\t\t/* 0x28 CTRLR. INTERNAL_TEMP_EXTADC */\n-\tSTAT(Px, AMBIENT_TEMP),\t\t/* 0x29 AMBIENT_TEMP */\n-\tSTAT(Px, AIRFLOW),\t\t/* 0x2a AIRFLOW */\n-\tSTAT(Px, VDD08D_VSS08D_CSR),\t/* 0x2b VDD08D_VSS08D_CSR */\n-\tSTAT(Px, VDD08D_VSS08D_CSR_EXTADC), /* 0x2c VDD08D_VSS08D_CSR_EXTADC */\n-\tSTAT(Px, HOTPOINT_TEMP),\t/* 0x2d HOTPOINT_TEMP */\n-\tSTAT(P1, PHY_POWER_SWITCH_PORT0),   /* 0x2e PHY_POWER_SWITCH_PORT0 */\n-\tSTAT(P2, PHY_POWER_SWITCH_PORT1),   /* 0x2f PHY_POWER_SWITCH_PORT1 */\n-\tSTAT(Px, MUM_VCC),\t\t/* 0x30 MUM_VCC */\n-\tSTAT(Px, 0V9_A),\t\t/* 0x31 0V9_A */\n-\tSTAT(Px, I0V9_A),\t\t/* 0x32 I0V9_A */\n-\tSTAT(Px, 0V9_A_TEMP),\t\t/* 0x33 0V9_A_TEMP */\n-\tSTAT(Px, 0V9_B),\t\t/* 0x34 0V9_B */\n-\tSTAT(Px, I0V9_B),\t\t/* 0x35 I0V9_B */\n-\tSTAT(Px, 0V9_B_TEMP),\t\t/* 0x36 0V9_B_TEMP */\n-\tSTAT(Px, CCOM_AVREG_1V2_SUPPLY),  /* 0x37 CCOM_AVREG_1V2_SUPPLY */\n-\tSTAT(Px, CCOM_AVREG_1V2_SUPPLY_EXT_ADC),\n-\t\t\t\t\t/* 0x38 CCOM_AVREG_1V2_SUPPLY_EXT_ADC */\n-\tSTAT(Px, CCOM_AVREG_1V8_SUPPLY),  /* 0x39 CCOM_AVREG_1V8_SUPPLY */\n-\tSTAT(Px, CCOM_AVREG_1V8_SUPPLY_EXT_ADC),\n-\t\t\t\t\t/* 0x3a CCOM_AVREG_1V8_SUPPLY_EXT_ADC */\n-\tSTAT_NO_SENSOR(),\t\t/* 0x3b (no sensor) */\n-\tSTAT_NO_SENSOR(),\t\t/* 0x3c (no sensor) */\n-\tSTAT_NO_SENSOR(),\t\t/* 0x3d (no sensor) */\n-\tSTAT_NO_SENSOR(),\t\t/* 0x3e (no sensor) */\n-\tSTAT_NEXT_PAGE(),\t\t/* 0x3f Next page flag (not a sensor) */\n-\n-\t/* Sensor page 2\t\tMC_CMD_SENSOR_xxx */\n-\tSTAT(Px, CONTROLLER_MASTER_VPTAT),\t   /* 0x40 MASTER_VPTAT */\n-\tSTAT(Px, CONTROLLER_MASTER_INTERNAL_TEMP), /* 0x41 MASTER_INT_TEMP */\n-\tSTAT(Px, CONTROLLER_MASTER_VPTAT_EXT_ADC), /* 0x42 MAST_VPTAT_EXT_ADC */\n-\tSTAT(Px, CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC),\n-\t\t\t\t\t/* 0x43 MASTER_INTERNAL_TEMP_EXT_ADC */\n-\tSTAT(Px, CONTROLLER_SLAVE_VPTAT),\t  /* 0x44 SLAVE_VPTAT */\n-\tSTAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP), /* 0x45 SLAVE_INTERNAL_TEMP */\n-\tSTAT(Px, CONTROLLER_SLAVE_VPTAT_EXT_ADC), /* 0x46 SLAVE_VPTAT_EXT_ADC */\n-\tSTAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC),\n-\t\t\t\t\t/* 0x47 SLAVE_INTERNAL_TEMP_EXT_ADC */\n-\tSTAT_NO_SENSOR(),\t\t/* 0x48 (no sensor) */\n-\tSTAT(Px, SODIMM_VOUT),\t\t/* 0x49 SODIMM_VOUT */\n-\tSTAT(Px, SODIMM_0_TEMP),\t/* 0x4a SODIMM_0_TEMP */\n-\tSTAT(Px, SODIMM_1_TEMP),\t/* 0x4b SODIMM_1_TEMP */\n-\tSTAT(Px, PHY0_VCC),\t\t/* 0x4c PHY0_VCC */\n-\tSTAT(Px, PHY1_VCC),\t\t/* 0x4d PHY1_VCC */\n-\tSTAT(Px, CONTROLLER_TDIODE_TEMP), /* 0x4e CONTROLLER_TDIODE_TEMP */\n-\tSTAT(Px, BOARD_FRONT_TEMP),\t/* 0x4f BOARD_FRONT_TEMP */\n-\tSTAT(Px, BOARD_BACK_TEMP),\t/* 0x50 BOARD_BACK_TEMP */\n-\tSTAT(Px, I1V8),\t\t\t/* 0x51 IN_I1V8 */\n-\tSTAT(Px, I2V5),\t\t\t/* 0x52 IN_I2V5 */\n-\tSTAT(Px, I3V3),\t\t\t/* 0x53 IN_I3V3 */\n-\tSTAT(Px, I12V0),\t\t/* 0x54 IN_I12V0 */\n-\tSTAT(Px, 1_3V),\t\t\t/* 0x55 IN_1V3 */\n-\tSTAT(Px, I1V3),\t\t\t/* 0x56 IN_I1V3 */\n-};\n-\n #define\tMCDI_STATIC_SENSOR_ASSERT(_field)\t\t\t\t\\\n \tEFX_STATIC_ASSERT(MC_CMD_SENSOR_STATE_ ## _field\t\t\\\n \t\t\t    == EFX_MON_STAT_STATE_ ## _field)\n@@ -156,10 +29,10 @@ mcdi_mon_decode_stats(\n \t__inout_ecount_opt(EFX_MON_NSTATS)\tefx_mon_stat_value_t *stat)\n {\n \tefx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);\n-\tuint16_t port_mask;\n+\tefx_mon_stat_portmask_t port_mask;\n \tuint16_t sensor;\n \tsize_t sensor_max;\n-\tuint32_t stat_mask[(EFX_ARRAY_SIZE(mcdi_sensor_map) + 31) / 32];\n+\tuint32_t stat_mask[(EFX_MON_NSTATS + 31) / 32];\n \tuint32_t idx = 0;\n \tuint32_t page = 0;\n \n@@ -170,13 +43,10 @@ mcdi_mon_decode_stats(\n \tMCDI_STATIC_SENSOR_ASSERT(BROKEN);\n \tMCDI_STATIC_SENSOR_ASSERT(NO_READING);\n \n-\tEFX_STATIC_ASSERT(sizeof (stat_mask[0]) * 8 ==\n-\t    EFX_MON_MASK_ELEMENT_SIZE);\n-\tsensor_max =\n-\t    MIN((8 * sensor_mask_size), EFX_ARRAY_SIZE(mcdi_sensor_map));\n+\tsensor_max = 8 * sensor_mask_size;\n \n \tEFSYS_ASSERT(emip->emi_port > 0); /* MCDI port number is one-based */\n-\tport_mask = MCDI_MON_PORT_MASK(emip);\n+\tport_mask = (efx_mon_stat_portmask_t)MCDI_MON_PORT_MASK(emip);\n \n \tmemset(stat_mask, 0, sizeof (stat_mask));\n \n@@ -191,19 +61,36 @@ mcdi_mon_decode_stats(\n \t * does not understand.\n \t */\n \tfor (sensor = 0; sensor < sensor_max; ++sensor) {\n-\t\tefx_mon_stat_t id = mcdi_sensor_map[sensor].msm_stat;\n+\t\tefx_mon_stat_t id;\n+\t\tefx_mon_stat_portmask_t stat_portmask = 0;\n+\t\tboolean_t decode_ok;\n+\t\tefx_mon_stat_unit_t stat_unit;\n \n-\t\tif ((sensor % MCDI_MON_PAGE_SIZE) == MC_CMD_SENSOR_PAGE0_NEXT) {\n-\t\t\tEFSYS_ASSERT3U(id, ==, MCDI_MON_NEXT_PAGE);\n+\t\tif ((sensor % (MC_CMD_SENSOR_PAGE0_NEXT + 1)) ==\n+\t\t    MC_CMD_SENSOR_PAGE0_NEXT) {\n \t\t\tpage++;\n \t\t\tcontinue;\n+\t\t\t/* This sensor is one of the page boundary bits. */\n \t\t}\n+\n \t\tif (~(sensor_mask[page]) & (1U << sensor))\n \t\t\tcontinue;\n+\t\t/* This sensor not in DMA buffer */\n+\n \t\tidx++;\n+\t\t/*\n+\t\t * Valid stat in DMA buffer that we need to increment over, even\n+\t\t * if we couldn't look up the id\n+\t\t */\n+\n+\t\tdecode_ok = efx_mon_mcdi_to_efx_stat(sensor, &id);\n+\t\tdecode_ok =\n+\t\t    decode_ok && efx_mon_get_stat_portmap(id, &stat_portmask);\n \n-\t\tif ((port_mask & mcdi_sensor_map[sensor].msm_port_mask) == 0)\n+\t\tif (!(decode_ok && (stat_portmask & port_mask)))\n \t\t\tcontinue;\n+\t\t/* Either bad decode, or don't know what port stat is on */\n+\n \t\tEFSYS_ASSERT(id < EFX_MON_NSTATS);\n \n \t\t/*\n@@ -229,6 +116,10 @@ mcdi_mon_decode_stats(\n \n \t\t\tstat[id].emsv_state = (uint16_t)EFX_DWORD_FIELD(dword,\n \t\t\t    MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE);\n+\n+\t\t\tstat[id].emsv_unit =\n+\t\t\t    efx_mon_get_stat_unit(id, &stat_unit) ?\n+\t\t\t    stat_unit : EFX_MON_STAT_UNIT_UNKNOWN;\n \t\t}\n \t}\n \n@@ -245,7 +136,7 @@ mcdi_mon_ev(\n \t__out\t\t\t\tefx_mon_stat_value_t *valuep)\n {\n \tefx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);\n-\tuint16_t port_mask;\n+\tefx_mon_stat_portmask_t port_mask, sensor_port_mask;\n \tuint16_t sensor;\n \tuint16_t state;\n \tuint16_t value;\n@@ -262,20 +153,22 @@ mcdi_mon_ev(\n \t/* Hardware must support this MCDI sensor */\n \tEFSYS_ASSERT3U(sensor, <,\n \t    (8 * enp->en_nic_cfg.enc_mcdi_sensor_mask_size));\n-\tEFSYS_ASSERT((sensor % MCDI_MON_PAGE_SIZE) != MC_CMD_SENSOR_PAGE0_NEXT);\n+\tEFSYS_ASSERT((sensor % (MC_CMD_SENSOR_PAGE0_NEXT + 1)) !=\n+\t    MC_CMD_SENSOR_PAGE0_NEXT);\n \tEFSYS_ASSERT(enp->en_nic_cfg.enc_mcdi_sensor_maskp != NULL);\n-\tEFSYS_ASSERT(\n-\t    (enp->en_nic_cfg.enc_mcdi_sensor_maskp[sensor/MCDI_MON_PAGE_SIZE] &\n-\t    (1U << (sensor % MCDI_MON_PAGE_SIZE))) != 0);\n+\tEFSYS_ASSERT((enp->en_nic_cfg.enc_mcdi_sensor_maskp[\n+\t\t    sensor / (MC_CMD_SENSOR_PAGE0_NEXT + 1)] &\n+\t\t(1U << (sensor % (MC_CMD_SENSOR_PAGE0_NEXT + 1)))) != 0);\n \n-\t/* But we don't have to understand it */\n-\tif (sensor >= EFX_ARRAY_SIZE(mcdi_sensor_map)) {\n+\t/* And we need to understand it, to get port-map */\n+\tif (!efx_mon_mcdi_to_efx_stat(sensor, &id)) {\n \t\trc = ENOTSUP;\n \t\tgoto fail1;\n \t}\n-\tid = mcdi_sensor_map[sensor].msm_stat;\n-\tif ((port_mask & mcdi_sensor_map[sensor].msm_port_mask) == 0)\n+\tif (!(efx_mon_get_stat_portmap(id, &sensor_port_mask) &&\n+\t\t(port_mask && sensor_port_mask))) {\n \t\treturn (ENODEV);\n+\t}\n \tEFSYS_ASSERT(id < EFX_MON_NSTATS);\n \n \t*idp = id;\n",
    "prefixes": [
        "13/37"
    ]
}