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GET /api/patches/44405/?format=api
{ "id": 44405, "url": "http://patches.dpdk.org/api/patches/44405/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-11-git-send-email-igor.russkikh@aquantia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536333719-32155-11-git-send-email-igor.russkikh@aquantia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536333719-32155-11-git-send-email-igor.russkikh@aquantia.com", "date": "2018-09-07T15:21:48", "name": "[10/21] net/atlantic: add hw adapter structures and defines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5039e20b1f71003a78aa65c0a0e745c43570558b", "submitter": { "id": 1124, "url": "http://patches.dpdk.org/api/people/1124/?format=api", "name": "Igor Russkikh", "email": "igor.russkikh@aquantia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-11-git-send-email-igor.russkikh@aquantia.com/mbox/", "series": [ { "id": 1228, "url": "http://patches.dpdk.org/api/series/1228/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1228", "date": "2018-09-07T15:21:39", "name": "net/atlantic: Aquantia aQtion 10G NIC Family DPDK PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/1228/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44405/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/44405/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BC64C5F19;\n\tFri, 7 Sep 2018 17:23:39 +0200 (CEST)", "from NAM03-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam03on0089.outbound.protection.outlook.com [104.47.42.89])\n\tby dpdk.org (Postfix) with ESMTP id 7C9CD4F9C\n\tfor <dev@dpdk.org>; Fri, 7 Sep 2018 17:23:25 +0200 (CEST)", "from ubuntubox.rdc.aquantia.com (95.79.108.179) by\n\tBLUPR0701MB1652.namprd07.prod.outlook.com (2a01:111:e400:58c6::22)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1122.16;\n\tFri, 7 Sep 2018 15:23:19 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=AQUANTIA1COM.onmicrosoft.com; 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"oMf/qBJPW27mvAmz0qd2R6TlYwo39r5H2mPgecZpLwkGwTKiqEggFFKU7yzh8+xBg2zvpn7iI2wbm0DpqhthUWlb7KGSha4u4B42aSDaVkFO+NF+bSnX/1YNyYJv1IwNoyfAMw5gQOu7dXp8+nP88tS3kBDnqFP2K0f4Otn+k61b3m7E+nm3+pLHyoz00ejtrXEHrpdlk6P66Yvg/rxy0rFPoWESp2OqkJntH5NVQVkUPjKbZDcetJz0jtjthbQi80JQMoVcs7cH03PHhuTf2jRw4pJgDwzpmvSqsPBpSClNi5SOicvWFnj9lV/lruZmvGK/ta1p6z4t0LTasi6BAENz82pcA3K7S+7LFfmAYMY=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "aquantia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Sep 2018 15:23:19.9262\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "8cb4757c-822a-4635-135f-08d614d5d885", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "83e2e134-991c-4ede-8ced-34d47e38e6b1", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR0701MB1652", "Subject": "[dpdk-dev] [PATCH 10/21] net/atlantic: add hw adapter structures\n\tand defines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavel Belous <pavel.belous@aquantia.com>\n\nThese declare statistic structures, hw internal structures and variables.\n\nSigned-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\n---\n drivers/net/atlantic/atl_ethdev.h | 9 ++\n drivers/net/atlantic/atl_types.h | 202 +++++++++++++++++++++++++++++++++++++-\n 2 files changed, 210 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h\nindex 5b9fc63c6..ce4bc9544 100644\n--- a/drivers/net/atlantic/atl_ethdev.h\n+++ b/drivers/net/atlantic/atl_ethdev.h\n@@ -16,12 +16,18 @@\n #define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)\n #define ATL_FLAG_NEED_LINK_CONFIG (uint32_t)(4 << 0)\n \n+struct atl_interrupt {\n+\tuint32_t flags;\n+\tuint32_t mask;\n+};\n+\n /*\n * Structure to store private data for each driver instance (for each port).\n */\n struct atl_adapter {\n \tstruct aq_hw_s hw;\n \tstruct aq_hw_cfg_s hw_cfg;\n+\tstruct atl_sw_stats sw_stats;\n \tstruct atl_interrupt intr;\n };\n \n@@ -31,6 +37,9 @@ struct atl_adapter {\n #define ATL_DEV_PRIVATE_TO_HW(adapter) \\\n \t(&((struct atl_adapter *)adapter)->hw)\n \n+#define ATL_DEV_PRIVATE_TO_STATS(adapter) \\\n+\t(&((struct atl_adapter *)adapter)->sw_stats)\n+\n #define ATL_DEV_PRIVATE_TO_INTR(adapter) \\\n \t(&((struct atl_adapter *)adapter)->intr)\n \ndiff --git a/drivers/net/atlantic/atl_types.h b/drivers/net/atlantic/atl_types.h\nindex f1558b0a5..60cbb6cda 100644\n--- a/drivers/net/atlantic/atl_types.h\n+++ b/drivers/net/atlantic/atl_types.h\n@@ -29,6 +29,206 @@ typedef int\t\tbool;\n #define min(a,b)\tRTE_MIN(a,b)\n #define max(a,b)\tRTE_MAX(a,b)\n \n-#define wmb()\t\trte_wmb()\n+#define wmb() rte_wmb()\n+\n+#include \"hw_atl/hw_atl_b0_internal.h\"\n+#include \"hw_atl/hw_atl_utils.h\"\n+\n+struct aq_hw_link_status_s {\n+\tunsigned int mbps;\n+};\n+\n+struct aq_stats_s {\n+\tu64 uprc;\n+\tu64 mprc;\n+\tu64 bprc;\n+\tu64 erpt;\n+\tu64 uptc;\n+\tu64 mptc;\n+\tu64 bptc;\n+\tu64 erpr;\n+\tu64 mbtc;\n+\tu64 bbtc;\n+\tu64 mbrc;\n+\tu64 bbrc;\n+\tu64 ubrc;\n+\tu64 ubtc;\n+\tu64 dpc;\n+\tu64 dma_pkt_rc;\n+\tu64 dma_pkt_tc;\n+\tu64 dma_oct_rc;\n+\tu64 dma_oct_tc;\n+};\n+\n+enum atl_bus_speed {\n+ atl_bus_speed_unknown = 0,\n+ atl_bus_speed_2500,\n+ atl_bus_speed_5000,\n+ atl_bus_speed_reserved\n+};\n+\n+enum atl_bus_width {\n+ atl_bus_width_unknown = 0,\n+ atl_bus_width_pcie_x1,\n+ atl_bus_width_pcie_x2,\n+ atl_bus_width_pcie_x4 = 4,\n+ atl_bus_width_pcie_x8 = 8,\n+ atl_bus_width_reserved\n+};\n+\n+struct atl_bus_info {\n+ enum atl_bus_speed speed;\n+ enum atl_bus_width width;\n+\n+ u16 func;\n+ u16 pci_cmd_word;\n+};\n+\n+struct aq_rss_parameters {\n+\tu16 base_cpu_number;\n+\tu16 indirection_table_size;\n+\tu16 hash_secret_key_size;\n+\tu32 hash_secret_key[HW_ATL_B0_RSS_HASHKEY_BITS/8];\n+\tu8 indirection_table[HW_ATL_B0_RSS_REDIRECTION_MAX];\n+};\n+\n+struct aq_hw_cfg_s {\n+\tbool is_lro;\n+\tbool is_rss;\n+\tunsigned int num_rss_queues;\n+\tint wol;\n+\n+\tint link_speed_msk;\n+\tint irq_type;\n+\tint irq_mask;\n+\tunsigned int vecs;\n+\n+\tbool vlan_strip;\n+\tuint32_t vlan_filter[HW_ATL_B0_MAX_VLAN_IDS];\n+\tuint32_t flow_control;\n+\n+\tstruct aq_rss_parameters aq_rss;\n+};\n+\n+struct aq_hw_s {\n+\tvoid *back;\n+\n+\tstruct atl_bus_info bus;\n+\n+\tconst u32 *mvals;\n+\tu16 device_id;\n+\tu16 vendor_id;\n+\tu16 subsystem_device_id;\n+\tu16 subsystem_vendor_id;\n+\tu8 revision_id;\n+\tbool adapter_stopped;\n+\tint api_version;\n+\tbool force_full_reset;\n+\tbool allow_unsupported_sfp;\n+\tbool wol_enabled;\n+\tbool need_crosstalk_fix;\n+\n+\tu8 rbl_enabled:1;\n+\tstruct aq_hw_cfg_s *aq_nic_cfg;\n+\tconst struct aq_fw_ops *aq_fw_ops;\n+\tvoid *mmio;\n+\n+\tstruct aq_hw_link_status_s aq_link_status;\n+\tbool is_autoneg;\n+\n+\tstruct hw_aq_atl_utils_mbox mbox;\n+\tstruct hw_atl_stats_s last_stats;\n+\tstruct aq_stats_s curr_stats;\n+\n+\tu64 speed;\n+\tu32 itr_tx;\n+\tu32 itr_rx;\n+\tunsigned int chip_features;\n+\tu32 fw_ver_actual;\n+\tu32 mbox_addr;\n+\tu32 rpc_addr;\n+\tu32 rpc_tid;\n+\tstruct hw_aq_atl_utils_fw_rpc rpc;\n+};\n+\n+struct aq_fw_ops {\n+\tint (*init)(struct aq_hw_s *self);\n+\n+\tint (*deinit)(struct aq_hw_s *self);\n+\n+\tint (*reset)(struct aq_hw_s *self);\n+\n+\tint (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);\n+\n+\tint (*set_link_speed)(struct aq_hw_s *self, u32 speed);\n+\n+\tint (*set_state)(struct aq_hw_s *self,\n+\t\t\tenum hal_atl_utils_fw_state_e state);\n+\n+\tint (*update_link_status)(struct aq_hw_s *self);\n+\n+\tint (*update_stats)(struct aq_hw_s *self);\n+\n+\tint (*set_power)(struct aq_hw_s *self, unsigned int power_state,\n+\t\t\tu8 *mac);\n+\n+\tint (*get_temp)(struct aq_hw_s *self, int *temp);\n+\n+\tint (*get_cable_len)(struct aq_hw_s *self, int *cable_len);\n+\n+\tint (*set_eee_rate)(struct aq_hw_s *self, u32 speed);\n+\n+\tint (*get_eee_rate)(struct aq_hw_s *self, u32 *rate,\n+\t\t\tu32 *supported_rates);\n+\n+\tint (*set_flow_control)(struct aq_hw_s *self);\n+\n+\tint (*led_control)(struct aq_hw_s *self, u32 mode);\n+\n+\tint (*get_eeprom)(struct aq_hw_s *self, u32 *data, u32 len);\n+\n+\tint (*set_eeprom)(struct aq_hw_s *self, u32 *data, u32 len);\n+};\n+\n+struct atl_sw_stats {\n+\tu64 crcerrs;\n+\tu64 errbc;\n+\tu64 mspdc;\n+\tu64 mpctotal;\n+\tu64 mpc[8];\n+\tu64 mlfc;\n+\tu64 mrfc;\n+\tu64 rlec;\n+\tu64 lxontxc;\n+\tu64 lxonrxc;\n+\tu64 lxofftxc;\n+\tu64 lxoffrxc;\n+\tu64 pxontxc[8];\n+\tu64 pxonrxc[8];\n+\tu64 pxofftxc[8];\n+\tu64 pxoffrxc[8];\n+\tu64 gprc;\n+\tu64 bprc;\n+\tu64 mprc;\n+\tu64 gptc;\n+\tu64 gorc;\n+\tu64 gotc;\n+\tu64 tor;\n+\tu64 tpr;\n+\tu64 tpt;\n+\tu64 mptc;\n+\tu64 bptc;\n+\tu64 xec;\n+\tu64 fccrc;\n+\tu64 ldpcec;\n+\tu64 pcrc8ec;\n+\n+\tu64 rx_nombuf;\n+\tu64 q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n+\tu64 q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n+\tu64 q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n+\tu64 q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n+\tu64 q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n+};\n \n #endif\n", "prefixes": [ "10/21" ] }