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{
    "id": 44400,
    "url": "http://patches.dpdk.org/api/patches/44400/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-5-git-send-email-igor.russkikh@aquantia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
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    "msgid": "<1536333719-32155-5-git-send-email-igor.russkikh@aquantia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1536333719-32155-5-git-send-email-igor.russkikh@aquantia.com",
    "date": "2018-09-07T15:21:42",
    "name": "[04/21] net/atlantic: hw_atl register declarations",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "45580f59d2c961d897ce7daec5b92f41bf73a30c",
    "submitter": {
        "id": 1124,
        "url": "http://patches.dpdk.org/api/people/1124/?format=api",
        "name": "Igor Russkikh",
        "email": "igor.russkikh@aquantia.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-5-git-send-email-igor.russkikh@aquantia.com/mbox/",
    "series": [
        {
            "id": 1228,
            "url": "http://patches.dpdk.org/api/series/1228/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1228",
            "date": "2018-09-07T15:21:39",
            "name": "net/atlantic: Aquantia aQtion 10G NIC Family DPDK PMD driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/1228/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/44400/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/44400/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Igor Russkikh <igor.russkikh@aquantia.com>",
        "To": "dev@dpdk.org",
        "Cc": "pavel.belous@aquantia.com, Nadezhda.Krupnina@aquantia.com,\n\tigor.russkikh@aquantia.com, Simon.Edelhaus@aquantia.com,\n\tCorey Melton <comelton@cisco.com>, Ashish Kumar <ashishk2@cisco.com>",
        "Date": "Fri,  7 Sep 2018 18:21:42 +0300",
        "Message-Id": "<1536333719-32155-5-git-send-email-igor.russkikh@aquantia.com>",
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        "Subject": "[dpdk-dev] [PATCH 04/21] net/atlantic: hw_atl register declarations",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
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    },
    "content": "This hw_atl layer is maintained in sync with linux kernel driver.\nIt will generally be in sync with linux upstream.\n\nSigned-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\n---\n drivers/net/atlantic/hw_atl/hw_atl_llh.c          | 1490 +++++++++++++\n drivers/net/atlantic/hw_atl/hw_atl_llh.h          |  714 ++++++\n drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h | 2413 +++++++++++++++++++++\n 3 files changed, 4617 insertions(+)\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh.c\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh.h\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h",
    "diff": "diff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/atlantic/hw_atl/hw_atl_llh.c\nnew file mode 100644\nindex 000000000..441745fd4\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_llh.c\n@@ -0,0 +1,1490 @@\n+/*\n+ * aQuantia Corporation Network Driver\n+ * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ */\n+\n+/* File hw_atl_llh.c: Definitions of bitfield and register access functions for\n+ * Atlantic registers.\n+ */\n+\n+#include \"hw_atl_llh.h\"\n+\n+#include \"../atl_hw_regs.h\"\n+#include \"hw_atl_llh_internal.h\"\n+\n+/* global */\n+void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,\n+\t\t\t\tu32 semaphore)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);\n+}\n+\n+u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));\n+}\n+\n+void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,\n+\t\t\t    HW_ATL_GLB_REG_RES_DIS_MSK,\n+\t\t\t    HW_ATL_GLB_REG_RES_DIS_SHIFT,\n+\t\t\t    glb_reg_res_dis);\n+}\n+\n+void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,\n+\t\t\t    HW_ATL_GLB_SOFT_RES_MSK,\n+\t\t\t    HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);\n+}\n+\n+u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,\n+\t\t\t\t  HW_ATL_GLB_SOFT_RES_MSK,\n+\t\t\t\t  HW_ATL_GLB_SOFT_RES_SHIFT);\n+}\n+\n+u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);\n+}\n+\n+/* stats */\n+u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);\n+}\n+\n+u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);\n+}\n+\n+u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);\n+}\n+\n+u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);\n+}\n+\n+u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);\n+}\n+\n+u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);\n+}\n+\n+u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);\n+}\n+\n+u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);\n+}\n+\n+u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);\n+}\n+\n+/* interrupt */\n+void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 irq_auto_masklsw)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);\n+}\n+\n+void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,\n+\t\t\t\t  u32 rx)\n+{\n+/* register address for bitfield imr_rx{r}_en */\n+\tstatic u32 itr_imr_rxren_adr[32] = {\n+\t\t\t0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,\n+\t\t\t0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,\n+\t\t\t0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,\n+\t\t\t0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,\n+\t\t\t0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,\n+\t\t\t0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,\n+\t\t\t0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,\n+\t\t\t0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU\n+\t\t};\n+\n+/* bitmask for bitfield imr_rx{r}_en */\n+\tstatic u32 itr_imr_rxren_msk[32] = {\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,\n+\t\t\t0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U\n+\t\t};\n+\n+/* lower bit position of bitfield imr_rx{r}_en */\n+\tstatic u32 itr_imr_rxren_shift[32] = {\n+\t\t\t15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,\n+\t\t\t15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,\n+\t\t\t15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,\n+\t\t\t15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U\n+\t\t};\n+\n+\taq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],\n+\t\t\t    itr_imr_rxren_msk[rx],\n+\t\t\t    itr_imr_rxren_shift[rx],\n+\t\t\t    irq_map_en_rx);\n+}\n+\n+void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,\n+\t\t\t\t  u32 tx)\n+{\n+/* register address for bitfield imr_tx{t}_en */\n+\tstatic u32 itr_imr_txten_adr[32] = {\n+\t\t\t0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,\n+\t\t\t0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,\n+\t\t\t0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,\n+\t\t\t0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,\n+\t\t\t0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,\n+\t\t\t0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,\n+\t\t\t0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,\n+\t\t\t0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU\n+\t\t};\n+\n+/* bitmask for bitfield imr_tx{t}_en */\n+\tstatic u32 itr_imr_txten_msk[32] = {\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,\n+\t\t\t0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U\n+\t\t};\n+\n+/* lower bit position of bitfield imr_tx{t}_en */\n+\tstatic u32 itr_imr_txten_shift[32] = {\n+\t\t\t31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,\n+\t\t\t31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,\n+\t\t\t31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,\n+\t\t\t31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U\n+\t\t};\n+\n+\taq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],\n+\t\t\t    itr_imr_txten_msk[tx],\n+\t\t\t    itr_imr_txten_shift[tx],\n+\t\t\t    irq_map_en_tx);\n+}\n+\n+void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)\n+{\n+/* register address for bitfield imr_rx{r}[4:0] */\n+\tstatic u32 itr_imr_rxr_adr[32] = {\n+\t\t\t0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,\n+\t\t\t0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,\n+\t\t\t0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,\n+\t\t\t0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,\n+\t\t\t0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,\n+\t\t\t0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,\n+\t\t\t0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,\n+\t\t\t0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU\n+\t\t};\n+\n+/* bitmask for bitfield imr_rx{r}[4:0] */\n+\tstatic u32 itr_imr_rxr_msk[32] = {\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,\n+\t\t\t0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU\n+\t\t};\n+\n+/* lower bit position of bitfield imr_rx{r}[4:0] */\n+\tstatic u32 itr_imr_rxr_shift[32] = {\n+\t\t\t8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,\n+\t\t\t8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,\n+\t\t\t8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,\n+\t\t\t8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U\n+\t\t};\n+\n+\taq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],\n+\t\t\t    itr_imr_rxr_msk[rx],\n+\t\t\t    itr_imr_rxr_shift[rx],\n+\t\t\t    irq_map_rx);\n+}\n+\n+void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)\n+{\n+/* register address for bitfield imr_tx{t}[4:0] */\n+\tstatic u32 itr_imr_txt_adr[32] = {\n+\t\t\t0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,\n+\t\t\t0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,\n+\t\t\t0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,\n+\t\t\t0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,\n+\t\t\t0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,\n+\t\t\t0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,\n+\t\t\t0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,\n+\t\t\t0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU\n+\t\t};\n+\n+/* bitmask for bitfield imr_tx{t}[4:0] */\n+\tstatic u32 itr_imr_txt_msk[32] = {\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,\n+\t\t\t0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U\n+\t\t};\n+\n+/* lower bit position of bitfield imr_tx{t}[4:0] */\n+\tstatic u32 itr_imr_txt_shift[32] = {\n+\t\t\t24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,\n+\t\t\t24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,\n+\t\t\t24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,\n+\t\t\t24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U\n+\t\t};\n+\n+\taq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],\n+\t\t\t    itr_imr_txt_msk[tx],\n+\t\t\t    itr_imr_txt_shift[tx],\n+\t\t\t    irq_map_tx);\n+}\n+\n+void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 irq_msk_clearlsw)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);\n+}\n+\n+void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);\n+}\n+\n+void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,\n+\t\t\t    HW_ATL_ITR_REG_RES_DSBL_MSK,\n+\t\t\t    HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);\n+}\n+\n+void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\tu32 irq_status_clearlsw)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);\n+}\n+\n+u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);\n+}\n+\n+u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,\n+\t\t\t\t  HW_ATL_ITR_RES_SHIFT);\n+}\n+\n+void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,\n+\t\t\t    HW_ATL_ITR_RES_SHIFT, res_irq);\n+}\n+\n+/* rdm */\n+void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),\n+\t\t\t    HW_ATL_RDM_DCADCPUID_MSK,\n+\t\t\t    HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);\n+}\n+\n+void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,\n+\t\t\t    HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);\n+}\n+\n+void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,\n+\t\t\t    HW_ATL_RDM_DCA_MODE_MSK,\n+\t\t\t    HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);\n+}\n+\n+void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_data_buff_size,\n+\t\t\t\t\t   u32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),\n+\t\t\t    HW_ATL_RDM_DESCDDATA_SIZE_MSK,\n+\t\t\t    HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,\n+\t\t\t    rx_desc_data_buff_size);\n+}\n+\n+void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,\n+\t\t\t\t   u32 dca)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),\n+\t\t\t    HW_ATL_RDM_DCADDESC_EN_MSK,\n+\t\t\t    HW_ATL_RDM_DCADDESC_EN_SHIFT,\n+\t\t\t    rx_desc_dca_en);\n+}\n+\n+void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,\n+\t\t\t       u32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),\n+\t\t\t    HW_ATL_RDM_DESCDEN_MSK,\n+\t\t\t    HW_ATL_RDM_DESCDEN_SHIFT,\n+\t\t\t    rx_desc_en);\n+}\n+\n+void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_head_buff_size,\n+\t\t\t\t\t   u32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),\n+\t\t\t    HW_ATL_RDM_DESCDHDR_SIZE_MSK,\n+\t\t\t    HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,\n+\t\t\t    rx_desc_head_buff_size);\n+}\n+\n+void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_head_splitting,\n+\t\t\t\t\t   u32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),\n+\t\t\t    HW_ATL_RDM_DESCDHDR_SPLIT_MSK,\n+\t\t\t    HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,\n+\t\t\t    rx_desc_head_splitting);\n+}\n+\n+u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),\n+\t\t\t\t  HW_ATL_RDM_DESCDHD_MSK,\n+\t\t\t\t  HW_ATL_RDM_DESCDHD_SHIFT);\n+}\n+\n+void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,\n+\t\t\t\tu32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),\n+\t\t\t    HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,\n+\t\t\t    rx_desc_len);\n+}\n+\n+void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,\n+\t\t\t\tu32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),\n+\t\t\t    HW_ATL_RDM_DESCDRESET_MSK,\n+\t\t\t    HW_ATL_RDM_DESCDRESET_SHIFT,\n+\t\t\t    rx_desc_res);\n+}\n+\n+void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 rx_desc_wr_wb_irq_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,\n+\t\t\t    HW_ATL_RDM_INT_DESC_WRB_EN_MSK,\n+\t\t\t    HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,\n+\t\t\t    rx_desc_wr_wb_irq_en);\n+}\n+\n+void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,\n+\t\t\t\t   u32 dca)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),\n+\t\t\t    HW_ATL_RDM_DCADHDR_EN_MSK,\n+\t\t\t    HW_ATL_RDM_DCADHDR_EN_SHIFT,\n+\t\t\t    rx_head_dca_en);\n+}\n+\n+void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,\n+\t\t\t\t  u32 dca)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),\n+\t\t\t    HW_ATL_RDM_DCADPAY_EN_MSK,\n+\t\t\t    HW_ATL_RDM_DCADPAY_EN_SHIFT,\n+\t\t\t    rx_pld_dca_en);\n+}\n+\n+void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 rdm_intr_moder_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,\n+\t\t\t    HW_ATL_RDM_INT_RIM_EN_MSK,\n+\t\t\t    HW_ATL_RDM_INT_RIM_EN_SHIFT,\n+\t\t\t    rdm_intr_moder_en);\n+}\n+\n+/* reg */\n+void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,\n+\t\t\t\tu32 regidx)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);\n+}\n+\n+u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);\n+}\n+\n+void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);\n+}\n+\n+void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);\n+}\n+\n+void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 rx_dma_desc_base_addrlsw,\n+\t\t\t\t\t       u32 descriptor)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),\n+\t\t\trx_dma_desc_base_addrlsw);\n+}\n+\n+void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 rx_dma_desc_base_addrmsw,\n+\t\t\t\t\t       u32 descriptor)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),\n+\t\t\trx_dma_desc_base_addrmsw);\n+}\n+\n+u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));\n+}\n+\n+void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 rx_dma_desc_tail_ptr,\n+\t\t\t\t\t u32 descriptor)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),\n+\t\t\trx_dma_desc_tail_ptr);\n+}\n+\n+void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\tu32 rx_flr_mcst_flr_msk)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,\n+\t\t\trx_flr_mcst_flr_msk);\n+}\n+\n+void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,\n+\t\t\t\t    u32 filter)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),\n+\t\t\trx_flr_mcst_flr);\n+}\n+\n+void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 rx_flr_rss_control1)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,\n+\t\t\trx_flr_rss_control1);\n+}\n+\n+void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t    u32 rx_filter_control2)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);\n+}\n+\n+void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 rx_intr_moderation_ctl,\n+\t\t\t\t       u32 queue)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),\n+\t\t\trx_intr_moderation_ctl);\n+}\n+\n+void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 tx_dma_debug_ctl)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);\n+}\n+\n+void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_dma_desc_base_addrlsw,\n+\t\t\t\t\t       u32 descriptor)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),\n+\t\t\ttx_dma_desc_base_addrlsw);\n+}\n+\n+void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_dma_desc_base_addrmsw,\n+\t\t\t\t\t       u32 descriptor)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),\n+\t\t\ttx_dma_desc_base_addrmsw);\n+}\n+\n+void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 tx_dma_desc_tail_ptr,\n+\t\t\t\t\t u32 descriptor)\n+{\n+\trte_wmb();\n+\n+\taq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),\n+\t\t\ttx_dma_desc_tail_ptr);\n+}\n+\n+void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 tx_intr_moderation_ctl,\n+\t\t\t\t       u32 queue)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),\n+\t\t\ttx_intr_moderation_ctl);\n+}\n+\n+/* RPB: rx packet buffer */\n+void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,\n+\t\t\t    HW_ATL_RPB_DMA_SYS_LBK_MSK,\n+\t\t\t    HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);\n+}\n+\n+void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_traf_class_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,\n+\t\t\t    HW_ATL_RPB_RPF_RX_TC_MODE_MSK,\n+\t\t\t    HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,\n+\t\t\t    rx_traf_class_mode);\n+}\n+\n+u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,\n+\t\t\tHW_ATL_RPB_RPF_RX_TC_MODE_MSK,\n+\t\t\tHW_ATL_RPB_RPF_RX_TC_MODE_SHIFT);\n+}\n+\n+void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,\n+\t\t\t    HW_ATL_RPB_RX_BUF_EN_MSK,\n+\t\t\t    HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);\n+}\n+\n+void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 rx_buff_hi_threshold_per_tc,\n+\t\t\t\t\t\tu32 buffer)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),\n+\t\t\t    HW_ATL_RPB_RXBHI_THRESH_MSK,\n+\t\t\t    HW_ATL_RPB_RXBHI_THRESH_SHIFT,\n+\t\t\t    rx_buff_hi_threshold_per_tc);\n+}\n+\n+void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 rx_buff_lo_threshold_per_tc,\n+\t\t\t\t\t\tu32 buffer)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),\n+\t\t\t    HW_ATL_RPB_RXBLO_THRESH_MSK,\n+\t\t\t    HW_ATL_RPB_RXBLO_THRESH_SHIFT,\n+\t\t\t    rx_buff_lo_threshold_per_tc);\n+}\n+\n+void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,\n+\t\t\t    HW_ATL_RPB_RX_FC_MODE_MSK,\n+\t\t\t    HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);\n+}\n+\n+void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 rx_pkt_buff_size_per_tc, u32 buffer)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),\n+\t\t\t    HW_ATL_RPB_RXBBUF_SIZE_MSK,\n+\t\t\t    HW_ATL_RPB_RXBBUF_SIZE_SHIFT,\n+\t\t\t    rx_pkt_buff_size_per_tc);\n+}\n+\n+void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,\n+\t\t\t\t      u32 buffer)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),\n+\t\t\t    HW_ATL_RPB_RXBXOFF_EN_MSK,\n+\t\t\t    HW_ATL_RPB_RXBXOFF_EN_SHIFT,\n+\t\t\t    rx_xoff_en_per_tc);\n+}\n+\n+/* rpf */\n+\n+void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 l2broadcast_count_threshold)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,\n+\t\t\t    HW_ATL_RPFL2BC_THRESH_MSK,\n+\t\t\t    HW_ATL_RPFL2BC_THRESH_SHIFT,\n+\t\t\t    l2broadcast_count_threshold);\n+}\n+\n+void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,\n+\t\t\t    HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);\n+}\n+\n+void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 l2broadcast_flr_act)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,\n+\t\t\t    HW_ATL_RPFL2BC_ACT_MSK,\n+\t\t\t    HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);\n+}\n+\n+void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 l2multicast_flr_en,\n+\t\t\t\t      u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),\n+\t\t\t    HW_ATL_RPFL2MC_ENF_MSK,\n+\t\t\t    HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);\n+}\n+\n+void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 l2promiscuous_mode_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,\n+\t\t\t    HW_ATL_RPFL2PROMIS_MODE_MSK,\n+\t\t\t    HW_ATL_RPFL2PROMIS_MODE_SHIFT,\n+\t\t\t    l2promiscuous_mode_en);\n+}\n+\n+void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 l2unicast_flr_act,\n+\t\t\t\t     u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),\n+\t\t\t    HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,\n+\t\t\t    l2unicast_flr_act);\n+}\n+\n+void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,\n+\t\t\t\tu32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),\n+\t\t\t    HW_ATL_RPFL2UC_ENF_MSK,\n+\t\t\t    HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);\n+}\n+\n+void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 l2unicast_dest_addresslsw,\n+\t\t\t\t\t     u32 filter)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),\n+\t\t\tl2unicast_dest_addresslsw);\n+}\n+\n+void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 l2unicast_dest_addressmsw,\n+\t\t\t\t\t     u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),\n+\t\t\t    HW_ATL_RPFL2UC_DAFMSW_MSK,\n+\t\t\t    HW_ATL_RPFL2UC_DAFMSW_SHIFT,\n+\t\t\t    l2unicast_dest_addressmsw);\n+}\n+\n+void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 l2_accept_all_mc_packets)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,\n+\t\t\t    HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,\n+\t\t\t    HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,\n+\t\t\t    l2_accept_all_mc_packets);\n+}\n+\n+void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 user_priority_tc_map, u32 tc)\n+{\n+/* register address for bitfield rx_tc_up{t}[2:0] */\n+\tstatic u32 rpf_rpb_rx_tc_upt_adr[8] = {\n+\t\t\t0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,\n+\t\t\t0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U\n+\t\t};\n+\n+/* bitmask for bitfield rx_tc_up{t}[2:0] */\n+\tstatic u32 rpf_rpb_rx_tc_upt_msk[8] = {\n+\t\t\t0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,\n+\t\t\t0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U\n+\t\t};\n+\n+/* lower bit position of bitfield rx_tc_up{t}[2:0] */\n+\tstatic u32 rpf_rpb_rx_tc_upt_shft[8] = {\n+\t\t\t0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U\n+\t\t};\n+\n+\taq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],\n+\t\t\t    rpf_rpb_rx_tc_upt_msk[tc],\n+\t\t\t    rpf_rpb_rx_tc_upt_shft[tc],\n+\t\t\t    user_priority_tc_map);\n+}\n+\n+void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,\n+\t\t\t    HW_ATL_RPF_RSS_KEY_ADDR_MSK,\n+\t\t\t    HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,\n+\t\t\t    rss_key_addr);\n+}\n+\n+void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,\n+\t\t\trss_key_wr_data);\n+}\n+\n+u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,\n+\t\t\t\t  HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,\n+\t\t\t\t  HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);\n+}\n+\n+void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,\n+\t\t\t    HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,\n+\t\t\t    HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,\n+\t\t\t    rss_key_wr_en);\n+}\n+\n+void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 rss_redir_tbl_addr)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,\n+\t\t\t    HW_ATL_RPF_RSS_REDIR_ADDR_MSK,\n+\t\t\t    HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,\n+\t\t\t    rss_redir_tbl_addr);\n+}\n+\n+void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 rss_redir_tbl_wr_data)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,\n+\t\t\t    HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,\n+\t\t\t    HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,\n+\t\t\t    rss_redir_tbl_wr_data);\n+}\n+\n+u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,\n+\t\t\t\t  HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,\n+\t\t\t\t  HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);\n+}\n+\n+void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,\n+\t\t\t    HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,\n+\t\t\t    HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);\n+}\n+\n+void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 tpo_to_rpf_sys_lbk)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,\n+\t\t\t    HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,\n+\t\t\t    HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,\n+\t\t\t    tpo_to_rpf_sys_lbk);\n+}\n+\n+void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,\n+\t\t\t    HW_ATL_RPF_VL_INNER_TPID_MSK,\n+\t\t\t    HW_ATL_RPF_VL_INNER_TPID_SHIFT,\n+\t\t\t    vlan_inner_etht);\n+}\n+\n+void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,\n+\t\t\t    HW_ATL_RPF_VL_OUTER_TPID_MSK,\n+\t\t\t    HW_ATL_RPF_VL_OUTER_TPID_SHIFT,\n+\t\t\t    vlan_outer_etht);\n+}\n+\n+void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 vlan_prom_mode_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,\n+\t\t\t    HW_ATL_RPF_VL_PROMIS_MODE_MSK,\n+\t\t\t    HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,\n+\t\t\t    vlan_prom_mode_en);\n+}\n+\n+void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t u32 vlan_acc_untagged_packets)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,\n+\t\t\t    HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,\n+\t\t\t    HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,\n+\t\t\t    vlan_acc_untagged_packets);\n+}\n+\n+void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 vlan_untagged_act)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,\n+\t\t\t    HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,\n+\t\t\t    HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,\n+\t\t\t    vlan_untagged_act);\n+}\n+\n+void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,\n+\t\t\t\tu32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),\n+\t\t\t    HW_ATL_RPF_VL_EN_F_MSK,\n+\t\t\t    HW_ATL_RPF_VL_EN_F_SHIFT,\n+\t\t\t    vlan_flr_en);\n+}\n+\n+void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,\n+\t\t\t\t u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),\n+\t\t\t    HW_ATL_RPF_VL_ACT_F_MSK,\n+\t\t\t    HW_ATL_RPF_VL_ACT_F_SHIFT,\n+\t\t\t    vlan_flr_act);\n+}\n+\n+void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,\n+\t\t\t\tu32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),\n+\t\t\t    HW_ATL_RPF_VL_ID_F_MSK,\n+\t\t\t    HW_ATL_RPF_VL_ID_F_SHIFT,\n+\t\t\t    vlan_id_flr);\n+}\n+\n+void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,\n+\t\t\t\tu32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_ENF_MSK,\n+\t\t\t    HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);\n+}\n+\n+void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 etht_user_priority_en, u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,\n+\t\t\t    etht_user_priority_en);\n+}\n+\n+void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 etht_rx_queue_en,\n+\t\t\t\t     u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_RXQFEN_MSK,\n+\t\t\t    HW_ATL_RPF_ET_RXQFEN_SHIFT,\n+\t\t\t    etht_rx_queue_en);\n+}\n+\n+void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 etht_user_priority,\n+\t\t\t\t       u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_UPF_MSK,\n+\t\t\t    HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);\n+}\n+\n+void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,\n+\t\t\t\t  u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_RXQF_MSK,\n+\t\t\t    HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);\n+}\n+\n+void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,\n+\t\t\t\t   u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_MNG_RXQF_MSK,\n+\t\t\t    HW_ATL_RPF_ET_MNG_RXQF_SHIFT,\n+\t\t\t    etht_mgt_queue);\n+}\n+\n+void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,\n+\t\t\t\t u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_ACTF_MSK,\n+\t\t\t    HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);\n+}\n+\n+void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),\n+\t\t\t    HW_ATL_RPF_ET_VALF_MSK,\n+\t\t\t    HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);\n+}\n+\n+/* RPO: rx packet offload */\n+void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 ipv4header_crc_offload_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,\n+\t\t\t    HW_ATL_RPO_IPV4CHK_EN_MSK,\n+\t\t\t    HW_ATL_RPO_IPV4CHK_EN_SHIFT,\n+\t\t\t    ipv4header_crc_offload_en);\n+}\n+\n+void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_vlan_stripping,\n+\t\t\t\t\t   u32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),\n+\t\t\t    HW_ATL_RPO_DESCDVL_STRIP_MSK,\n+\t\t\t    HW_ATL_RPO_DESCDVL_STRIP_SHIFT,\n+\t\t\t    rx_desc_vlan_stripping);\n+}\n+\n+void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 tcp_udp_crc_offload_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,\n+\t\t\t    HW_ATL_RPOL4CHK_EN_MSK,\n+\t\t\t    HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);\n+}\n+\n+void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);\n+}\n+\n+void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 lro_patch_optimization_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,\n+\t\t\t    HW_ATL_RPO_LRO_PTOPT_EN_MSK,\n+\t\t\t    HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,\n+\t\t\t    lro_patch_optimization_en);\n+}\n+\n+void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 lro_qsessions_lim)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,\n+\t\t\t    HW_ATL_RPO_LRO_QSES_LMT_MSK,\n+\t\t\t    HW_ATL_RPO_LRO_QSES_LMT_SHIFT,\n+\t\t\t    lro_qsessions_lim);\n+}\n+\n+void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 lro_total_desc_lim)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,\n+\t\t\t    HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,\n+\t\t\t    HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,\n+\t\t\t    lro_total_desc_lim);\n+}\n+\n+void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 lro_min_pld_of_first_pkt)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,\n+\t\t\t    HW_ATL_RPO_LRO_PKT_MIN_MSK,\n+\t\t\t    HW_ATL_RPO_LRO_PKT_MIN_SHIFT,\n+\t\t\t    lro_min_pld_of_first_pkt);\n+}\n+\n+void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);\n+}\n+\n+void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 lro_max_number_of_descriptors,\n+\t\t\t\t\t       u32 lro)\n+{\n+/* Register address for bitfield lro{L}_des_max[1:0] */\n+\tstatic u32 rpo_lro_ldes_max_adr[32] = {\n+\t\t\t0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,\n+\t\t\t0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,\n+\t\t\t0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,\n+\t\t\t0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,\n+\t\t\t0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,\n+\t\t\t0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,\n+\t\t\t0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,\n+\t\t\t0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU\n+\t\t};\n+\n+/* Bitmask for bitfield lro{L}_des_max[1:0] */\n+\tstatic u32 rpo_lro_ldes_max_msk[32] = {\n+\t\t\t0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,\n+\t\t\t0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,\n+\t\t\t0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,\n+\t\t\t0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,\n+\t\t\t0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,\n+\t\t\t0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,\n+\t\t\t0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,\n+\t\t\t0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U\n+\t\t};\n+\n+/* Lower bit position of bitfield lro{L}_des_max[1:0] */\n+\tstatic u32 rpo_lro_ldes_max_shift[32] = {\n+\t\t\t0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,\n+\t\t\t0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,\n+\t\t\t0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,\n+\t\t\t0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U\n+\t\t};\n+\n+\taq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],\n+\t\t\t    rpo_lro_ldes_max_msk[lro],\n+\t\t\t    rpo_lro_ldes_max_shift[lro],\n+\t\t\t    lro_max_number_of_descriptors);\n+}\n+\n+void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 lro_time_base_divider)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,\n+\t\t\t    HW_ATL_RPO_LRO_TB_DIV_MSK,\n+\t\t\t    HW_ATL_RPO_LRO_TB_DIV_SHIFT,\n+\t\t\t    lro_time_base_divider);\n+}\n+\n+void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 lro_inactive_interval)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,\n+\t\t\t    HW_ATL_RPO_LRO_INA_IVAL_MSK,\n+\t\t\t    HW_ATL_RPO_LRO_INA_IVAL_SHIFT,\n+\t\t\t    lro_inactive_interval);\n+}\n+\n+void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 lro_max_coal_interval)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,\n+\t\t\t    HW_ATL_RPO_LRO_MAX_IVAL_MSK,\n+\t\t\t    HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,\n+\t\t\t    lro_max_coal_interval);\n+}\n+\n+/* rx */\n+void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,\n+\t\t\t    HW_ATL_RX_REG_RES_DSBL_MSK,\n+\t\t\t    HW_ATL_RX_REG_RES_DSBL_SHIFT,\n+\t\t\t    rx_reg_res_dis);\n+}\n+\n+/* tdm */\n+void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),\n+\t\t\t    HW_ATL_TDM_DCADCPUID_MSK,\n+\t\t\t    HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);\n+}\n+\n+void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 large_send_offload_en)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);\n+}\n+\n+void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,\n+\t\t\t    HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);\n+}\n+\n+void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,\n+\t\t\t    HW_ATL_TDM_DCA_MODE_MSK,\n+\t\t\t    HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);\n+}\n+\n+void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,\n+\t\t\t\t   u32 dca)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),\n+\t\t\t    HW_ATL_TDM_DCADDESC_EN_MSK,\n+\t\t\t    HW_ATL_TDM_DCADDESC_EN_SHIFT,\n+\t\t\t    tx_desc_dca_en);\n+}\n+\n+void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,\n+\t\t\t       u32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),\n+\t\t\t    HW_ATL_TDM_DESCDEN_MSK,\n+\t\t\t    HW_ATL_TDM_DESCDEN_SHIFT,\n+\t\t\t    tx_desc_en);\n+}\n+\n+u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),\n+\t\t\t\t  HW_ATL_TDM_DESCDHD_MSK,\n+\t\t\t\t  HW_ATL_TDM_DESCDHD_SHIFT);\n+}\n+\n+void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,\n+\t\t\t\tu32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),\n+\t\t\t    HW_ATL_TDM_DESCDLEN_MSK,\n+\t\t\t    HW_ATL_TDM_DESCDLEN_SHIFT,\n+\t\t\t    tx_desc_len);\n+}\n+\n+void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 tx_desc_wr_wb_irq_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,\n+\t\t\t    HW_ATL_TDM_INT_DESC_WRB_EN_MSK,\n+\t\t\t    HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,\n+\t\t\t    tx_desc_wr_wb_irq_en);\n+}\n+\n+void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 tx_desc_wr_wb_threshold,\n+\t\t\t\t\t    u32 descriptor)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),\n+\t\t\t    HW_ATL_TDM_DESCDWRB_THRESH_MSK,\n+\t\t\t    HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,\n+\t\t\t    tx_desc_wr_wb_threshold);\n+}\n+\n+void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 tdm_irq_moderation_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,\n+\t\t\t    HW_ATL_TDM_INT_MOD_EN_MSK,\n+\t\t\t    HW_ATL_TDM_INT_MOD_EN_SHIFT,\n+\t\t\t    tdm_irq_moderation_en);\n+}\n+\n+/* thm */\n+void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 lso_tcp_flag_of_first_pkt)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,\n+\t\t\t    HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,\n+\t\t\t    HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,\n+\t\t\t    lso_tcp_flag_of_first_pkt);\n+}\n+\n+void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 lso_tcp_flag_of_last_pkt)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,\n+\t\t\t    HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,\n+\t\t\t    HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,\n+\t\t\t    lso_tcp_flag_of_last_pkt);\n+}\n+\n+void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 lso_tcp_flag_of_middle_pkt)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,\n+\t\t\t    HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,\n+\t\t\t    HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,\n+\t\t\t    lso_tcp_flag_of_middle_pkt);\n+}\n+\n+/* TPB: tx packet buffer */\n+void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,\n+\t\t\t    HW_ATL_TPB_TX_BUF_EN_MSK,\n+\t\t\t    HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);\n+}\n+\n+u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,\n+\t\t\tHW_ATL_TPB_TX_TC_MODE_MSK,\n+\t\t\tHW_ATL_TPB_TX_TC_MODE_SHIFT);\n+}\n+\n+void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, u32 tx_traf_class_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,\n+\t\t\tHW_ATL_TPB_TX_TC_MODE_MSK,\n+\t\t\tHW_ATL_TPB_TX_TC_MODE_SHIFT,\n+\t\t\ttx_traf_class_mode);\n+}\n+\n+void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 tx_buff_hi_threshold_per_tc,\n+\t\t\t\t\t u32 buffer)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),\n+\t\t\t    HW_ATL_TPB_TXBHI_THRESH_MSK,\n+\t\t\t    HW_ATL_TPB_TXBHI_THRESH_SHIFT,\n+\t\t\t    tx_buff_hi_threshold_per_tc);\n+}\n+\n+void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 tx_buff_lo_threshold_per_tc,\n+\t\t\t\t\t u32 buffer)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),\n+\t\t\t    HW_ATL_TPB_TXBLO_THRESH_MSK,\n+\t\t\t    HW_ATL_TPB_TXBLO_THRESH_SHIFT,\n+\t\t\t    tx_buff_lo_threshold_per_tc);\n+}\n+\n+void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,\n+\t\t\t    HW_ATL_TPB_DMA_SYS_LBK_MSK,\n+\t\t\t    HW_ATL_TPB_DMA_SYS_LBK_SHIFT,\n+\t\t\t    tx_dma_sys_lbk_en);\n+}\n+\n+void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 tx_pkt_buff_size_per_tc, u32 buffer)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),\n+\t\t\t    HW_ATL_TPB_TXBBUF_SIZE_MSK,\n+\t\t\t    HW_ATL_TPB_TXBBUF_SIZE_SHIFT,\n+\t\t\t    tx_pkt_buff_size_per_tc);\n+}\n+\n+void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,\n+\t\t\t    HW_ATL_TPB_TX_SCP_INS_EN_MSK,\n+\t\t\t    HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,\n+\t\t\t    tx_path_scp_ins_en);\n+}\n+\n+/* TPO: tx packet offload */\n+void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 ipv4header_crc_offload_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,\n+\t\t\t    HW_ATL_TPO_IPV4CHK_EN_MSK,\n+\t\t\t    HW_ATL_TPO_IPV4CHK_EN_SHIFT,\n+\t\t\t    ipv4header_crc_offload_en);\n+}\n+\n+void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 tcp_udp_crc_offload_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,\n+\t\t\t    HW_ATL_TPOL4CHK_EN_MSK,\n+\t\t\t    HW_ATL_TPOL4CHK_EN_SHIFT,\n+\t\t\t    tcp_udp_crc_offload_en);\n+}\n+\n+void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 tx_pkt_sys_lbk_en)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,\n+\t\t\t    HW_ATL_TPO_PKT_SYS_LBK_MSK,\n+\t\t\t    HW_ATL_TPO_PKT_SYS_LBK_SHIFT,\n+\t\t\t    tx_pkt_sys_lbk_en);\n+}\n+\n+/* TPS: tx packet scheduler */\n+void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 tx_pkt_shed_data_arb_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,\n+\t\t\t    HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,\n+\t\t\t    HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,\n+\t\t\t    tx_pkt_shed_data_arb_mode);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t\tu32 curr_time_res)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,\n+\t\t\t    HW_ATL_TPS_DESC_RATE_TA_RST_MSK,\n+\t\t\t    HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,\n+\t\t\t    curr_time_res);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 tx_pkt_shed_desc_rate_lim)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,\n+\t\t\t    HW_ATL_TPS_DESC_RATE_LIM_MSK,\n+\t\t\t    HW_ATL_TPS_DESC_RATE_LIM_SHIFT,\n+\t\t\t    tx_pkt_shed_desc_rate_lim);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t u32 arb_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,\n+\t\t\t    HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,\n+\t\t\t    HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,\n+\t\t\t    arb_mode);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t   u32 max_credit,\n+\t\t\t\t\t\t   u32 tc)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),\n+\t\t\t    HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,\n+\t\t\t    HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,\n+\t\t\t    max_credit);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_pkt_shed_desc_tc_weight,\n+\t\t\t\t\t       u32 tc)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),\n+\t\t\t    HW_ATL_TPS_DESC_TCTWEIGHT_MSK,\n+\t\t\t    HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,\n+\t\t\t    tx_pkt_shed_desc_tc_weight);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t u32 arb_mode)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,\n+\t\t\t    HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,\n+\t\t\t    HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,\n+\t\t\t    arb_mode);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t   u32 max_credit,\n+\t\t\t\t\t\t   u32 tc)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),\n+\t\t\t    HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,\n+\t\t\t    HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,\n+\t\t\t    max_credit);\n+}\n+\n+void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_pkt_shed_tc_data_weight,\n+\t\t\t\t\t       u32 tc)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),\n+\t\t\t    HW_ATL_TPS_DATA_TCTWEIGHT_MSK,\n+\t\t\t    HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,\n+\t\t\t    tx_pkt_shed_tc_data_weight);\n+}\n+\n+/* tx */\n+void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,\n+\t\t\t    HW_ATL_TX_REG_RES_DSBL_MSK,\n+\t\t\t    HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);\n+}\n+\n+/* msm */\n+u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,\n+\t\t\t\t  HW_ATL_MSM_REG_ACCESS_BUSY_MSK,\n+\t\t\t\t  HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);\n+}\n+\n+void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 reg_addr_for_indirect_addr)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,\n+\t\t\t    HW_ATL_MSM_REG_ADDR_MSK,\n+\t\t\t    HW_ATL_MSM_REG_ADDR_SHIFT,\n+\t\t\t    reg_addr_for_indirect_addr);\n+}\n+\n+void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,\n+\t\t\t    HW_ATL_MSM_REG_RD_STROBE_MSK,\n+\t\t\t    HW_ATL_MSM_REG_RD_STROBE_SHIFT,\n+\t\t\t    reg_rd_strobe);\n+}\n+\n+u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)\n+{\n+\treturn aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);\n+}\n+\n+void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);\n+}\n+\n+void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,\n+\t\t\t    HW_ATL_MSM_REG_WR_STROBE_MSK,\n+\t\t\t    HW_ATL_MSM_REG_WR_STROBE_SHIFT,\n+\t\t\t    reg_wr_strobe);\n+}\n+\n+/* pci */\n+void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)\n+{\n+\taq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,\n+\t\t\t    HW_ATL_PCI_REG_RES_DSBL_MSK,\n+\t\t\t    HW_ATL_PCI_REG_RES_DSBL_SHIFT,\n+\t\t\t    pci_reg_res_dis);\n+}\n+\n+void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\tu32 glb_cpu_scratch_scp,\n+\t\t\t\t\tu32 scratch_scp)\n+{\n+\taq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),\n+\t\t\tglb_cpu_scratch_scp);\n+}\n+\n+void mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)\n+{\n+\n+\taq_hw_write_reg_bit(aq_hw, mcp_up_force_interrupt_adr,\n+\t\t\tmcp_up_force_interrupt_msk,\n+\t\t\tmcp_up_force_interrupt_shift, up_force_intr);\n+}\ndiff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/atlantic/hw_atl/hw_atl_llh.h\nnew file mode 100644\nindex 000000000..91b5030d2\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_llh.h\n@@ -0,0 +1,714 @@\n+/*\n+ * aQuantia Corporation Network Driver\n+ * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ */\n+\n+/* File hw_atl_llh.h: Declarations of bitfield and register access functions for\n+ * Atlantic registers.\n+ */\n+\n+#ifndef HW_ATL_LLH_H\n+#define HW_ATL_LLH_H\n+\n+#include \"../atl_types.h\"\n+\n+struct aq_hw_s;\n+\n+/* global */\n+\n+/* set global microprocessor semaphore */\n+void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw,\tu32 glb_cpu_sem,\n+\t\t\t\tu32 semaphore);\n+\n+/* get global microprocessor semaphore */\n+u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore);\n+\n+/* set global register reset disable */\n+void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis);\n+\n+/* set soft reset */\n+void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res);\n+\n+/* get soft reset */\n+u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw);\n+\n+/* stats */\n+\n+u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get rx dma good octet counter lsw */\n+u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get rx dma good packet counter lsw */\n+u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get tx dma good octet counter lsw */\n+u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get tx dma good packet counter lsw */\n+u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get rx dma good octet counter msw */\n+u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get rx dma good packet counter msw */\n+u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get tx dma good octet counter msw */\n+u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get tx dma good packet counter msw */\n+u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm rx errors counter register */\n+u32 hw_atl_reg_mac_msm_rx_errs_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm rx unicast frames counter register */\n+u32 hw_atl_reg_mac_msm_rx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm rx multicast frames counter register */\n+u32 hw_atl_reg_mac_msm_rx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm rx broadcast frames counter register */\n+u32 hw_atl_reg_mac_msm_rx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm rx broadcast octets counter register 1 */\n+u32 hw_atl_reg_mac_msm_rx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);\n+\n+/* get msm rx unicast octets counter register 0 */\n+u32 hw_atl_reg_mac_msm_rx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);\n+\n+/* get rx dma statistics counter 7 */\n+u32 hw_atl_reg_rx_dma_stat_counter7get(struct aq_hw_s *aq_hw);\n+\n+/* get msm tx errors counter register */\n+u32 hw_atl_reg_mac_msm_tx_errs_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm tx unicast frames counter register */\n+u32 hw_atl_reg_mac_msm_tx_ucst_frm_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm tx multicast frames counter register */\n+u32 hw_atl_reg_mac_msm_tx_mcst_frm_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm tx broadcast frames counter register */\n+u32 hw_atl_reg_mac_msm_tx_bcst_frm_cnt_get(struct aq_hw_s *aq_hw);\n+\n+/* get msm tx multicast octets counter register 1 */\n+u32 hw_atl_reg_mac_msm_tx_mcst_octets_counter1get(struct aq_hw_s *aq_hw);\n+\n+/* get msm tx broadcast octets counter register 1 */\n+u32 hw_atl_reg_mac_msm_tx_bcst_octets_counter1get(struct aq_hw_s *aq_hw);\n+\n+/* get msm tx unicast octets counter register 0 */\n+u32 hw_atl_reg_mac_msm_tx_ucst_octets_counter0get(struct aq_hw_s *aq_hw);\n+\n+/* get global mif identification */\n+u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw);\n+\n+/* interrupt */\n+\n+/* set interrupt auto mask lsw */\n+void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 irq_auto_masklsw);\n+\n+/* set interrupt mapping enable rx */\n+void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,\n+\t\t\t\t  u32 rx);\n+\n+/* set interrupt mapping enable tx */\n+void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,\n+\t\t\t\t  u32 tx);\n+\n+/* set interrupt mapping rx */\n+void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx);\n+\n+/* set interrupt mapping tx */\n+void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx);\n+\n+/* set interrupt mask clear lsw */\n+void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 irq_msk_clearlsw);\n+\n+/* set interrupt mask set lsw */\n+void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw);\n+\n+/* set interrupt register reset disable */\n+void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis);\n+\n+/* set interrupt status clear lsw */\n+void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\tu32 irq_status_clearlsw);\n+\n+/* get interrupt status lsw */\n+u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw);\n+\n+/* get reset interrupt */\n+u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw);\n+\n+/* set reset interrupt */\n+void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq);\n+\n+/* rdm */\n+\n+/* set cpu id */\n+void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);\n+\n+/* set rx dca enable */\n+void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en);\n+\n+/* set rx dca mode */\n+void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode);\n+\n+/* set rx descriptor data buffer size */\n+void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_data_buff_size,\n+\t\t\t\t    u32 descriptor);\n+\n+/* set rx descriptor dca enable */\n+void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,\n+\t\t\t\t   u32 dca);\n+\n+/* set rx descriptor enable */\n+void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,\n+\t\t\t       u32 descriptor);\n+\n+/* set rx descriptor header splitting */\n+void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_head_splitting,\n+\t\t\t\t    u32 descriptor);\n+\n+/* get rx descriptor head pointer */\n+u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);\n+\n+/* set rx descriptor length */\n+void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,\n+\t\t\t\tu32 descriptor);\n+\n+/* set rx descriptor write-back interrupt enable */\n+void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 rx_desc_wr_wb_irq_en);\n+\n+/* set rx header dca enable */\n+void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,\n+\t\t\t\t   u32 dca);\n+\n+/* set rx payload dca enable */\n+void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,\n+\t\t\t\t  u32 dca);\n+\n+/* set rx descriptor header buffer size */\n+void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_head_buff_size,\n+\t\t\t\t\t   u32 descriptor);\n+\n+/* set rx descriptor reset */\n+void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,\n+\t\t\t\tu32 descriptor);\n+\n+/* Set RDM Interrupt Moderation Enable */\n+void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 rdm_intr_moder_en);\n+\n+/* reg */\n+\n+/* set general interrupt mapping register */\n+void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,\n+\t\t\t\tu32 regidx);\n+\n+/* get general interrupt status register */\n+u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw);\n+\n+/* set interrupt global control register */\n+void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl);\n+\n+/* set interrupt throttle register */\n+void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle);\n+\n+/* set rx dma descriptor base address lsw */\n+void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 rx_dma_desc_base_addrlsw,\n+\t\t\t\t\tu32 descriptor);\n+\n+/* set rx dma descriptor base address msw */\n+void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 rx_dma_desc_base_addrmsw,\n+\t\t\t\t\tu32 descriptor);\n+\n+/* get rx dma descriptor status register */\n+u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor);\n+\n+/* set rx dma descriptor tail pointer register */\n+void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 rx_dma_desc_tail_ptr,\n+\t\t\t\t  u32 descriptor);\n+\n+/* set rx filter multicast filter mask register */\n+void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\tu32 rx_flr_mcst_flr_msk);\n+\n+/* set rx filter multicast filter register */\n+void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,\n+\t\t\t\t    u32 filter);\n+\n+/* set rx filter rss control register 1 */\n+void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 rx_flr_rss_control1);\n+\n+/* Set RX Filter Control Register 2 */\n+void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw, u32 rx_flr_control2);\n+\n+/* Set RX Interrupt Moderation Control Register */\n+void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 rx_intr_moderation_ctl,\n+\t\t\t\tu32 queue);\n+\n+/* set tx dma debug control */\n+void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 tx_dma_debug_ctl);\n+\n+/* set tx dma descriptor base address lsw */\n+void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_dma_desc_base_addrlsw,\n+\t\t\t\t\tu32 descriptor);\n+\n+/* set tx dma descriptor base address msw */\n+void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_dma_desc_base_addrmsw,\n+\t\t\t\t\tu32 descriptor);\n+\n+/* set tx dma descriptor tail pointer register */\n+void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 tx_dma_desc_tail_ptr,\n+\t\t\t\t\t u32 descriptor);\n+\n+/* Set TX Interrupt Moderation Control Register */\n+void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 tx_intr_moderation_ctl,\n+\t\t\t\t       u32 queue);\n+\n+/* set global microprocessor scratch pad */\n+void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\tu32 glb_cpu_scratch_scp,\n+\t\t\t\t\tu32 scratch_scp);\n+\n+/* rpb */\n+\n+/* set dma system loopback */\n+void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk);\n+\n+/* set rx traffic class mode */\n+void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_traf_class_mode);\n+\n+/* get rx traffic class mode */\n+u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw);\n+\n+/* set rx buffer enable */\n+void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en);\n+\n+/* set rx buffer high threshold (per tc) */\n+void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 rx_buff_hi_threshold_per_tc,\n+\t\t\t\t\t\tu32 buffer);\n+\n+/* set rx buffer low threshold (per tc) */\n+void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 rx_buff_lo_threshold_per_tc,\n+\t\t\t\t\t u32 buffer);\n+\n+/* set rx flow control mode */\n+void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode);\n+\n+/* set rx packet buffer size (per tc) */\n+void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 rx_pkt_buff_size_per_tc,\n+\t\t\t\t\t    u32 buffer);\n+\n+/* set rx xoff enable (per tc) */\n+void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,\n+\t\t\t\t      u32 buffer);\n+\n+/* rpf */\n+\n+/* set l2 broadcast count threshold */\n+void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 l2broadcast_count_threshold);\n+\n+/* set l2 broadcast enable */\n+void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en);\n+\n+/* set l2 broadcast filter action */\n+void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 l2broadcast_flr_act);\n+\n+/* set l2 multicast filter enable */\n+void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 l2multicast_flr_en,\n+\t\t\t\t      u32 filter);\n+\n+/* set l2 promiscuous mode enable */\n+void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 l2promiscuous_mode_en);\n+\n+/* set l2 unicast filter action */\n+void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 l2unicast_flr_act,\n+\t\t\t\t     u32 filter);\n+\n+/* set l2 unicast filter enable */\n+void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,\n+\t\t\t\tu32 filter);\n+\n+/* set l2 unicast destination address lsw */\n+void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 l2unicast_dest_addresslsw,\n+\t\t\t\t      u32 filter);\n+\n+/* set l2 unicast destination address msw */\n+void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 l2unicast_dest_addressmsw,\n+\t\t\t\t      u32 filter);\n+\n+/* Set L2 Accept all Multicast packets */\n+void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 l2_accept_all_mc_packets);\n+\n+/* set user-priority tc mapping */\n+void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 user_priority_tc_map, u32 tc);\n+\n+/* set rss key address */\n+void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr);\n+\n+/* set rss key write data */\n+void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data);\n+\n+/* get rss key write enable */\n+u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw);\n+\n+/* set rss key write enable */\n+void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en);\n+\n+/* set rss redirection table address */\n+void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 rss_redir_tbl_addr);\n+\n+/* set rss redirection table write data */\n+void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 rss_redir_tbl_wr_data);\n+\n+/* get rss redirection write enable */\n+u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw);\n+\n+/* set rss redirection write enable */\n+void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en);\n+\n+/* set tpo to rpf system loopback */\n+void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 tpo_to_rpf_sys_lbk);\n+\n+/* set vlan inner ethertype */\n+void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht);\n+\n+/* set vlan outer ethertype */\n+void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht);\n+\n+/* set vlan promiscuous mode enable */\n+void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 vlan_prom_mode_en);\n+\n+/* Set VLAN untagged action */\n+void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 vlan_untagged_act);\n+\n+/* Set VLAN accept untagged packets */\n+void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t u32 vlan_acc_untagged_packets);\n+\n+/* Set VLAN filter enable */\n+void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,\n+\t\t\t\tu32 filter);\n+\n+/* Set VLAN Filter Action */\n+void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,\n+\t\t\t\t u32 filter);\n+\n+/* Set VLAN ID Filter */\n+void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,\n+\t\t\t\tu32 filter);\n+\n+/* set ethertype filter enable */\n+void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,\n+\t\t\t\tu32 filter);\n+\n+/* set  ethertype user-priority enable */\n+void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 etht_user_priority_en,\n+\t\t\t\t\t  u32 filter);\n+\n+/* set  ethertype rx queue enable */\n+void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t     u32 etht_rx_queue_en,\n+\t\t\t\t     u32 filter);\n+\n+/* set ethertype rx queue */\n+void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,\n+\t\t\t\t  u32 filter);\n+\n+/* set ethertype user-priority */\n+void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 etht_user_priority,\n+\t\t\t\t       u32 filter);\n+\n+/* set ethertype management queue */\n+void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,\n+\t\t\t\t   u32 filter);\n+\n+/* set ethertype filter action */\n+void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,\n+\t\t\t\t u32 filter);\n+\n+/* set ethertype filter */\n+void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);\n+\n+/* rpo */\n+\n+/* set ipv4 header checksum offload enable */\n+void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 ipv4header_crc_offload_en);\n+\n+/* set rx descriptor vlan stripping */\n+void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 rx_desc_vlan_stripping,\n+\t\t\t\t\t   u32 descriptor);\n+\n+/* set tcp/udp checksum offload enable */\n+void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 tcp_udp_crc_offload_en);\n+\n+/* Set LRO Patch Optimization Enable. */\n+void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 lro_patch_optimization_en);\n+\n+/* Set Large Receive Offload Enable */\n+void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en);\n+\n+/* Set LRO Q Sessions Limit */\n+void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 lro_qsessions_lim);\n+\n+/* Set LRO Total Descriptor Limit */\n+void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t       u32 lro_total_desc_lim);\n+\n+/* Set LRO Min Payload of First Packet */\n+void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 lro_min_pld_of_first_pkt);\n+\n+/* Set LRO Packet Limit */\n+void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_packet_lim);\n+\n+/* Set LRO Max Number of Descriptors */\n+void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 lro_max_desc_num, u32 lro);\n+\n+/* Set LRO Time Base Divider */\n+void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 lro_time_base_divider);\n+\n+/*Set LRO Inactive Interval */\n+void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 lro_inactive_interval);\n+\n+/*Set LRO Max Coalescing Interval */\n+void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 lro_max_coal_interval);\n+\n+/* rx */\n+\n+/* set rx register reset disable */\n+void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis);\n+\n+/* tdm */\n+\n+/* set cpu id */\n+void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca);\n+\n+/* set large send offload enable */\n+void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t  u32 large_send_offload_en);\n+\n+/* set tx descriptor enable */\n+void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,\n+\t\t\t       u32 descriptor);\n+\n+/* set tx dca enable */\n+void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en);\n+\n+/* set tx dca mode */\n+void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode);\n+\n+/* set tx descriptor dca enable */\n+void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,\n+\t\t\t\t   u32 dca);\n+\n+/* get tx descriptor head pointer */\n+u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor);\n+\n+/* set tx descriptor length */\n+void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,\n+\t\t\t\tu32 descriptor);\n+\n+/* set tx descriptor write-back interrupt enable */\n+void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t u32 tx_desc_wr_wb_irq_en);\n+\n+/* set tx descriptor write-back threshold */\n+void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 tx_desc_wr_wb_threshold,\n+\t\t\t\t     u32 descriptor);\n+\n+/* Set TDM Interrupt Moderation Enable */\n+void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 tdm_irq_moderation_en);\n+/* thm */\n+\n+/* set lso tcp flag of first packet */\n+void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 lso_tcp_flag_of_first_pkt);\n+\n+/* set lso tcp flag of last packet */\n+void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t     u32 lso_tcp_flag_of_last_pkt);\n+\n+/* set lso tcp flag of middle packet */\n+void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 lso_tcp_flag_of_middle_pkt);\n+\n+/* tpb */\n+\n+/* set TX Traffic Class Mode */\n+void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw, u32 tx_traf_class_mode);\n+\n+/* get TX Traffic Class Mode */\n+u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw);\n+\n+/* set tx buffer enable */\n+void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en);\n+\n+/* set tx buffer high threshold (per tc) */\n+void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 tx_buff_hi_threshold_per_tc,\n+\t\t\t\t\t u32 buffer);\n+\n+/* set tx buffer low threshold (per tc) */\n+void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\tu32 tx_buff_lo_threshold_per_tc,\n+\t\t\t\t\t u32 buffer);\n+\n+/* set tx dma system loopback enable */\n+void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en);\n+\n+/* set tx packet buffer size (per tc) */\n+void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t    u32 tx_pkt_buff_size_per_tc, u32 buffer);\n+\n+/* set tx path pad insert enable */\n+void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en);\n+\n+/* tpo */\n+\n+/* set ipv4 header checksum offload enable */\n+void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 ipv4header_crc_offload_en);\n+\n+/* set tcp/udp checksum offload enable */\n+void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t   u32 tcp_udp_crc_offload_en);\n+\n+/* set tx pkt system loopback enable */\n+void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t      u32 tx_pkt_sys_lbk_en);\n+\n+/* tps */\n+\n+/* set tx packet scheduler data arbitration mode */\n+void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 tx_pkt_shed_data_arb_mode);\n+\n+/* set tx packet scheduler descriptor rate current time reset */\n+void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t\tu32 curr_time_res);\n+\n+/* set tx packet scheduler descriptor rate limit */\n+void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t      u32 tx_pkt_shed_desc_rate_lim);\n+\n+/* set tx packet scheduler descriptor tc arbitration mode */\n+void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t u32 arb_mode);\n+\n+/* set tx packet scheduler descriptor tc max credit */\n+void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t   u32 max_credit,\n+\t\t\t\t\t    u32 tc);\n+\n+/* set tx packet scheduler descriptor tc weight */\n+void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_pkt_shed_desc_tc_weight,\n+\t\t\t\t\tu32 tc);\n+\n+/* set tx packet scheduler descriptor vm arbitration mode */\n+void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t u32 arb_mode);\n+\n+/* set tx packet scheduler tc data max credit */\n+void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t\t   u32 max_credit,\n+\t\t\t\t\t    u32 tc);\n+\n+/* set tx packet scheduler tc data weight */\n+void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 tx_pkt_shed_tc_data_weight,\n+\t\t\t\t\tu32 tc);\n+\n+/* tx */\n+\n+/* set tx register reset disable */\n+void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis);\n+\n+/* msm */\n+\n+/* get register access status */\n+u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw);\n+\n+/* set  register address for indirect address */\n+void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,\n+\t\t\t\t\t       u32 reg_addr_for_indirect_addr);\n+\n+/* set register read strobe */\n+void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe);\n+\n+/* get  register read data */\n+u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw);\n+\n+/* set  register write data */\n+void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data);\n+\n+/* set register write strobe */\n+void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe);\n+\n+/* pci */\n+\n+/* set pci register reset disable */\n+void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);\n+\n+/* set uP Force Interrupt */\n+void mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr);\n+\n+\n+#endif /* HW_ATL_LLH_H */\ndiff --git a/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h\nnew file mode 100644\nindex 000000000..14d99c463\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_llh_internal.h\n@@ -0,0 +1,2413 @@\n+/*\n+ * aQuantia Corporation Network Driver\n+ * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ */\n+\n+/* File hw_atl_llh_internal.h: Preprocessor definitions\n+ * for Atlantic registers.\n+ */\n+\n+#ifndef HW_ATL_LLH_INTERNAL_H\n+#define HW_ATL_LLH_INTERNAL_H\n+\n+/* global microprocessor semaphore  definitions\n+ * base address: 0x000003a0\n+ * parameter: semaphore {s} | stride size 0x4 | range [0, 15]\n+ */\n+#define HW_ATL_GLB_CPU_SEM_ADR(semaphore)  (0x000003a0u + (semaphore) * 0x4)\n+/* register address for bitfield rx dma good octet counter lsw [1f:0] */\n+#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808\n+/* register address for bitfield rx dma good packet counter lsw [1f:0] */\n+#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800\n+/* register address for bitfield tx dma good octet counter lsw [1f:0] */\n+#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808\n+/* register address for bitfield tx dma good packet counter lsw [1f:0] */\n+#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800\n+\n+/* register address for bitfield rx dma good octet counter msw [3f:20] */\n+#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c\n+/* register address for bitfield rx dma good packet counter msw [3f:20] */\n+#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804\n+/* register address for bitfield tx dma good octet counter msw [3f:20] */\n+#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c\n+/* register address for bitfield tx dma good packet counter msw [3f:20] */\n+#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804\n+\n+/* preprocessor definitions for msm rx errors counter register */\n+#define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u\n+\n+/* preprocessor definitions for msm rx unicast frames counter register */\n+#define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u\n+\n+/* preprocessor definitions for msm rx multicast frames counter register */\n+#define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u\n+\n+/* preprocessor definitions for msm rx broadcast frames counter register */\n+#define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u\n+\n+/* preprocessor definitions for msm rx broadcast octets counter register 1 */\n+#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u\n+\n+/* preprocessor definitions for msm rx broadcast octets counter register 2 */\n+#define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u\n+\n+/* preprocessor definitions for msm rx unicast octets counter register 0 */\n+#define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u\n+\n+/* preprocessor definitions for msm tx unicast frames counter register */\n+#define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u\n+\n+/* preprocessor definitions for msm tx multicast frames counter register */\n+#define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u\n+\n+/* preprocessor definitions for global mif identification */\n+#define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu\n+\n+/* register address for bitfield iamr_lsw[1f:0] */\n+#define HW_ATL_ITR_IAMRLSW_ADR 0x00002090\n+/* register address for bitfield rx dma drop packet counter [1f:0] */\n+#define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818\n+\n+/* register address for bitfield imcr_lsw[1f:0] */\n+#define HW_ATL_ITR_IMCRLSW_ADR 0x00002070\n+/* register address for bitfield imsr_lsw[1f:0] */\n+#define HW_ATL_ITR_IMSRLSW_ADR 0x00002060\n+/* register address for bitfield itr_reg_res_dsbl */\n+#define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300\n+/* bitmask for bitfield itr_reg_res_dsbl */\n+#define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000\n+/* lower bit position of bitfield itr_reg_res_dsbl */\n+#define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29\n+/* register address for bitfield iscr_lsw[1f:0] */\n+#define HW_ATL_ITR_ISCRLSW_ADR 0x00002050\n+/* register address for bitfield isr_lsw[1f:0] */\n+#define HW_ATL_ITR_ISRLSW_ADR 0x00002000\n+/* register address for bitfield itr_reset */\n+#define HW_ATL_ITR_RES_ADR 0x00002300\n+/* bitmask for bitfield itr_reset */\n+#define HW_ATL_ITR_RES_MSK 0x80000000\n+/* lower bit position of bitfield itr_reset */\n+#define HW_ATL_ITR_RES_SHIFT 31\n+/* register address for bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4)\n+/* bitmask for bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff\n+/* lower bit position of bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_RDM_DCADCPUID_SHIFT 0\n+/* register address for bitfield dca_en */\n+#define HW_ATL_RDM_DCA_EN_ADR 0x00006180\n+\n+/* rx dca_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca_en\".\n+ * port=\"pif_rdm_dca_en_i\"\n+ */\n+\n+/* register address for bitfield dca_en */\n+#define HW_ATL_RDM_DCA_EN_ADR 0x00006180\n+/* bitmask for bitfield dca_en */\n+#define HW_ATL_RDM_DCA_EN_MSK 0x80000000\n+/* inverted bitmask for bitfield dca_en */\n+#define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff\n+/* lower bit position of bitfield dca_en */\n+#define HW_ATL_RDM_DCA_EN_SHIFT 31\n+/* width of bitfield dca_en */\n+#define HW_ATL_RDM_DCA_EN_WIDTH 1\n+/* default value of bitfield dca_en */\n+#define HW_ATL_RDM_DCA_EN_DEFAULT 0x1\n+\n+/* rx dca_mode[3:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca_mode[3:0]\".\n+ * port=\"pif_rdm_dca_mode_i[3:0]\"\n+ */\n+\n+/* register address for bitfield dca_mode[3:0] */\n+#define HW_ATL_RDM_DCA_MODE_ADR 0x00006180\n+/* bitmask for bitfield dca_mode[3:0] */\n+#define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f\n+/* inverted bitmask for bitfield dca_mode[3:0] */\n+#define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0\n+/* lower bit position of bitfield dca_mode[3:0] */\n+#define HW_ATL_RDM_DCA_MODE_SHIFT 0\n+/* width of bitfield dca_mode[3:0] */\n+#define HW_ATL_RDM_DCA_MODE_WIDTH 4\n+/* default value of bitfield dca_mode[3:0] */\n+#define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0\n+\n+/* rx desc{d}_data_size[4:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_data_size[4:0]\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"pif_rdm_desc0_data_size_i[4:0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_data_size[4:0] */\n+#define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \\\n+\t(0x00005b18 + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_data_size[4:0] */\n+#define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f\n+/* inverted bitmask for bitfield desc{d}_data_size[4:0] */\n+#define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0\n+/* lower bit position of bitfield desc{d}_data_size[4:0] */\n+#define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0\n+/* width of bitfield desc{d}_data_size[4:0] */\n+#define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5\n+/* default value of bitfield desc{d}_data_size[4:0] */\n+#define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0\n+\n+/* rx dca{d}_desc_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca{d}_desc_en\".\n+ * parameter: dca {d} | stride size 0x4 | range [0, 31]\n+ * port=\"pif_rdm_dca_desc_en_i[0]\"\n+ */\n+\n+/* register address for bitfield dca{d}_desc_en */\n+#define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4)\n+/* bitmask for bitfield dca{d}_desc_en */\n+#define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000\n+/* inverted bitmask for bitfield dca{d}_desc_en */\n+#define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff\n+/* lower bit position of bitfield dca{d}_desc_en */\n+#define HW_ATL_RDM_DCADDESC_EN_SHIFT 31\n+/* width of bitfield dca{d}_desc_en */\n+#define HW_ATL_RDM_DCADDESC_EN_WIDTH 1\n+/* default value of bitfield dca{d}_desc_en */\n+#define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0\n+\n+/* rx desc{d}_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_en\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"pif_rdm_desc_en_i[0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_en */\n+#define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_en */\n+#define HW_ATL_RDM_DESCDEN_MSK 0x80000000\n+/* inverted bitmask for bitfield desc{d}_en */\n+#define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff\n+/* lower bit position of bitfield desc{d}_en */\n+#define HW_ATL_RDM_DESCDEN_SHIFT 31\n+/* width of bitfield desc{d}_en */\n+#define HW_ATL_RDM_DESCDEN_WIDTH 1\n+/* default value of bitfield desc{d}_en */\n+#define HW_ATL_RDM_DESCDEN_DEFAULT 0x0\n+\n+/* rx desc{d}_hdr_size[4:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_hdr_size[4:0]\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"pif_rdm_desc0_hdr_size_i[4:0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_hdr_size[4:0] */\n+#define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \\\n+\t(0x00005b18 + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_hdr_size[4:0] */\n+#define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00\n+/* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */\n+#define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff\n+/* lower bit position of bitfield desc{d}_hdr_size[4:0] */\n+#define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8\n+/* width of bitfield desc{d}_hdr_size[4:0] */\n+#define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5\n+/* default value of bitfield desc{d}_hdr_size[4:0] */\n+#define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0\n+\n+/* rx desc{d}_hdr_split bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_hdr_split\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"pif_rdm_desc_hdr_split_i[0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_hdr_split */\n+#define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \\\n+\t(0x00005b08 + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_hdr_split */\n+#define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000\n+/* inverted bitmask for bitfield desc{d}_hdr_split */\n+#define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff\n+/* lower bit position of bitfield desc{d}_hdr_split */\n+#define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28\n+/* width of bitfield desc{d}_hdr_split */\n+#define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1\n+/* default value of bitfield desc{d}_hdr_split */\n+#define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0\n+\n+/* rx desc{d}_hd[c:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_hd[c:0]\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"rdm_pif_desc0_hd_o[12:0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_RDM_DESCDHD_MSK 0x00001fff\n+/* inverted bitmask for bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000\n+/* lower bit position of bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_RDM_DESCDHD_SHIFT 0\n+/* width of bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_RDM_DESCDHD_WIDTH 13\n+\n+/* rx desc{d}_len[9:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_len[9:0]\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"pif_rdm_desc0_len_i[9:0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_len[9:0] */\n+#define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_len[9:0] */\n+#define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8\n+/* inverted bitmask for bitfield desc{d}_len[9:0] */\n+#define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007\n+/* lower bit position of bitfield desc{d}_len[9:0] */\n+#define HW_ATL_RDM_DESCDLEN_SHIFT 3\n+/* width of bitfield desc{d}_len[9:0] */\n+#define HW_ATL_RDM_DESCDLEN_WIDTH 10\n+/* default value of bitfield desc{d}_len[9:0] */\n+#define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0\n+\n+/* rx desc{d}_reset bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_reset\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"pif_rdm_q_pf_res_i[0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_reset */\n+#define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_reset */\n+#define HW_ATL_RDM_DESCDRESET_MSK 0x02000000\n+/* inverted bitmask for bitfield desc{d}_reset */\n+#define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff\n+/* lower bit position of bitfield desc{d}_reset */\n+#define HW_ATL_RDM_DESCDRESET_SHIFT 25\n+/* width of bitfield desc{d}_reset */\n+#define HW_ATL_RDM_DESCDRESET_WIDTH 1\n+/* default value of bitfield desc{d}_reset */\n+#define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0\n+\n+/* rx int_desc_wrb_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"int_desc_wrb_en\".\n+ * port=\"pif_rdm_int_desc_wrb_en_i\"\n+ */\n+\n+/* register address for bitfield int_desc_wrb_en */\n+#define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30\n+/* bitmask for bitfield int_desc_wrb_en */\n+#define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004\n+/* inverted bitmask for bitfield int_desc_wrb_en */\n+#define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb\n+/* lower bit position of bitfield int_desc_wrb_en */\n+#define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2\n+/* width of bitfield int_desc_wrb_en */\n+#define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1\n+/* default value of bitfield int_desc_wrb_en */\n+#define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0\n+\n+/* rx dca{d}_hdr_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca{d}_hdr_en\".\n+ * parameter: dca {d} | stride size 0x4 | range [0, 31]\n+ * port=\"pif_rdm_dca_hdr_en_i[0]\"\n+ */\n+\n+/* register address for bitfield dca{d}_hdr_en */\n+#define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4)\n+/* bitmask for bitfield dca{d}_hdr_en */\n+#define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000\n+/* inverted bitmask for bitfield dca{d}_hdr_en */\n+#define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff\n+/* lower bit position of bitfield dca{d}_hdr_en */\n+#define HW_ATL_RDM_DCADHDR_EN_SHIFT 30\n+/* width of bitfield dca{d}_hdr_en */\n+#define HW_ATL_RDM_DCADHDR_EN_WIDTH 1\n+/* default value of bitfield dca{d}_hdr_en */\n+#define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0\n+\n+/* rx dca{d}_pay_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca{d}_pay_en\".\n+ * parameter: dca {d} | stride size 0x4 | range [0, 31]\n+ * port=\"pif_rdm_dca_pay_en_i[0]\"\n+ */\n+\n+/* register address for bitfield dca{d}_pay_en */\n+#define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4)\n+/* bitmask for bitfield dca{d}_pay_en */\n+#define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000\n+/* inverted bitmask for bitfield dca{d}_pay_en */\n+#define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff\n+/* lower bit position of bitfield dca{d}_pay_en */\n+#define HW_ATL_RDM_DCADPAY_EN_SHIFT 29\n+/* width of bitfield dca{d}_pay_en */\n+#define HW_ATL_RDM_DCADPAY_EN_WIDTH 1\n+/* default value of bitfield dca{d}_pay_en */\n+#define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0\n+\n+/* RX rdm_int_rim_en Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"rdm_int_rim_en\".\n+ * PORT=\"pif_rdm_int_rim_en_i\"\n+ */\n+\n+/* Register address for bitfield rdm_int_rim_en */\n+#define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30\n+/* Bitmask for bitfield rdm_int_rim_en */\n+#define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008\n+/* Inverted bitmask for bitfield rdm_int_rim_en */\n+#define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7\n+/* Lower bit position of bitfield rdm_int_rim_en */\n+#define HW_ATL_RDM_INT_RIM_EN_SHIFT 3\n+/* Width of bitfield rdm_int_rim_en */\n+#define HW_ATL_RDM_INT_RIM_EN_WIDTH 1\n+/* Default value of bitfield rdm_int_rim_en */\n+#define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0\n+\n+/* general interrupt mapping register definitions\n+ * preprocessor definitions for general interrupt mapping register\n+ * base address: 0x00002180\n+ * parameter: regidx {f} | stride size 0x4 | range [0, 3]\n+ */\n+#define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4)\n+\n+/* general interrupt status register definitions\n+ * preprocessor definitions for general interrupt status register\n+ * address: 0x000021A0\n+ */\n+\n+#define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U\n+\n+/* interrupt global control register  definitions\n+ * preprocessor definitions for interrupt global control register\n+ * address: 0x00002300\n+ */\n+#define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u\n+\n+/* interrupt throttle register definitions\n+ * preprocessor definitions for interrupt throttle register\n+ * base address: 0x00002800\n+ * parameter: throttle {t} | stride size 0x4 | range [0, 31]\n+ */\n+#define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4)\n+\n+/* rx dma descriptor base address lsw definitions\n+ * preprocessor definitions for rx dma descriptor base address lsw\n+ * base address: 0x00005b00\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ */\n+#define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \\\n+(0x00005b00u + (descriptor) * 0x20)\n+\n+/* rx dma descriptor base address msw definitions\n+ * preprocessor definitions for rx dma descriptor base address msw\n+ * base address: 0x00005b04\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ */\n+#define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \\\n+(0x00005b04u + (descriptor) * 0x20)\n+\n+/* rx dma descriptor status register definitions\n+ * preprocessor definitions for rx dma descriptor status register\n+ * base address: 0x00005b14\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ */\n+#define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \\\n+\t(0x00005b14u + (descriptor) * 0x20)\n+\n+/* rx dma descriptor tail pointer register definitions\n+ * preprocessor definitions for rx dma descriptor tail pointer register\n+ * base address: 0x00005b10\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ */\n+#define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \\\n+\t(0x00005b10u + (descriptor) * 0x20)\n+\n+/* rx interrupt moderation control register definitions\n+ * Preprocessor definitions for RX Interrupt Moderation Control Register\n+ * Base Address: 0x00005A40\n+ * Parameter: RIM {R} | stride size 0x4 | range [0, 31]\n+ */\n+#define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4)\n+\n+/* rx filter multicast filter mask register definitions\n+ * preprocessor definitions for rx filter multicast filter mask register\n+ * address: 0x00005270\n+ */\n+#define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u\n+\n+/* rx filter multicast filter register definitions\n+ * preprocessor definitions for rx filter multicast filter register\n+ * base address: 0x00005250\n+ * parameter: filter {f} | stride size 0x4 | range [0, 7]\n+ */\n+#define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4)\n+\n+/* RX Filter RSS Control Register 1 Definitions\n+ * Preprocessor definitions for RX Filter RSS Control Register 1\n+ * Address: 0x000054C0\n+ */\n+#define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u\n+\n+/* RX Filter Control Register 2 Definitions\n+ * Preprocessor definitions for RX Filter Control Register 2\n+ * Address: 0x00005104\n+ */\n+#define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u\n+\n+/* tx tx dma debug control [1f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"tx dma debug control [1f:0]\".\n+ * port=\"pif_tdm_debug_cntl_i[31:0]\"\n+ */\n+\n+/* register address for bitfield tx dma debug control [1f:0] */\n+#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920\n+/* bitmask for bitfield tx dma debug control [1f:0] */\n+#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff\n+/* inverted bitmask for bitfield tx dma debug control [1f:0] */\n+#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000\n+/* lower bit position of bitfield tx dma debug control [1f:0] */\n+#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0\n+/* width of bitfield tx dma debug control [1f:0] */\n+#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32\n+/* default value of bitfield tx dma debug control [1f:0] */\n+#define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0\n+\n+/* tx dma descriptor base address lsw definitions\n+ * preprocessor definitions for tx dma descriptor base address lsw\n+ * base address: 0x00007c00\n+ * parameter: descriptor {d} | stride size 0x40 | range [0, 31]\n+ */\n+#define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \\\n+\t(0x00007c00u + (descriptor) * 0x40)\n+\n+/* tx dma descriptor tail pointer register definitions\n+ * preprocessor definitions for tx dma descriptor tail pointer register\n+ * base address: 0x00007c10\n+ *  parameter: descriptor {d} | stride size 0x40 | range [0, 31]\n+ */\n+#define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \\\n+\t(0x00007c10u + (descriptor) * 0x40)\n+\n+/* rx dma_sys_loopback bitfield definitions\n+ * preprocessor definitions for the bitfield \"dma_sys_loopback\".\n+ * port=\"pif_rpb_dma_sys_lbk_i\"\n+ */\n+\n+/* register address for bitfield dma_sys_loopback */\n+#define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000\n+/* bitmask for bitfield dma_sys_loopback */\n+#define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040\n+/* inverted bitmask for bitfield dma_sys_loopback */\n+#define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf\n+/* lower bit position of bitfield dma_sys_loopback */\n+#define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6\n+/* width of bitfield dma_sys_loopback */\n+#define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1\n+/* default value of bitfield dma_sys_loopback */\n+#define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0\n+\n+/* rx rx_tc_mode bitfield definitions\n+ * preprocessor definitions for the bitfield \"rx_tc_mode\".\n+ * port=\"pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i\"\n+ */\n+\n+/* register address for bitfield rx_tc_mode */\n+#define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700\n+/* bitmask for bitfield rx_tc_mode */\n+#define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100\n+/* inverted bitmask for bitfield rx_tc_mode */\n+#define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff\n+/* lower bit position of bitfield rx_tc_mode */\n+#define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8\n+/* width of bitfield rx_tc_mode */\n+#define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1\n+/* default value of bitfield rx_tc_mode */\n+#define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0\n+\n+/* rx rx_buf_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"rx_buf_en\".\n+ * port=\"pif_rpb_rx_buf_en_i\"\n+ */\n+\n+/* register address for bitfield rx_buf_en */\n+#define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700\n+/* bitmask for bitfield rx_buf_en */\n+#define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001\n+/* inverted bitmask for bitfield rx_buf_en */\n+#define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe\n+/* lower bit position of bitfield rx_buf_en */\n+#define HW_ATL_RPB_RX_BUF_EN_SHIFT 0\n+/* width of bitfield rx_buf_en */\n+#define HW_ATL_RPB_RX_BUF_EN_WIDTH 1\n+/* default value of bitfield rx_buf_en */\n+#define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0\n+\n+/* rx rx{b}_hi_thresh[d:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rx{b}_hi_thresh[d:0]\".\n+ * parameter: buffer {b} | stride size 0x10 | range [0, 7]\n+ * port=\"pif_rpb_rx0_hi_thresh_i[13:0]\"\n+ */\n+\n+/* register address for bitfield rx{b}_hi_thresh[d:0] */\n+#define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10)\n+/* bitmask for bitfield rx{b}_hi_thresh[d:0] */\n+#define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000\n+/* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */\n+#define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff\n+/* lower bit position of bitfield rx{b}_hi_thresh[d:0] */\n+#define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16\n+/* width of bitfield rx{b}_hi_thresh[d:0] */\n+#define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14\n+/* default value of bitfield rx{b}_hi_thresh[d:0] */\n+#define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0\n+\n+/* rx rx{b}_lo_thresh[d:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rx{b}_lo_thresh[d:0]\".\n+ * parameter: buffer {b} | stride size 0x10 | range [0, 7]\n+ * port=\"pif_rpb_rx0_lo_thresh_i[13:0]\"\n+ */\n+\n+/* register address for bitfield rx{b}_lo_thresh[d:0] */\n+#define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10)\n+/* bitmask for bitfield rx{b}_lo_thresh[d:0] */\n+#define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff\n+/* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */\n+#define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000\n+/* lower bit position of bitfield rx{b}_lo_thresh[d:0] */\n+#define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0\n+/* width of bitfield rx{b}_lo_thresh[d:0] */\n+#define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14\n+/* default value of bitfield rx{b}_lo_thresh[d:0] */\n+#define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0\n+\n+/* rx rx_fc_mode[1:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rx_fc_mode[1:0]\".\n+ * port=\"pif_rpb_rx_fc_mode_i[1:0]\"\n+ */\n+\n+/* register address for bitfield rx_fc_mode[1:0] */\n+#define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700\n+/* bitmask for bitfield rx_fc_mode[1:0] */\n+#define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030\n+/* inverted bitmask for bitfield rx_fc_mode[1:0] */\n+#define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf\n+/* lower bit position of bitfield rx_fc_mode[1:0] */\n+#define HW_ATL_RPB_RX_FC_MODE_SHIFT 4\n+/* width of bitfield rx_fc_mode[1:0] */\n+#define HW_ATL_RPB_RX_FC_MODE_WIDTH 2\n+/* default value of bitfield rx_fc_mode[1:0] */\n+#define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0\n+\n+/* rx rx{b}_buf_size[8:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rx{b}_buf_size[8:0]\".\n+ * parameter: buffer {b} | stride size 0x10 | range [0, 7]\n+ * port=\"pif_rpb_rx0_buf_size_i[8:0]\"\n+ */\n+\n+/* register address for bitfield rx{b}_buf_size[8:0] */\n+#define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10)\n+/* bitmask for bitfield rx{b}_buf_size[8:0] */\n+#define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff\n+/* inverted bitmask for bitfield rx{b}_buf_size[8:0] */\n+#define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00\n+/* lower bit position of bitfield rx{b}_buf_size[8:0] */\n+#define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0\n+/* width of bitfield rx{b}_buf_size[8:0] */\n+#define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9\n+/* default value of bitfield rx{b}_buf_size[8:0] */\n+#define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0\n+\n+/* rx rx{b}_xoff_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"rx{b}_xoff_en\".\n+ * parameter: buffer {b} | stride size 0x10 | range [0, 7]\n+ * port=\"pif_rpb_rx_xoff_en_i[0]\"\n+ */\n+\n+/* register address for bitfield rx{b}_xoff_en */\n+#define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10)\n+/* bitmask for bitfield rx{b}_xoff_en */\n+#define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000\n+/* inverted bitmask for bitfield rx{b}_xoff_en */\n+#define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff\n+/* lower bit position of bitfield rx{b}_xoff_en */\n+#define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31\n+/* width of bitfield rx{b}_xoff_en */\n+#define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1\n+/* default value of bitfield rx{b}_xoff_en */\n+#define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0\n+\n+/* rx l2_bc_thresh[f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"l2_bc_thresh[f:0]\".\n+ * port=\"pif_rpf_l2_bc_thresh_i[15:0]\"\n+ */\n+\n+/* register address for bitfield l2_bc_thresh[f:0] */\n+#define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100\n+/* bitmask for bitfield l2_bc_thresh[f:0] */\n+#define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000\n+/* inverted bitmask for bitfield l2_bc_thresh[f:0] */\n+#define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff\n+/* lower bit position of bitfield l2_bc_thresh[f:0] */\n+#define HW_ATL_RPFL2BC_THRESH_SHIFT 16\n+/* width of bitfield l2_bc_thresh[f:0] */\n+#define HW_ATL_RPFL2BC_THRESH_WIDTH 16\n+/* default value of bitfield l2_bc_thresh[f:0] */\n+#define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0\n+\n+/* rx l2_bc_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"l2_bc_en\".\n+ * port=\"pif_rpf_l2_bc_en_i\"\n+ */\n+\n+/* register address for bitfield l2_bc_en */\n+#define HW_ATL_RPFL2BC_EN_ADR 0x00005100\n+/* bitmask for bitfield l2_bc_en */\n+#define HW_ATL_RPFL2BC_EN_MSK 0x00000001\n+/* inverted bitmask for bitfield l2_bc_en */\n+#define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe\n+/* lower bit position of bitfield l2_bc_en */\n+#define HW_ATL_RPFL2BC_EN_SHIFT 0\n+/* width of bitfield l2_bc_en */\n+#define HW_ATL_RPFL2BC_EN_WIDTH 1\n+/* default value of bitfield l2_bc_en */\n+#define HW_ATL_RPFL2BC_EN_DEFAULT 0x0\n+\n+/* rx l2_bc_act[2:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"l2_bc_act[2:0]\".\n+ * port=\"pif_rpf_l2_bc_act_i[2:0]\"\n+ */\n+\n+/* register address for bitfield l2_bc_act[2:0] */\n+#define HW_ATL_RPFL2BC_ACT_ADR 0x00005100\n+/* bitmask for bitfield l2_bc_act[2:0] */\n+#define HW_ATL_RPFL2BC_ACT_MSK 0x00007000\n+/* inverted bitmask for bitfield l2_bc_act[2:0] */\n+#define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff\n+/* lower bit position of bitfield l2_bc_act[2:0] */\n+#define HW_ATL_RPFL2BC_ACT_SHIFT 12\n+/* width of bitfield l2_bc_act[2:0] */\n+#define HW_ATL_RPFL2BC_ACT_WIDTH 3\n+/* default value of bitfield l2_bc_act[2:0] */\n+#define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0\n+\n+/* rx l2_mc_en{f} bitfield definitions\n+ * preprocessor definitions for the bitfield \"l2_mc_en{f}\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 7]\n+ * port=\"pif_rpf_l2_mc_en_i[0]\"\n+ */\n+\n+/* register address for bitfield l2_mc_en{f} */\n+#define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4)\n+/* bitmask for bitfield l2_mc_en{f} */\n+#define HW_ATL_RPFL2MC_ENF_MSK 0x80000000\n+/* inverted bitmask for bitfield l2_mc_en{f} */\n+#define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff\n+/* lower bit position of bitfield l2_mc_en{f} */\n+#define HW_ATL_RPFL2MC_ENF_SHIFT 31\n+/* width of bitfield l2_mc_en{f} */\n+#define HW_ATL_RPFL2MC_ENF_WIDTH 1\n+/* default value of bitfield l2_mc_en{f} */\n+#define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0\n+\n+/* rx l2_promis_mode bitfield definitions\n+ * preprocessor definitions for the bitfield \"l2_promis_mode\".\n+ * port=\"pif_rpf_l2_promis_mode_i\"\n+ */\n+\n+/* register address for bitfield l2_promis_mode */\n+#define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100\n+/* bitmask for bitfield l2_promis_mode */\n+#define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008\n+/* inverted bitmask for bitfield l2_promis_mode */\n+#define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7\n+/* lower bit position of bitfield l2_promis_mode */\n+#define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3\n+/* width of bitfield l2_promis_mode */\n+#define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1\n+/* default value of bitfield l2_promis_mode */\n+#define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0\n+\n+/* rx l2_uc_act{f}[2:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"l2_uc_act{f}[2:0]\".\n+ * parameter: filter {f} | stride size 0x8 | range [0, 37]\n+ * port=\"pif_rpf_l2_uc_act0_i[2:0]\"\n+ */\n+\n+/* register address for bitfield l2_uc_act{f}[2:0] */\n+#define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8)\n+/* bitmask for bitfield l2_uc_act{f}[2:0] */\n+#define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000\n+/* inverted bitmask for bitfield l2_uc_act{f}[2:0] */\n+#define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff\n+/* lower bit position of bitfield l2_uc_act{f}[2:0] */\n+#define HW_ATL_RPFL2UC_ACTF_SHIFT 16\n+/* width of bitfield l2_uc_act{f}[2:0] */\n+#define HW_ATL_RPFL2UC_ACTF_WIDTH 3\n+/* default value of bitfield l2_uc_act{f}[2:0] */\n+#define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0\n+\n+/* rx l2_uc_en{f} bitfield definitions\n+ * preprocessor definitions for the bitfield \"l2_uc_en{f}\".\n+ * parameter: filter {f} | stride size 0x8 | range [0, 37]\n+ * port=\"pif_rpf_l2_uc_en_i[0]\"\n+ */\n+\n+/* register address for bitfield l2_uc_en{f} */\n+#define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8)\n+/* bitmask for bitfield l2_uc_en{f} */\n+#define HW_ATL_RPFL2UC_ENF_MSK 0x80000000\n+/* inverted bitmask for bitfield l2_uc_en{f} */\n+#define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff\n+/* lower bit position of bitfield l2_uc_en{f} */\n+#define HW_ATL_RPFL2UC_ENF_SHIFT 31\n+/* width of bitfield l2_uc_en{f} */\n+#define HW_ATL_RPFL2UC_ENF_WIDTH 1\n+/* default value of bitfield l2_uc_en{f} */\n+#define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0\n+\n+/* register address for bitfield l2_uc_da{f}_lsw[1f:0] */\n+#define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8)\n+/* register address for bitfield l2_uc_da{f}_msw[f:0] */\n+#define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8)\n+/* bitmask for bitfield l2_uc_da{f}_msw[f:0] */\n+#define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff\n+/* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */\n+#define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0\n+\n+/* rx l2_mc_accept_all bitfield definitions\n+ * Preprocessor definitions for the bitfield \"l2_mc_accept_all\".\n+ * PORT=\"pif_rpf_l2_mc_all_accept_i\"\n+ */\n+\n+/* Register address for bitfield l2_mc_accept_all */\n+#define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270\n+/* Bitmask for bitfield l2_mc_accept_all */\n+#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000\n+/* Inverted bitmask for bitfield l2_mc_accept_all */\n+#define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF\n+/* Lower bit position of bitfield l2_mc_accept_all */\n+#define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14\n+/* Width of bitfield l2_mc_accept_all */\n+#define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1\n+/* Default value of bitfield l2_mc_accept_all */\n+#define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0\n+\n+/* width of bitfield rx_tc_up{t}[2:0] */\n+#define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3\n+/* default value of bitfield rx_tc_up{t}[2:0] */\n+#define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0\n+\n+/* rx rss_key_addr[4:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rss_key_addr[4:0]\".\n+ * port=\"pif_rpf_rss_key_addr_i[4:0]\"\n+ */\n+\n+/* register address for bitfield rss_key_addr[4:0] */\n+#define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0\n+/* bitmask for bitfield rss_key_addr[4:0] */\n+#define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f\n+/* inverted bitmask for bitfield rss_key_addr[4:0] */\n+#define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0\n+/* lower bit position of bitfield rss_key_addr[4:0] */\n+#define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0\n+/* width of bitfield rss_key_addr[4:0] */\n+#define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5\n+/* default value of bitfield rss_key_addr[4:0] */\n+#define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0\n+\n+/* rx rss_key_wr_data[1f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rss_key_wr_data[1f:0]\".\n+ * port=\"pif_rpf_rss_key_wr_data_i[31:0]\"\n+ */\n+\n+/* register address for bitfield rss_key_wr_data[1f:0] */\n+#define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4\n+/* bitmask for bitfield rss_key_wr_data[1f:0] */\n+#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff\n+/* inverted bitmask for bitfield rss_key_wr_data[1f:0] */\n+#define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000\n+/* lower bit position of bitfield rss_key_wr_data[1f:0] */\n+#define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0\n+/* width of bitfield rss_key_wr_data[1f:0] */\n+#define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32\n+/* default value of bitfield rss_key_wr_data[1f:0] */\n+#define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0\n+\n+/* rx rss_key_wr_en_i bitfield definitions\n+ * preprocessor definitions for the bitfield \"rss_key_wr_en_i\".\n+ * port=\"pif_rpf_rss_key_wr_en_i\"\n+ */\n+\n+/* register address for bitfield rss_key_wr_en_i */\n+#define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0\n+/* bitmask for bitfield rss_key_wr_en_i */\n+#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020\n+/* inverted bitmask for bitfield rss_key_wr_en_i */\n+#define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf\n+/* lower bit position of bitfield rss_key_wr_en_i */\n+#define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5\n+/* width of bitfield rss_key_wr_en_i */\n+#define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1\n+/* default value of bitfield rss_key_wr_en_i */\n+#define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0\n+\n+/* rx rss_redir_addr[3:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rss_redir_addr[3:0]\".\n+ * port=\"pif_rpf_rss_redir_addr_i[3:0]\"\n+ */\n+\n+/* register address for bitfield rss_redir_addr[3:0] */\n+#define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0\n+/* bitmask for bitfield rss_redir_addr[3:0] */\n+#define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f\n+/* inverted bitmask for bitfield rss_redir_addr[3:0] */\n+#define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0\n+/* lower bit position of bitfield rss_redir_addr[3:0] */\n+#define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0\n+/* width of bitfield rss_redir_addr[3:0] */\n+#define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4\n+/* default value of bitfield rss_redir_addr[3:0] */\n+#define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0\n+\n+/* rx rss_redir_wr_data[f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"rss_redir_wr_data[f:0]\".\n+ * port=\"pif_rpf_rss_redir_wr_data_i[15:0]\"\n+ */\n+\n+/* register address for bitfield rss_redir_wr_data[f:0] */\n+#define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4\n+/* bitmask for bitfield rss_redir_wr_data[f:0] */\n+#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff\n+/* inverted bitmask for bitfield rss_redir_wr_data[f:0] */\n+#define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000\n+/* lower bit position of bitfield rss_redir_wr_data[f:0] */\n+#define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0\n+/* width of bitfield rss_redir_wr_data[f:0] */\n+#define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16\n+/* default value of bitfield rss_redir_wr_data[f:0] */\n+#define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0\n+\n+/* rx rss_redir_wr_en_i bitfield definitions\n+ * preprocessor definitions for the bitfield \"rss_redir_wr_en_i\".\n+ * port=\"pif_rpf_rss_redir_wr_en_i\"\n+ */\n+\n+/* register address for bitfield rss_redir_wr_en_i */\n+#define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0\n+/* bitmask for bitfield rss_redir_wr_en_i */\n+#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010\n+/* inverted bitmask for bitfield rss_redir_wr_en_i */\n+#define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef\n+/* lower bit position of bitfield rss_redir_wr_en_i */\n+#define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4\n+/* width of bitfield rss_redir_wr_en_i */\n+#define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1\n+/* default value of bitfield rss_redir_wr_en_i */\n+#define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0\n+\n+/* rx tpo_rpf_sys_loopback bitfield definitions\n+ * preprocessor definitions for the bitfield \"tpo_rpf_sys_loopback\".\n+ * port=\"pif_rpf_tpo_pkt_sys_lbk_i\"\n+ */\n+\n+/* register address for bitfield tpo_rpf_sys_loopback */\n+#define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000\n+/* bitmask for bitfield tpo_rpf_sys_loopback */\n+#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100\n+/* inverted bitmask for bitfield tpo_rpf_sys_loopback */\n+#define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff\n+/* lower bit position of bitfield tpo_rpf_sys_loopback */\n+#define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8\n+/* width of bitfield tpo_rpf_sys_loopback */\n+#define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1\n+/* default value of bitfield tpo_rpf_sys_loopback */\n+#define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0\n+\n+/* rx vl_inner_tpid[f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"vl_inner_tpid[f:0]\".\n+ * port=\"pif_rpf_vl_inner_tpid_i[15:0]\"\n+ */\n+\n+/* register address for bitfield vl_inner_tpid[f:0] */\n+#define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284\n+/* bitmask for bitfield vl_inner_tpid[f:0] */\n+#define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff\n+/* inverted bitmask for bitfield vl_inner_tpid[f:0] */\n+#define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000\n+/* lower bit position of bitfield vl_inner_tpid[f:0] */\n+#define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0\n+/* width of bitfield vl_inner_tpid[f:0] */\n+#define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16\n+/* default value of bitfield vl_inner_tpid[f:0] */\n+#define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100\n+\n+/* rx vl_outer_tpid[f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"vl_outer_tpid[f:0]\".\n+ * port=\"pif_rpf_vl_outer_tpid_i[15:0]\"\n+ */\n+\n+/* register address for bitfield vl_outer_tpid[f:0] */\n+#define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284\n+/* bitmask for bitfield vl_outer_tpid[f:0] */\n+#define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000\n+/* inverted bitmask for bitfield vl_outer_tpid[f:0] */\n+#define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff\n+/* lower bit position of bitfield vl_outer_tpid[f:0] */\n+#define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16\n+/* width of bitfield vl_outer_tpid[f:0] */\n+#define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16\n+/* default value of bitfield vl_outer_tpid[f:0] */\n+#define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8\n+\n+/* rx vl_promis_mode bitfield definitions\n+ * preprocessor definitions for the bitfield \"vl_promis_mode\".\n+ * port=\"pif_rpf_vl_promis_mode_i\"\n+ */\n+\n+/* register address for bitfield vl_promis_mode */\n+#define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280\n+/* bitmask for bitfield vl_promis_mode */\n+#define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002\n+/* inverted bitmask for bitfield vl_promis_mode */\n+#define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd\n+/* lower bit position of bitfield vl_promis_mode */\n+#define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1\n+/* width of bitfield vl_promis_mode */\n+#define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1\n+/* default value of bitfield vl_promis_mode */\n+#define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0\n+\n+/* RX vl_accept_untagged_mode Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"vl_accept_untagged_mode\".\n+ * PORT=\"pif_rpf_vl_accept_untagged_i\"\n+ */\n+\n+/* Register address for bitfield vl_accept_untagged_mode */\n+#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280\n+/* Bitmask for bitfield vl_accept_untagged_mode */\n+#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004\n+/* Inverted bitmask for bitfield vl_accept_untagged_mode */\n+#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB\n+/* Lower bit position of bitfield vl_accept_untagged_mode */\n+#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2\n+/* Width of bitfield vl_accept_untagged_mode */\n+#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1\n+/* Default value of bitfield vl_accept_untagged_mode */\n+#define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0\n+\n+/* rX vl_untagged_act[2:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"vl_untagged_act[2:0]\".\n+ * PORT=\"pif_rpf_vl_untagged_act_i[2:0]\"\n+ */\n+\n+/* Register address for bitfield vl_untagged_act[2:0] */\n+#define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280\n+/* Bitmask for bitfield vl_untagged_act[2:0] */\n+#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038\n+/* Inverted bitmask for bitfield vl_untagged_act[2:0] */\n+#define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7\n+/* Lower bit position of bitfield vl_untagged_act[2:0] */\n+#define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3\n+/* Width of bitfield vl_untagged_act[2:0] */\n+#define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3\n+/* Default value of bitfield vl_untagged_act[2:0] */\n+#define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0\n+\n+/* RX vl_en{F} Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"vl_en{F}\".\n+ * Parameter: filter {F} | stride size 0x4 | range [0, 15]\n+ * PORT=\"pif_rpf_vl_en_i[0]\"\n+ */\n+\n+/* Register address for bitfield vl_en{F} */\n+#define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)\n+/* Bitmask for bitfield vl_en{F} */\n+#define HW_ATL_RPF_VL_EN_F_MSK 0x80000000\n+/* Inverted bitmask for bitfield vl_en{F} */\n+#define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF\n+/* Lower bit position of bitfield vl_en{F} */\n+#define HW_ATL_RPF_VL_EN_F_SHIFT 31\n+/* Width of bitfield vl_en{F} */\n+#define HW_ATL_RPF_VL_EN_F_WIDTH 1\n+/* Default value of bitfield vl_en{F} */\n+#define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0\n+\n+/* RX vl_act{F}[2:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"vl_act{F}[2:0]\".\n+ * Parameter: filter {F} | stride size 0x4 | range [0, 15]\n+ * PORT=\"pif_rpf_vl_act0_i[2:0]\"\n+ */\n+\n+/* Register address for bitfield vl_act{F}[2:0] */\n+#define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4)\n+/* Bitmask for bitfield vl_act{F}[2:0] */\n+#define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000\n+/* Inverted bitmask for bitfield vl_act{F}[2:0] */\n+#define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF\n+/* Lower bit position of bitfield vl_act{F}[2:0] */\n+#define HW_ATL_RPF_VL_ACT_F_SHIFT 16\n+/* Width of bitfield vl_act{F}[2:0] */\n+#define HW_ATL_RPF_VL_ACT_F_WIDTH 3\n+/* Default value of bitfield vl_act{F}[2:0] */\n+#define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0\n+\n+/* RX vl_id{F}[B:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"vl_id{F}[B:0]\".\n+ * Parameter: filter {F} | stride size 0x4 | range [0, 15]\n+ * PORT=\"pif_rpf_vl_id0_i[11:0]\"\n+ */\n+\n+/* Register address for bitfield vl_id{F}[B:0] */\n+#define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4)\n+/* Bitmask for bitfield vl_id{F}[B:0] */\n+#define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF\n+/* Inverted bitmask for bitfield vl_id{F}[B:0] */\n+#define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000\n+/* Lower bit position of bitfield vl_id{F}[B:0] */\n+#define HW_ATL_RPF_VL_ID_F_SHIFT 0\n+/* Width of bitfield vl_id{F}[B:0] */\n+#define HW_ATL_RPF_VL_ID_F_WIDTH 12\n+/* Default value of bitfield vl_id{F}[B:0] */\n+#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0\n+\n+/* RX et_en{F} Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"et_en{F}\".\n+ * Parameter: filter {F} | stride size 0x4 | range [0, 15]\n+ * PORT=\"pif_rpf_et_en_i[0]\"\n+ */\n+\n+/* Register address for bitfield et_en{F} */\n+#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* Bitmask for bitfield et_en{F} */\n+#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000\n+/* Inverted bitmask for bitfield et_en{F} */\n+#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF\n+/* Lower bit position of bitfield et_en{F} */\n+#define HW_ATL_RPF_ET_EN_F_SHIFT 31\n+/* Width of bitfield et_en{F} */\n+#define HW_ATL_RPF_ET_EN_F_WIDTH 1\n+/* Default value of bitfield et_en{F} */\n+#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0\n+\n+/* rx et_en{f} bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_en{f}\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_en_i[0]\"\n+ */\n+\n+/* register address for bitfield et_en{f} */\n+#define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_en{f} */\n+#define HW_ATL_RPF_ET_ENF_MSK 0x80000000\n+/* inverted bitmask for bitfield et_en{f} */\n+#define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff\n+/* lower bit position of bitfield et_en{f} */\n+#define HW_ATL_RPF_ET_ENF_SHIFT 31\n+/* width of bitfield et_en{f} */\n+#define HW_ATL_RPF_ET_ENF_WIDTH 1\n+/* default value of bitfield et_en{f} */\n+#define HW_ATL_RPF_ET_ENF_DEFAULT 0x0\n+\n+/* rx et_up{f}_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_up{f}_en\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_up_en_i[0]\"\n+ */\n+\n+/* register address for bitfield et_up{f}_en */\n+#define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_up{f}_en */\n+#define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000\n+/* inverted bitmask for bitfield et_up{f}_en */\n+#define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff\n+/* lower bit position of bitfield et_up{f}_en */\n+#define HW_ATL_RPF_ET_UPFEN_SHIFT 30\n+/* width of bitfield et_up{f}_en */\n+#define HW_ATL_RPF_ET_UPFEN_WIDTH 1\n+/* default value of bitfield et_up{f}_en */\n+#define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0\n+\n+/* rx et_rxq{f}_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_rxq{f}_en\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_rxq_en_i[0]\"\n+ */\n+\n+/* register address for bitfield et_rxq{f}_en */\n+#define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_rxq{f}_en */\n+#define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000\n+/* inverted bitmask for bitfield et_rxq{f}_en */\n+#define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff\n+/* lower bit position of bitfield et_rxq{f}_en */\n+#define HW_ATL_RPF_ET_RXQFEN_SHIFT 29\n+/* width of bitfield et_rxq{f}_en */\n+#define HW_ATL_RPF_ET_RXQFEN_WIDTH 1\n+/* default value of bitfield et_rxq{f}_en */\n+#define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0\n+\n+/* rx et_up{f}[2:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_up{f}[2:0]\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_up0_i[2:0]\"\n+ */\n+\n+/* register address for bitfield et_up{f}[2:0] */\n+#define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_up{f}[2:0] */\n+#define HW_ATL_RPF_ET_UPF_MSK 0x1c000000\n+/* inverted bitmask for bitfield et_up{f}[2:0] */\n+#define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff\n+/* lower bit position of bitfield et_up{f}[2:0] */\n+#define HW_ATL_RPF_ET_UPF_SHIFT 26\n+/* width of bitfield et_up{f}[2:0] */\n+#define HW_ATL_RPF_ET_UPF_WIDTH 3\n+/* default value of bitfield et_up{f}[2:0] */\n+#define HW_ATL_RPF_ET_UPF_DEFAULT 0x0\n+\n+/* rx et_rxq{f}[4:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_rxq{f}[4:0]\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_rxq0_i[4:0]\"\n+ */\n+\n+/* register address for bitfield et_rxq{f}[4:0] */\n+#define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_rxq{f}[4:0] */\n+#define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000\n+/* inverted bitmask for bitfield et_rxq{f}[4:0] */\n+#define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff\n+/* lower bit position of bitfield et_rxq{f}[4:0] */\n+#define HW_ATL_RPF_ET_RXQF_SHIFT 20\n+/* width of bitfield et_rxq{f}[4:0] */\n+#define HW_ATL_RPF_ET_RXQF_WIDTH 5\n+/* default value of bitfield et_rxq{f}[4:0] */\n+#define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0\n+\n+/* rx et_mng_rxq{f} bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_mng_rxq{f}\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_mng_rxq_i[0]\"\n+ */\n+\n+/* register address for bitfield et_mng_rxq{f} */\n+#define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_mng_rxq{f} */\n+#define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000\n+/* inverted bitmask for bitfield et_mng_rxq{f} */\n+#define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff\n+/* lower bit position of bitfield et_mng_rxq{f} */\n+#define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19\n+/* width of bitfield et_mng_rxq{f} */\n+#define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1\n+/* default value of bitfield et_mng_rxq{f} */\n+#define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0\n+\n+/* rx et_act{f}[2:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_act{f}[2:0]\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_act0_i[2:0]\"\n+ */\n+\n+/* register address for bitfield et_act{f}[2:0] */\n+#define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_act{f}[2:0] */\n+#define HW_ATL_RPF_ET_ACTF_MSK 0x00070000\n+/* inverted bitmask for bitfield et_act{f}[2:0] */\n+#define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff\n+/* lower bit position of bitfield et_act{f}[2:0] */\n+#define HW_ATL_RPF_ET_ACTF_SHIFT 16\n+/* width of bitfield et_act{f}[2:0] */\n+#define HW_ATL_RPF_ET_ACTF_WIDTH 3\n+/* default value of bitfield et_act{f}[2:0] */\n+#define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0\n+\n+/* rx et_val{f}[f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"et_val{f}[f:0]\".\n+ * parameter: filter {f} | stride size 0x4 | range [0, 15]\n+ * port=\"pif_rpf_et_val0_i[15:0]\"\n+ */\n+\n+/* register address for bitfield et_val{f}[f:0] */\n+#define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4)\n+/* bitmask for bitfield et_val{f}[f:0] */\n+#define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff\n+/* inverted bitmask for bitfield et_val{f}[f:0] */\n+#define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000\n+/* lower bit position of bitfield et_val{f}[f:0] */\n+#define HW_ATL_RPF_ET_VALF_SHIFT 0\n+/* width of bitfield et_val{f}[f:0] */\n+#define HW_ATL_RPF_ET_VALF_WIDTH 16\n+/* default value of bitfield et_val{f}[f:0] */\n+#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0\n+\n+/* rx ipv4_chk_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"ipv4_chk_en\".\n+ * port=\"pif_rpo_ipv4_chk_en_i\"\n+ */\n+\n+/* register address for bitfield ipv4_chk_en */\n+#define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580\n+/* bitmask for bitfield ipv4_chk_en */\n+#define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002\n+/* inverted bitmask for bitfield ipv4_chk_en */\n+#define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd\n+/* lower bit position of bitfield ipv4_chk_en */\n+#define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1\n+/* width of bitfield ipv4_chk_en */\n+#define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1\n+/* default value of bitfield ipv4_chk_en */\n+#define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0\n+\n+/* rx desc{d}_vl_strip bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_vl_strip\".\n+ * parameter: descriptor {d} | stride size 0x20 | range [0, 31]\n+ * port=\"pif_rpo_desc_vl_strip_i[0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_vl_strip */\n+#define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \\\n+\t(0x00005b08 + (descriptor) * 0x20)\n+/* bitmask for bitfield desc{d}_vl_strip */\n+#define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000\n+/* inverted bitmask for bitfield desc{d}_vl_strip */\n+#define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff\n+/* lower bit position of bitfield desc{d}_vl_strip */\n+#define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29\n+/* width of bitfield desc{d}_vl_strip */\n+#define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1\n+/* default value of bitfield desc{d}_vl_strip */\n+#define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0\n+\n+/* rx l4_chk_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"l4_chk_en\".\n+ * port=\"pif_rpo_l4_chk_en_i\"\n+ */\n+\n+/* register address for bitfield l4_chk_en */\n+#define HW_ATL_RPOL4CHK_EN_ADR 0x00005580\n+/* bitmask for bitfield l4_chk_en */\n+#define HW_ATL_RPOL4CHK_EN_MSK 0x00000001\n+/* inverted bitmask for bitfield l4_chk_en */\n+#define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe\n+/* lower bit position of bitfield l4_chk_en */\n+#define HW_ATL_RPOL4CHK_EN_SHIFT 0\n+/* width of bitfield l4_chk_en */\n+#define HW_ATL_RPOL4CHK_EN_WIDTH 1\n+/* default value of bitfield l4_chk_en */\n+#define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0\n+\n+/* rx reg_res_dsbl bitfield definitions\n+ * preprocessor definitions for the bitfield \"reg_res_dsbl\".\n+ * port=\"pif_rx_reg_res_dsbl_i\"\n+ */\n+\n+/* register address for bitfield reg_res_dsbl */\n+#define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000\n+/* bitmask for bitfield reg_res_dsbl */\n+#define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000\n+/* inverted bitmask for bitfield reg_res_dsbl */\n+#define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff\n+/* lower bit position of bitfield reg_res_dsbl */\n+#define HW_ATL_RX_REG_RES_DSBL_SHIFT 29\n+/* width of bitfield reg_res_dsbl */\n+#define HW_ATL_RX_REG_RES_DSBL_WIDTH 1\n+/* default value of bitfield reg_res_dsbl */\n+#define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1\n+\n+/* tx dca{d}_cpuid[7:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca{d}_cpuid[7:0]\".\n+ * parameter: dca {d} | stride size 0x4 | range [0, 31]\n+ * port=\"pif_tdm_dca0_cpuid_i[7:0]\"\n+ */\n+\n+/* register address for bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4)\n+/* bitmask for bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff\n+/* inverted bitmask for bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00\n+/* lower bit position of bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCADCPUID_SHIFT 0\n+/* width of bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCADCPUID_WIDTH 8\n+/* default value of bitfield dca{d}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0\n+\n+/* tx lso_en[1f:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"lso_en[1f:0]\".\n+ * port=\"pif_tdm_lso_en_i[31:0]\"\n+ */\n+\n+/* register address for bitfield lso_en[1f:0] */\n+#define HW_ATL_TDM_LSO_EN_ADR 0x00007810\n+/* bitmask for bitfield lso_en[1f:0] */\n+#define HW_ATL_TDM_LSO_EN_MSK 0xffffffff\n+/* inverted bitmask for bitfield lso_en[1f:0] */\n+#define HW_ATL_TDM_LSO_EN_MSKN 0x00000000\n+/* lower bit position of bitfield lso_en[1f:0] */\n+#define HW_ATL_TDM_LSO_EN_SHIFT 0\n+/* width of bitfield lso_en[1f:0] */\n+#define HW_ATL_TDM_LSO_EN_WIDTH 32\n+/* default value of bitfield lso_en[1f:0] */\n+#define HW_ATL_TDM_LSO_EN_DEFAULT 0x0\n+\n+/* tx dca_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca_en\".\n+ * port=\"pif_tdm_dca_en_i\"\n+ */\n+\n+/* register address for bitfield dca_en */\n+#define HW_ATL_TDM_DCA_EN_ADR 0x00008480\n+/* bitmask for bitfield dca_en */\n+#define HW_ATL_TDM_DCA_EN_MSK 0x80000000\n+/* inverted bitmask for bitfield dca_en */\n+#define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff\n+/* lower bit position of bitfield dca_en */\n+#define HW_ATL_TDM_DCA_EN_SHIFT 31\n+/* width of bitfield dca_en */\n+#define HW_ATL_TDM_DCA_EN_WIDTH 1\n+/* default value of bitfield dca_en */\n+#define HW_ATL_TDM_DCA_EN_DEFAULT 0x1\n+\n+/* tx dca_mode[3:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca_mode[3:0]\".\n+ * port=\"pif_tdm_dca_mode_i[3:0]\"\n+ */\n+\n+/* register address for bitfield dca_mode[3:0] */\n+#define HW_ATL_TDM_DCA_MODE_ADR 0x00008480\n+/* bitmask for bitfield dca_mode[3:0] */\n+#define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f\n+/* inverted bitmask for bitfield dca_mode[3:0] */\n+#define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0\n+/* lower bit position of bitfield dca_mode[3:0] */\n+#define HW_ATL_TDM_DCA_MODE_SHIFT 0\n+/* width of bitfield dca_mode[3:0] */\n+#define HW_ATL_TDM_DCA_MODE_WIDTH 4\n+/* default value of bitfield dca_mode[3:0] */\n+#define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0\n+\n+/* tx dca{d}_desc_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"dca{d}_desc_en\".\n+ * parameter: dca {d} | stride size 0x4 | range [0, 31]\n+ * port=\"pif_tdm_dca_desc_en_i[0]\"\n+ */\n+\n+/* register address for bitfield dca{d}_desc_en */\n+#define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4)\n+/* bitmask for bitfield dca{d}_desc_en */\n+#define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000\n+/* inverted bitmask for bitfield dca{d}_desc_en */\n+#define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff\n+/* lower bit position of bitfield dca{d}_desc_en */\n+#define HW_ATL_TDM_DCADDESC_EN_SHIFT 31\n+/* width of bitfield dca{d}_desc_en */\n+#define HW_ATL_TDM_DCADDESC_EN_WIDTH 1\n+/* default value of bitfield dca{d}_desc_en */\n+#define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0\n+\n+/* tx desc{d}_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_en\".\n+ * parameter: descriptor {d} | stride size 0x40 | range [0, 31]\n+ * port=\"pif_tdm_desc_en_i[0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_en */\n+#define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40)\n+/* bitmask for bitfield desc{d}_en */\n+#define HW_ATL_TDM_DESCDEN_MSK 0x80000000\n+/* inverted bitmask for bitfield desc{d}_en */\n+#define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff\n+/* lower bit position of bitfield desc{d}_en */\n+#define HW_ATL_TDM_DESCDEN_SHIFT 31\n+/* width of bitfield desc{d}_en */\n+#define HW_ATL_TDM_DESCDEN_WIDTH 1\n+/* default value of bitfield desc{d}_en */\n+#define HW_ATL_TDM_DESCDEN_DEFAULT 0x0\n+\n+/* tx desc{d}_hd[c:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_hd[c:0]\".\n+ * parameter: descriptor {d} | stride size 0x40 | range [0, 31]\n+ * port=\"tdm_pif_desc0_hd_o[12:0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40)\n+/* bitmask for bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_TDM_DESCDHD_MSK 0x00001fff\n+/* inverted bitmask for bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000\n+/* lower bit position of bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_TDM_DESCDHD_SHIFT 0\n+/* width of bitfield desc{d}_hd[c:0] */\n+#define HW_ATL_TDM_DESCDHD_WIDTH 13\n+\n+/* tx desc{d}_len[9:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_len[9:0]\".\n+ * parameter: descriptor {d} | stride size 0x40 | range [0, 31]\n+ * port=\"pif_tdm_desc0_len_i[9:0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_len[9:0] */\n+#define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40)\n+/* bitmask for bitfield desc{d}_len[9:0] */\n+#define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8\n+/* inverted bitmask for bitfield desc{d}_len[9:0] */\n+#define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007\n+/* lower bit position of bitfield desc{d}_len[9:0] */\n+#define HW_ATL_TDM_DESCDLEN_SHIFT 3\n+/* width of bitfield desc{d}_len[9:0] */\n+#define HW_ATL_TDM_DESCDLEN_WIDTH 10\n+/* default value of bitfield desc{d}_len[9:0] */\n+#define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0\n+\n+/* tx int_desc_wrb_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"int_desc_wrb_en\".\n+ * port=\"pif_tdm_int_desc_wrb_en_i\"\n+ */\n+\n+/* register address for bitfield int_desc_wrb_en */\n+#define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40\n+/* bitmask for bitfield int_desc_wrb_en */\n+#define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002\n+/* inverted bitmask for bitfield int_desc_wrb_en */\n+#define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd\n+/* lower bit position of bitfield int_desc_wrb_en */\n+#define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1\n+/* width of bitfield int_desc_wrb_en */\n+#define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1\n+/* default value of bitfield int_desc_wrb_en */\n+#define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0\n+\n+/* tx desc{d}_wrb_thresh[6:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc{d}_wrb_thresh[6:0]\".\n+ * parameter: descriptor {d} | stride size 0x40 | range [0, 31]\n+ * port=\"pif_tdm_desc0_wrb_thresh_i[6:0]\"\n+ */\n+\n+/* register address for bitfield desc{d}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \\\n+\t(0x00007c18 + (descriptor) * 0x40)\n+/* bitmask for bitfield desc{d}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00\n+/* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff\n+/* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8\n+/* width of bitfield desc{d}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7\n+/* default value of bitfield desc{d}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0\n+\n+/* tx lso_tcp_flag_first[b:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"lso_tcp_flag_first[b:0]\".\n+ * port=\"pif_thm_lso_tcp_flag_first_i[11:0]\"\n+ */\n+\n+/* register address for bitfield lso_tcp_flag_first[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820\n+/* bitmask for bitfield lso_tcp_flag_first[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff\n+/* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000\n+/* lower bit position of bitfield lso_tcp_flag_first[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0\n+/* width of bitfield lso_tcp_flag_first[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12\n+/* default value of bitfield lso_tcp_flag_first[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0\n+\n+/* tx lso_tcp_flag_last[b:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"lso_tcp_flag_last[b:0]\".\n+ * port=\"pif_thm_lso_tcp_flag_last_i[11:0]\"\n+ */\n+\n+/* register address for bitfield lso_tcp_flag_last[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824\n+/* bitmask for bitfield lso_tcp_flag_last[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff\n+/* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000\n+/* lower bit position of bitfield lso_tcp_flag_last[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0\n+/* width of bitfield lso_tcp_flag_last[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12\n+/* default value of bitfield lso_tcp_flag_last[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0\n+\n+/* tx lso_tcp_flag_mid[b:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"lso_tcp_flag_mid[b:0]\".\n+ * port=\"pif_thm_lso_tcp_flag_mid_i[11:0]\"\n+ */\n+\n+/* Register address for bitfield lro_rsc_max[1F:0] */\n+#define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598\n+/* Bitmask for bitfield lro_rsc_max[1F:0] */\n+#define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF\n+/* Inverted bitmask for bitfield lro_rsc_max[1F:0] */\n+#define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000\n+/* Lower bit position of bitfield lro_rsc_max[1F:0] */\n+#define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0\n+/* Width of bitfield lro_rsc_max[1F:0] */\n+#define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32\n+/* Default value of bitfield lro_rsc_max[1F:0] */\n+#define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0\n+\n+/* RX lro_en[1F:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lro_en[1F:0]\".\n+ * PORT=\"pif_rpo_lro_en_i[31:0]\"\n+ */\n+\n+/* Register address for bitfield lro_en[1F:0] */\n+#define HW_ATL_RPO_LRO_EN_ADR 0x00005590\n+/* Bitmask for bitfield lro_en[1F:0] */\n+#define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF\n+/* Inverted bitmask for bitfield lro_en[1F:0] */\n+#define HW_ATL_RPO_LRO_EN_MSKN 0x00000000\n+/* Lower bit position of bitfield lro_en[1F:0] */\n+#define HW_ATL_RPO_LRO_EN_SHIFT 0\n+/* Width of bitfield lro_en[1F:0] */\n+#define HW_ATL_RPO_LRO_EN_WIDTH 32\n+/* Default value of bitfield lro_en[1F:0] */\n+#define HW_ATL_RPO_LRO_EN_DEFAULT 0x0\n+\n+/* RX lro_ptopt_en Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lro_ptopt_en\".\n+ * PORT=\"pif_rpo_lro_ptopt_en_i\"\n+ */\n+\n+/* Register address for bitfield lro_ptopt_en */\n+#define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594\n+/* Bitmask for bitfield lro_ptopt_en */\n+#define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000\n+/* Inverted bitmask for bitfield lro_ptopt_en */\n+#define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF\n+/* Lower bit position of bitfield lro_ptopt_en */\n+#define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15\n+/* Width of bitfield lro_ptopt_en */\n+#define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1\n+/* Default value of bitfield lro_ptopt_en */\n+#define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1\n+\n+/* RX lro_q_ses_lmt Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lro_q_ses_lmt\".\n+ * PORT=\"pif_rpo_lro_q_ses_lmt_i[1:0]\"\n+ */\n+\n+/* Register address for bitfield lro_q_ses_lmt */\n+#define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594\n+/* Bitmask for bitfield lro_q_ses_lmt */\n+#define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000\n+/* Inverted bitmask for bitfield lro_q_ses_lmt */\n+#define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF\n+/* Lower bit position of bitfield lro_q_ses_lmt */\n+#define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12\n+/* Width of bitfield lro_q_ses_lmt */\n+#define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2\n+/* Default value of bitfield lro_q_ses_lmt */\n+#define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1\n+\n+/* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lro_tot_dsc_lmt[1:0]\".\n+ * PORT=\"pif_rpo_lro_tot_dsc_lmt_i[1:0]\"\n+ */\n+\n+/* Register address for bitfield lro_tot_dsc_lmt[1:0] */\n+#define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594\n+/* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */\n+#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060\n+/* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */\n+#define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F\n+/* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */\n+#define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5\n+/* Width of bitfield lro_tot_dsc_lmt[1:0] */\n+#define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2\n+/* Default value of bitfield lro_tot_dsc_lmt[1:0] */\n+#define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1\n+\n+/* RX lro_pkt_min[4:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lro_pkt_min[4:0]\".\n+ * PORT=\"pif_rpo_lro_pkt_min_i[4:0]\"\n+ */\n+\n+/* Register address for bitfield lro_pkt_min[4:0] */\n+#define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594\n+/* Bitmask for bitfield lro_pkt_min[4:0] */\n+#define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F\n+/* Inverted bitmask for bitfield lro_pkt_min[4:0] */\n+#define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0\n+/* Lower bit position of bitfield lro_pkt_min[4:0] */\n+#define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0\n+/* Width of bitfield lro_pkt_min[4:0] */\n+#define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5\n+/* Default value of bitfield lro_pkt_min[4:0] */\n+#define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8\n+\n+/* Width of bitfield lro{L}_des_max[1:0] */\n+#define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2\n+/* Default value of bitfield lro{L}_des_max[1:0] */\n+#define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0\n+\n+/* RX lro_tb_div[11:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lro_tb_div[11:0]\".\n+ * PORT=\"pif_rpo_lro_tb_div_i[11:0]\"\n+ */\n+\n+/* Register address for bitfield lro_tb_div[11:0] */\n+#define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620\n+/* Bitmask for bitfield lro_tb_div[11:0] */\n+#define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000\n+/* Inverted bitmask for bitfield lro_tb_div[11:0] */\n+#define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF\n+/* Lower bit position of bitfield lro_tb_div[11:0] */\n+#define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20\n+/* Width of bitfield lro_tb_div[11:0] */\n+#define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12\n+/* Default value of bitfield lro_tb_div[11:0] */\n+#define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35\n+\n+/* RX lro_ina_ival[9:0] Bitfield Definitions\n+ *   Preprocessor definitions for the bitfield \"lro_ina_ival[9:0]\".\n+ *   PORT=\"pif_rpo_lro_ina_ival_i[9:0]\"\n+ */\n+\n+/* Register address for bitfield lro_ina_ival[9:0] */\n+#define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620\n+/* Bitmask for bitfield lro_ina_ival[9:0] */\n+#define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00\n+/* Inverted bitmask for bitfield lro_ina_ival[9:0] */\n+#define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF\n+/* Lower bit position of bitfield lro_ina_ival[9:0] */\n+#define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10\n+/* Width of bitfield lro_ina_ival[9:0] */\n+#define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10\n+/* Default value of bitfield lro_ina_ival[9:0] */\n+#define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA\n+\n+/* RX lro_max_ival[9:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lro_max_ival[9:0]\".\n+ * PORT=\"pif_rpo_lro_max_ival_i[9:0]\"\n+ */\n+\n+/* Register address for bitfield lro_max_ival[9:0] */\n+#define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620\n+/* Bitmask for bitfield lro_max_ival[9:0] */\n+#define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF\n+/* Inverted bitmask for bitfield lro_max_ival[9:0] */\n+#define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00\n+/* Lower bit position of bitfield lro_max_ival[9:0] */\n+#define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0\n+/* Width of bitfield lro_max_ival[9:0] */\n+#define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10\n+/* Default value of bitfield lro_max_ival[9:0] */\n+#define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19\n+\n+/* TX dca{D}_cpuid[7:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"dca{D}_cpuid[7:0]\".\n+ * Parameter: DCA {D} | stride size 0x4 | range [0, 31]\n+ * PORT=\"pif_tdm_dca0_cpuid_i[7:0]\"\n+ */\n+\n+/* Register address for bitfield dca{D}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4)\n+/* Bitmask for bitfield dca{D}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF\n+/* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00\n+/* Lower bit position of bitfield dca{D}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCA_DCPUID_SHIFT 0\n+/* Width of bitfield dca{D}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCA_DCPUID_WIDTH 8\n+/* Default value of bitfield dca{D}_cpuid[7:0] */\n+#define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0\n+\n+/* TX dca{D}_desc_en Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"dca{D}_desc_en\".\n+ * Parameter: DCA {D} | stride size 0x4 | range [0, 31]\n+ * PORT=\"pif_tdm_dca_desc_en_i[0]\"\n+ */\n+\n+/* Register address for bitfield dca{D}_desc_en */\n+#define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4)\n+/* Bitmask for bitfield dca{D}_desc_en */\n+#define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000\n+/* Inverted bitmask for bitfield dca{D}_desc_en */\n+#define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF\n+/* Lower bit position of bitfield dca{D}_desc_en */\n+#define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31\n+/* Width of bitfield dca{D}_desc_en */\n+#define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1\n+/* Default value of bitfield dca{D}_desc_en */\n+#define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0\n+\n+/* TX desc{D}_en Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"desc{D}_en\".\n+ * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]\n+ * PORT=\"pif_tdm_desc_en_i[0]\"\n+ */\n+\n+/* Register address for bitfield desc{D}_en */\n+#define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40)\n+/* Bitmask for bitfield desc{D}_en */\n+#define HW_ATL_TDM_DESC_DEN_MSK 0x80000000\n+/* Inverted bitmask for bitfield desc{D}_en */\n+#define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF\n+/* Lower bit position of bitfield desc{D}_en */\n+#define HW_ATL_TDM_DESC_DEN_SHIFT 31\n+/* Width of bitfield desc{D}_en */\n+#define HW_ATL_TDM_DESC_DEN_WIDTH 1\n+/* Default value of bitfield desc{D}_en */\n+#define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0\n+\n+/* TX desc{D}_hd[C:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"desc{D}_hd[C:0]\".\n+ * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]\n+ * PORT=\"tdm_pif_desc0_hd_o[12:0]\"\n+ */\n+\n+/* Register address for bitfield desc{D}_hd[C:0] */\n+#define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40)\n+/* Bitmask for bitfield desc{D}_hd[C:0] */\n+#define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF\n+/* Inverted bitmask for bitfield desc{D}_hd[C:0] */\n+#define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000\n+/* Lower bit position of bitfield desc{D}_hd[C:0] */\n+#define HW_ATL_TDM_DESC_DHD_SHIFT 0\n+/* Width of bitfield desc{D}_hd[C:0] */\n+#define HW_ATL_TDM_DESC_DHD_WIDTH 13\n+\n+/* TX desc{D}_len[9:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"desc{D}_len[9:0]\".\n+ * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]\n+ * PORT=\"pif_tdm_desc0_len_i[9:0]\"\n+ */\n+\n+/* Register address for bitfield desc{D}_len[9:0] */\n+#define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40)\n+/* Bitmask for bitfield desc{D}_len[9:0] */\n+#define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8\n+/* Inverted bitmask for bitfield desc{D}_len[9:0] */\n+#define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007\n+/* Lower bit position of bitfield desc{D}_len[9:0] */\n+#define HW_ATL_TDM_DESC_DLEN_SHIFT 3\n+/* Width of bitfield desc{D}_len[9:0] */\n+#define HW_ATL_TDM_DESC_DLEN_WIDTH 10\n+/* Default value of bitfield desc{D}_len[9:0] */\n+#define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0\n+\n+/* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"desc{D}_wrb_thresh[6:0]\".\n+ * Parameter: descriptor {D} | stride size 0x40 | range [0, 31]\n+ * PORT=\"pif_tdm_desc0_wrb_thresh_i[6:0]\"\n+ */\n+\n+/* Register address for bitfield desc{D}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \\\n+\t(0x00007C18 + (descriptor) * 0x40)\n+/* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00\n+/* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF\n+/* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8\n+/* Width of bitfield desc{D}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7\n+/* Default value of bitfield desc{D}_wrb_thresh[6:0] */\n+#define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0\n+\n+/* TX tdm_int_mod_en Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"tdm_int_mod_en\".\n+ * PORT=\"pif_tdm_int_mod_en_i\"\n+ */\n+\n+/* Register address for bitfield tdm_int_mod_en */\n+#define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40\n+/* Bitmask for bitfield tdm_int_mod_en */\n+#define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010\n+/* Inverted bitmask for bitfield tdm_int_mod_en */\n+#define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF\n+/* Lower bit position of bitfield tdm_int_mod_en */\n+#define HW_ATL_TDM_INT_MOD_EN_SHIFT 4\n+/* Width of bitfield tdm_int_mod_en */\n+#define HW_ATL_TDM_INT_MOD_EN_WIDTH 1\n+/* Default value of bitfield tdm_int_mod_en */\n+#define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0\n+\n+/* TX lso_tcp_flag_mid[B:0] Bitfield Definitions\n+ * Preprocessor definitions for the bitfield \"lso_tcp_flag_mid[B:0]\".\n+ * PORT=\"pif_thm_lso_tcp_flag_mid_i[11:0]\"\n+ */\n+/* register address for bitfield lso_tcp_flag_mid[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820\n+/* bitmask for bitfield lso_tcp_flag_mid[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000\n+/* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff\n+/* lower bit position of bitfield lso_tcp_flag_mid[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16\n+/* width of bitfield lso_tcp_flag_mid[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12\n+/* default value of bitfield lso_tcp_flag_mid[b:0] */\n+#define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0\n+\n+/* tx tx_buf_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"tx_buf_en\".\n+ * port=\"pif_tpb_tx_buf_en_i\"\n+ */\n+\n+/* register address for bitfield tx_buf_en */\n+#define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900\n+/* bitmask for bitfield tx_buf_en */\n+#define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001\n+/* inverted bitmask for bitfield tx_buf_en */\n+#define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe\n+/* lower bit position of bitfield tx_buf_en */\n+#define HW_ATL_TPB_TX_BUF_EN_SHIFT 0\n+/* width of bitfield tx_buf_en */\n+#define HW_ATL_TPB_TX_BUF_EN_WIDTH 1\n+/* default value of bitfield tx_buf_en */\n+#define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0\n+\n+/* register address for bitfield tx_tc_mode */\n+#define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900\n+/* bitmask for bitfield tx_tc_mode */\n+#define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100\n+/* inverted bitmask for bitfield tx_tc_mode */\n+#define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF\n+/* lower bit position of bitfield tx_tc_mode */\n+#define HW_ATL_TPB_TX_TC_MODE_SHIFT 8\n+/* width of bitfield tx_tc_mode */\n+#define HW_ATL_TPB_TX_TC_MODE_WIDTH 1\n+/* default value of bitfield tx_tc_mode */\n+#define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0\n+\n+/* tx tx{b}_hi_thresh[c:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"tx{b}_hi_thresh[c:0]\".\n+ * parameter: buffer {b} | stride size 0x10 | range [0, 7]\n+ * port=\"pif_tpb_tx0_hi_thresh_i[12:0]\"\n+ */\n+\n+/* register address for bitfield tx{b}_hi_thresh[c:0] */\n+#define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10)\n+/* bitmask for bitfield tx{b}_hi_thresh[c:0] */\n+#define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000\n+/* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */\n+#define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff\n+/* lower bit position of bitfield tx{b}_hi_thresh[c:0] */\n+#define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16\n+/* width of bitfield tx{b}_hi_thresh[c:0] */\n+#define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13\n+/* default value of bitfield tx{b}_hi_thresh[c:0] */\n+#define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0\n+\n+/* tx tx{b}_lo_thresh[c:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"tx{b}_lo_thresh[c:0]\".\n+ * parameter: buffer {b} | stride size 0x10 | range [0, 7]\n+ * port=\"pif_tpb_tx0_lo_thresh_i[12:0]\"\n+ */\n+\n+/* register address for bitfield tx{b}_lo_thresh[c:0] */\n+#define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10)\n+/* bitmask for bitfield tx{b}_lo_thresh[c:0] */\n+#define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff\n+/* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */\n+#define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000\n+/* lower bit position of bitfield tx{b}_lo_thresh[c:0] */\n+#define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0\n+/* width of bitfield tx{b}_lo_thresh[c:0] */\n+#define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13\n+/* default value of bitfield tx{b}_lo_thresh[c:0] */\n+#define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0\n+\n+/* tx dma_sys_loopback bitfield definitions\n+ * preprocessor definitions for the bitfield \"dma_sys_loopback\".\n+ * port=\"pif_tpb_dma_sys_lbk_i\"\n+ */\n+\n+/* register address for bitfield dma_sys_loopback */\n+#define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000\n+/* bitmask for bitfield dma_sys_loopback */\n+#define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040\n+/* inverted bitmask for bitfield dma_sys_loopback */\n+#define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf\n+/* lower bit position of bitfield dma_sys_loopback */\n+#define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6\n+/* width of bitfield dma_sys_loopback */\n+#define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1\n+/* default value of bitfield dma_sys_loopback */\n+#define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0\n+\n+/* tx tx{b}_buf_size[7:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"tx{b}_buf_size[7:0]\".\n+ * parameter: buffer {b} | stride size 0x10 | range [0, 7]\n+ * port=\"pif_tpb_tx0_buf_size_i[7:0]\"\n+ */\n+\n+/* register address for bitfield tx{b}_buf_size[7:0] */\n+#define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10)\n+/* bitmask for bitfield tx{b}_buf_size[7:0] */\n+#define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff\n+/* inverted bitmask for bitfield tx{b}_buf_size[7:0] */\n+#define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00\n+/* lower bit position of bitfield tx{b}_buf_size[7:0] */\n+#define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0\n+/* width of bitfield tx{b}_buf_size[7:0] */\n+#define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8\n+/* default value of bitfield tx{b}_buf_size[7:0] */\n+#define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0\n+\n+/* tx tx_scp_ins_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"tx_scp_ins_en\".\n+ * port=\"pif_tpb_scp_ins_en_i\"\n+ */\n+\n+/* register address for bitfield tx_scp_ins_en */\n+#define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900\n+/* bitmask for bitfield tx_scp_ins_en */\n+#define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004\n+/* inverted bitmask for bitfield tx_scp_ins_en */\n+#define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb\n+/* lower bit position of bitfield tx_scp_ins_en */\n+#define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2\n+/* width of bitfield tx_scp_ins_en */\n+#define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1\n+/* default value of bitfield tx_scp_ins_en */\n+#define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0\n+\n+/* tx ipv4_chk_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"ipv4_chk_en\".\n+ * port=\"pif_tpo_ipv4_chk_en_i\"\n+ */\n+\n+/* register address for bitfield ipv4_chk_en */\n+#define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800\n+/* bitmask for bitfield ipv4_chk_en */\n+#define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002\n+/* inverted bitmask for bitfield ipv4_chk_en */\n+#define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd\n+/* lower bit position of bitfield ipv4_chk_en */\n+#define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1\n+/* width of bitfield ipv4_chk_en */\n+#define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1\n+/* default value of bitfield ipv4_chk_en */\n+#define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0\n+\n+/* tx l4_chk_en bitfield definitions\n+ * preprocessor definitions for the bitfield \"l4_chk_en\".\n+ * port=\"pif_tpo_l4_chk_en_i\"\n+ */\n+\n+/* register address for bitfield l4_chk_en */\n+#define HW_ATL_TPOL4CHK_EN_ADR 0x00007800\n+/* bitmask for bitfield l4_chk_en */\n+#define HW_ATL_TPOL4CHK_EN_MSK 0x00000001\n+/* inverted bitmask for bitfield l4_chk_en */\n+#define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe\n+/* lower bit position of bitfield l4_chk_en */\n+#define HW_ATL_TPOL4CHK_EN_SHIFT 0\n+/* width of bitfield l4_chk_en */\n+#define HW_ATL_TPOL4CHK_EN_WIDTH 1\n+/* default value of bitfield l4_chk_en */\n+#define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0\n+\n+/* tx pkt_sys_loopback bitfield definitions\n+ * preprocessor definitions for the bitfield \"pkt_sys_loopback\".\n+ * port=\"pif_tpo_pkt_sys_lbk_i\"\n+ */\n+\n+/* register address for bitfield pkt_sys_loopback */\n+#define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000\n+/* bitmask for bitfield pkt_sys_loopback */\n+#define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080\n+/* inverted bitmask for bitfield pkt_sys_loopback */\n+#define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f\n+/* lower bit position of bitfield pkt_sys_loopback */\n+#define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7\n+/* width of bitfield pkt_sys_loopback */\n+#define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1\n+/* default value of bitfield pkt_sys_loopback */\n+#define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0\n+\n+/* tx data_tc_arb_mode bitfield definitions\n+ * preprocessor definitions for the bitfield \"data_tc_arb_mode\".\n+ * port=\"pif_tps_data_tc_arb_mode_i\"\n+ */\n+\n+/* register address for bitfield data_tc_arb_mode */\n+#define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100\n+/* bitmask for bitfield data_tc_arb_mode */\n+#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001\n+/* inverted bitmask for bitfield data_tc_arb_mode */\n+#define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe\n+/* lower bit position of bitfield data_tc_arb_mode */\n+#define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0\n+/* width of bitfield data_tc_arb_mode */\n+#define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1\n+/* default value of bitfield data_tc_arb_mode */\n+#define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0\n+\n+/* tx desc_rate_ta_rst bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc_rate_ta_rst\".\n+ * port=\"pif_tps_desc_rate_ta_rst_i\"\n+ */\n+\n+/* register address for bitfield desc_rate_ta_rst */\n+#define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310\n+/* bitmask for bitfield desc_rate_ta_rst */\n+#define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000\n+/* inverted bitmask for bitfield desc_rate_ta_rst */\n+#define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff\n+/* lower bit position of bitfield desc_rate_ta_rst */\n+#define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31\n+/* width of bitfield desc_rate_ta_rst */\n+#define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1\n+/* default value of bitfield desc_rate_ta_rst */\n+#define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0\n+\n+/* tx desc_rate_limit[a:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc_rate_limit[a:0]\".\n+ * port=\"pif_tps_desc_rate_lim_i[10:0]\"\n+ */\n+\n+/* register address for bitfield desc_rate_limit[a:0] */\n+#define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310\n+/* bitmask for bitfield desc_rate_limit[a:0] */\n+#define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff\n+/* inverted bitmask for bitfield desc_rate_limit[a:0] */\n+#define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800\n+/* lower bit position of bitfield desc_rate_limit[a:0] */\n+#define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0\n+/* width of bitfield desc_rate_limit[a:0] */\n+#define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11\n+/* default value of bitfield desc_rate_limit[a:0] */\n+#define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0\n+\n+/* tx desc_tc_arb_mode[1:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc_tc_arb_mode[1:0]\".\n+ * port=\"pif_tps_desc_tc_arb_mode_i[1:0]\"\n+ */\n+\n+/* register address for bitfield desc_tc_arb_mode[1:0] */\n+#define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200\n+/* bitmask for bitfield desc_tc_arb_mode[1:0] */\n+#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003\n+/* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */\n+#define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc\n+/* lower bit position of bitfield desc_tc_arb_mode[1:0] */\n+#define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0\n+/* width of bitfield desc_tc_arb_mode[1:0] */\n+#define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2\n+/* default value of bitfield desc_tc_arb_mode[1:0] */\n+#define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0\n+\n+/* tx desc_tc{t}_credit_max[b:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc_tc{t}_credit_max[b:0]\".\n+ * parameter: tc {t} | stride size 0x4 | range [0, 7]\n+ * port=\"pif_tps_desc_tc0_credit_max_i[11:0]\"\n+ */\n+\n+/* register address for bitfield desc_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4)\n+/* bitmask for bitfield desc_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000\n+/* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff\n+/* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16\n+/* width of bitfield desc_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12\n+/* default value of bitfield desc_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0\n+\n+/* tx desc_tc{t}_weight[8:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc_tc{t}_weight[8:0]\".\n+ * parameter: tc {t} | stride size 0x4 | range [0, 7]\n+ * port=\"pif_tps_desc_tc0_weight_i[8:0]\"\n+ */\n+\n+/* register address for bitfield desc_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4)\n+/* bitmask for bitfield desc_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff\n+/* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00\n+/* lower bit position of bitfield desc_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0\n+/* width of bitfield desc_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9\n+/* default value of bitfield desc_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0\n+\n+/* tx desc_vm_arb_mode bitfield definitions\n+ * preprocessor definitions for the bitfield \"desc_vm_arb_mode\".\n+ * port=\"pif_tps_desc_vm_arb_mode_i\"\n+ */\n+\n+/* register address for bitfield desc_vm_arb_mode */\n+#define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300\n+/* bitmask for bitfield desc_vm_arb_mode */\n+#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001\n+/* inverted bitmask for bitfield desc_vm_arb_mode */\n+#define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe\n+/* lower bit position of bitfield desc_vm_arb_mode */\n+#define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0\n+/* width of bitfield desc_vm_arb_mode */\n+#define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1\n+/* default value of bitfield desc_vm_arb_mode */\n+#define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0\n+\n+/* tx data_tc{t}_credit_max[b:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"data_tc{t}_credit_max[b:0]\".\n+ * parameter: tc {t} | stride size 0x4 | range [0, 7]\n+ * port=\"pif_tps_data_tc0_credit_max_i[11:0]\"\n+ */\n+\n+/* register address for bitfield data_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)\n+/* bitmask for bitfield data_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000\n+/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff\n+/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16\n+/* width of bitfield data_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12\n+/* default value of bitfield data_tc{t}_credit_max[b:0] */\n+#define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0\n+\n+/* tx data_tc{t}_weight[8:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"data_tc{t}_weight[8:0]\".\n+ * parameter: tc {t} | stride size 0x4 | range [0, 7]\n+ * port=\"pif_tps_data_tc0_weight_i[8:0]\"\n+ */\n+\n+/* register address for bitfield data_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)\n+/* bitmask for bitfield data_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff\n+/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00\n+/* lower bit position of bitfield data_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0\n+/* width of bitfield data_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9\n+/* default value of bitfield data_tc{t}_weight[8:0] */\n+#define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0\n+\n+/* tx reg_res_dsbl bitfield definitions\n+ * preprocessor definitions for the bitfield \"reg_res_dsbl\".\n+ * port=\"pif_tx_reg_res_dsbl_i\"\n+ */\n+\n+/* register address for bitfield reg_res_dsbl */\n+#define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000\n+/* bitmask for bitfield reg_res_dsbl */\n+#define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000\n+/* inverted bitmask for bitfield reg_res_dsbl */\n+#define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff\n+/* lower bit position of bitfield reg_res_dsbl */\n+#define HW_ATL_TX_REG_RES_DSBL_SHIFT 29\n+/* width of bitfield reg_res_dsbl */\n+#define HW_ATL_TX_REG_RES_DSBL_WIDTH 1\n+/* default value of bitfield reg_res_dsbl */\n+#define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1\n+\n+/* mac_phy register access busy bitfield definitions\n+ * preprocessor definitions for the bitfield \"register access busy\".\n+ * port=\"msm_pif_reg_busy_o\"\n+ */\n+\n+/* register address for bitfield register access busy */\n+#define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400\n+/* bitmask for bitfield register access busy */\n+#define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000\n+/* inverted bitmask for bitfield register access busy */\n+#define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff\n+/* lower bit position of bitfield register access busy */\n+#define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12\n+/* width of bitfield register access busy */\n+#define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1\n+\n+/* mac_phy msm register address[7:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"msm register address[7:0]\".\n+ * port=\"pif_msm_reg_addr_i[7:0]\"\n+ */\n+\n+/* register address for bitfield msm register address[7:0] */\n+#define HW_ATL_MSM_REG_ADDR_ADR 0x00004400\n+/* bitmask for bitfield msm register address[7:0] */\n+#define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff\n+/* inverted bitmask for bitfield msm register address[7:0] */\n+#define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00\n+/* lower bit position of bitfield msm register address[7:0] */\n+#define HW_ATL_MSM_REG_ADDR_SHIFT 0\n+/* width of bitfield msm register address[7:0] */\n+#define HW_ATL_MSM_REG_ADDR_WIDTH 8\n+/* default value of bitfield msm register address[7:0] */\n+#define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0\n+\n+/* mac_phy register read strobe bitfield definitions\n+ * preprocessor definitions for the bitfield \"register read strobe\".\n+ * port=\"pif_msm_reg_rden_i\"\n+ */\n+\n+/* register address for bitfield register read strobe */\n+#define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400\n+/* bitmask for bitfield register read strobe */\n+#define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200\n+/* inverted bitmask for bitfield register read strobe */\n+#define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff\n+/* lower bit position of bitfield register read strobe */\n+#define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9\n+/* width of bitfield register read strobe */\n+#define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1\n+/* default value of bitfield register read strobe */\n+#define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0\n+\n+/* mac_phy msm register read data[31:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"msm register read data[31:0]\".\n+ * port=\"msm_pif_reg_rd_data_o[31:0]\"\n+ */\n+\n+/* register address for bitfield msm register read data[31:0] */\n+#define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408\n+/* bitmask for bitfield msm register read data[31:0] */\n+#define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff\n+/* inverted bitmask for bitfield msm register read data[31:0] */\n+#define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000\n+/* lower bit position of bitfield msm register read data[31:0] */\n+#define HW_ATL_MSM_REG_RD_DATA_SHIFT 0\n+/* width of bitfield msm register read data[31:0] */\n+#define HW_ATL_MSM_REG_RD_DATA_WIDTH 32\n+\n+/* mac_phy msm register write data[31:0] bitfield definitions\n+ * preprocessor definitions for the bitfield \"msm register write data[31:0]\".\n+ * port=\"pif_msm_reg_wr_data_i[31:0]\"\n+ */\n+\n+/* register address for bitfield msm register write data[31:0] */\n+#define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404\n+/* bitmask for bitfield msm register write data[31:0] */\n+#define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff\n+/* inverted bitmask for bitfield msm register write data[31:0] */\n+#define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000\n+/* lower bit position of bitfield msm register write data[31:0] */\n+#define HW_ATL_MSM_REG_WR_DATA_SHIFT 0\n+/* width of bitfield msm register write data[31:0] */\n+#define HW_ATL_MSM_REG_WR_DATA_WIDTH 32\n+/* default value of bitfield msm register write data[31:0] */\n+#define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0\n+\n+/* mac_phy register write strobe bitfield definitions\n+ * preprocessor definitions for the bitfield \"register write strobe\".\n+ * port=\"pif_msm_reg_wren_i\"\n+ */\n+\n+/* register address for bitfield register write strobe */\n+#define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400\n+/* bitmask for bitfield register write strobe */\n+#define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100\n+/* inverted bitmask for bitfield register write strobe */\n+#define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff\n+/* lower bit position of bitfield register write strobe */\n+#define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8\n+/* width of bitfield register write strobe */\n+#define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1\n+/* default value of bitfield register write strobe */\n+#define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0\n+\n+/* mif soft reset bitfield definitions\n+ * preprocessor definitions for the bitfield \"soft reset\".\n+ * port=\"pif_glb_res_i\"\n+ */\n+\n+/* register address for bitfield soft reset */\n+#define HW_ATL_GLB_SOFT_RES_ADR 0x00000000\n+/* bitmask for bitfield soft reset */\n+#define HW_ATL_GLB_SOFT_RES_MSK 0x00008000\n+/* inverted bitmask for bitfield soft reset */\n+#define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff\n+/* lower bit position of bitfield soft reset */\n+#define HW_ATL_GLB_SOFT_RES_SHIFT 15\n+/* width of bitfield soft reset */\n+#define HW_ATL_GLB_SOFT_RES_WIDTH 1\n+/* default value of bitfield soft reset */\n+#define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0\n+\n+/* mif register reset disable bitfield definitions\n+ * preprocessor definitions for the bitfield \"register reset disable\".\n+ * port=\"pif_glb_reg_res_dsbl_i\"\n+ */\n+\n+/* register address for bitfield register reset disable */\n+#define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000\n+/* bitmask for bitfield register reset disable */\n+#define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000\n+/* inverted bitmask for bitfield register reset disable */\n+#define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff\n+/* lower bit position of bitfield register reset disable */\n+#define HW_ATL_GLB_REG_RES_DIS_SHIFT 14\n+/* width of bitfield register reset disable */\n+#define HW_ATL_GLB_REG_RES_DIS_WIDTH 1\n+/* default value of bitfield register reset disable */\n+#define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1\n+\n+/* tx dma debug control definitions */\n+#define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u\n+\n+/* tx dma descriptor base address msw definitions */\n+#define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \\\n+\t\t\t(0x00007c04u + (descriptor) * 0x40)\n+\n+/* tx dma total request limit */\n+#define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u\n+\n+/* tx interrupt moderation control register definitions\n+ * Preprocessor definitions for TX Interrupt Moderation Control Register\n+ * Base Address: 0x00008980\n+ * Parameter: queue {Q} | stride size 0x4 | range [0, 31]\n+ */\n+\n+#define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4)\n+\n+/* pcie reg_res_dsbl bitfield definitions\n+ * preprocessor definitions for the bitfield \"reg_res_dsbl\".\n+ * port=\"pif_pci_reg_res_dsbl_i\"\n+ */\n+\n+/* register address for bitfield reg_res_dsbl */\n+#define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000\n+/* bitmask for bitfield reg_res_dsbl */\n+#define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000\n+/* inverted bitmask for bitfield reg_res_dsbl */\n+#define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff\n+/* lower bit position of bitfield reg_res_dsbl */\n+#define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29\n+/* width of bitfield reg_res_dsbl */\n+#define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1\n+/* default value of bitfield reg_res_dsbl */\n+#define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1\n+\n+/* PCI core control register */\n+#define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u\n+\n+/* global microprocessor scratch pad definitions */\n+#define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \\\n+\t(0x00000300u + (scratch_scp) * 0x4)\n+\n+/* register address for bitfield uP Force Interrupt */\n+#define mcp_up_force_interrupt_adr 0x00000404\n+/* bitmask for bitfield uP Force Interrupt */\n+#define mcp_up_force_interrupt_msk 0x00000002\n+/* inverted bitmask for bitfield uP Force Interrupt */\n+#define mcp_up_force_interrupt_mskn 0xFFFFFFFD\n+/* lower bit position of bitfield uP Force Interrupt */\n+#define mcp_up_force_interrupt_shift 1\n+/* width of bitfield uP Force Interrupt */\n+#define mcp_up_force_interrupt_width 1\n+/* default value of bitfield uP Force Interrupt */\n+#define mcp_up_force_interrupt_default 0x0\n+\n+#endif /* HW_ATL_LLH_INTERNAL_H */\n",
    "prefixes": [
        "04/21"
    ]
}