Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/44398/?format=api
{ "id": 44398, "url": "http://patches.dpdk.org/api/patches/44398/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-6-git-send-email-igor.russkikh@aquantia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536333719-32155-6-git-send-email-igor.russkikh@aquantia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536333719-32155-6-git-send-email-igor.russkikh@aquantia.com", "date": "2018-09-07T15:21:43", "name": "[05/21] net/atlantic: b0 hardware layer main logic", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "94629b01c37939f1ab8be06a9edd1526bb909ecc", "submitter": { "id": 1124, "url": "http://patches.dpdk.org/api/people/1124/?format=api", "name": "Igor Russkikh", "email": "igor.russkikh@aquantia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536333719-32155-6-git-send-email-igor.russkikh@aquantia.com/mbox/", "series": [ { "id": 1228, "url": "http://patches.dpdk.org/api/series/1228/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1228", "date": "2018-09-07T15:21:39", "name": "net/atlantic: Aquantia aQtion 10G NIC Family DPDK PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/1228/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44398/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/44398/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7AB4A4F93;\n\tFri, 7 Sep 2018 17:23:24 +0200 (CEST)", "from NAM03-BY2-obe.outbound.protection.outlook.com\n\t(mail-by2nam03on0044.outbound.protection.outlook.com [104.47.42.44])\n\tby dpdk.org (Postfix) with ESMTP id 06E3C2AA0\n\tfor <dev@dpdk.org>; Fri, 7 Sep 2018 17:23:19 +0200 (CEST)", "from ubuntubox.rdc.aquantia.com (95.79.108.179) by\n\tBLUPR0701MB1652.namprd07.prod.outlook.com (2a01:111:e400:58c6::22)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1122.16;\n\tFri, 7 Sep 2018 15:23:10 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=vvkYkA2pocpJ5wotLSt/6oUpFUO46sRYmbcLIqU3jg8=;\n\tb=blfjSLMctFk0CRGSKwk+N7qTCJRgUsqRbhSFRONGb4jsAI5741PTuB7bkTE8wmYBeeSgLg6EHBHfTy5A9+eJMtWQindIxSkUHJkxXq4i/G2gf5lAax2hoIQG3J8F0njNDHviBddPQ9mm6SJ1IISd6EiflIcwIgEVJ/JgjQJgJLs=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Igor.Russkikh@aquantia.com; ", "From": "Igor Russkikh <igor.russkikh@aquantia.com>", "To": "dev@dpdk.org", "Cc": "pavel.belous@aquantia.com, Nadezhda.Krupnina@aquantia.com,\n\tigor.russkikh@aquantia.com, Simon.Edelhaus@aquantia.com,\n\tCorey Melton <comelton@cisco.com>, Ashish Kumar <ashishk2@cisco.com>", "Date": "Fri, 7 Sep 2018 18:21:43 +0300", "Message-Id": "<1536333719-32155-6-git-send-email-igor.russkikh@aquantia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536333719-32155-1-git-send-email-igor.russkikh@aquantia.com>", "References": "<1536333719-32155-1-git-send-email-igor.russkikh@aquantia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[95.79.108.179]", "X-ClientProxiedBy": "BN6PR20CA0060.namprd20.prod.outlook.com\n\t(2603:10b6:404:151::22) To BLUPR0701MB1652.namprd07.prod.outlook.com\n\t(2a01:111:e400:58c6::22)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "35b483ca-60b1-42b0-1d6b-08d614d5d2b4", "X-Microsoft-Antispam": "BCL:0; PCL:0;\n\tRULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(2017052603328)(7153060)(7193020);\n\tSRVR:BLUPR0701MB1652; ", "X-Microsoft-Exchange-Diagnostics": [ "1; BLUPR0701MB1652;\n\t3:aPNt6p9tFSZgnh0RHSh9y6VRb8dBLyOwqAW20M0z37QGkbtf2HdGj0Eo0wPo9ua4wWO20RZoklXqgcEnVbc/ZjPIeqH2Joqreqy3LuHEp3yob+125sAg1sb/PKDjuUW1UULG6JgxVUOEnNAgq/WtxlR93xEQpkdPZMYTexc8fLW56uAUL772AI0xT+RKgnY6HqHxMFFAndNMqnUlGhd3YxYgsNmymvBNyTVXBH4ii9yYaQk7sdSaOJSry7l6lIlR;\n\t25:+Rslese3An08J5oBUtj57w0Jj8UzarNk6HJDz5jM8jpe1Vr6pu3DERb+6kr68vEoTsSH24oUS4MhHSZ808/kctGDHC96Jt59suL1lj2TT8qsSG+OFVFeW7KqMOWr9YjxLjmxDrMyJSDxQmc4SP6fEEiM17o0kuy0I3vyQ/RiagEcg09R8veDPCANiAJLUicyegiTSNOLrElGwYN5EW9Dk+UB97o5Pv5TyW2b5gluaTNmhJb1vCWzYXURnf0/ov159a2EvkVMWyeSV2QuDsrMxltnKG3x/7LK0qRFDTR/uZLvC6RXJaRnfO7nCs3nIRbEJuvDK4Rbpc4l+aowk97tog==;\n\t31:szYwl/fmxA5azvYzw1xgWcnW6iZ8tQv+V7OamVB2NfcCUzufXcFRzD3VZg6hiVCso4zioJNuQgpb/d5GJ7OWwlun95bboHgHBRpv6tYclHiFvjPe95Bpc77Qh5j7foUvrS1Zq4bwIJok4PZHcblwQoont37uEhHppYswEgw8F0oDw/LJmynKEesbbJ+HiNE0n9Q6SXm40Mt5fz8A9vgryNjCUJy4LOtsNgBSxUBj5pU=", "1; BLUPR0701MB1652;\n\t20:PI5hFOdLc5JNVG54OdVmmpLL1p/bF8givNmCejkZ7/n0Q5OkqMAzZ5FpgEwPi6vdP8UOhyPbDsw3Cxep2jlXGIYTKo01fGedILrU/0o8zyeJvH62PdBGdIPHVHE4JSS7mH8FYrJ5dYTlWj3N3+OXRBlRWds/qH/11GFWz//0rE08FrJ03itWThjPMi00o/iH9B/3aXu6Kij58PaOPuicVFP8q7OVqXYOVgT3Che/1cdIaWi/lb2cG1tukwNW8MqGd1USi11TKuBrfZXxVEGsrShfC8a4PrkkAp/d4ZX6NcjZIn1E5bSxtXKOLBh8oZ8HQO4+lselnchrQTUv5ougDkeO4t7cGrpNLthvi6X0MI35ucrDNMHnucleSOISCkELidFfr++1Aklh4JductRu0JDgan+iiADnsy+SqcFlIJ4ytW+evFcG1js/xKj/hiK4E7u67WkLfDA2SA707Kk52HlwZ5oODi6OQu9VfOwot90cHAJRkowg0dbSY0s0y/FR;\n\t4:ihlTMpr6I2n0gTDd8twAv6AHyLJnD0eWgt9goAXPRGfktjHDvZbY37HZ+PM+ZOukhl2RjP0+P7dZFwFsoKScG2YPNc4H+8mrOxnNTSb2/9/uZ2PePwDxIgCWvMz9JZiO7zfeXpvjVNXPxU2u61IFYU/Cml3fagg2y/4J8myQt95ZHHv9sBxWxEKAgG3bKya/QVIROTt9Ee3rGDR/tzNlWL4pkjBi0TqBjiEEEVMdYpzJLKpKoehggeBWV/11IvVCShSchB8ehFovhWfIkSAkWQ==", "=?us-ascii?Q?1; BLUPR0701MB1652;\n\t23:rHILEYQKgbhK+NdXX4TrbGov+9BhrkJHgW5c5QX?=\n\tEzsX+Vouh5tPzV9L/phNjqWmyUepGbG7RHOfY5sB3gCHmN3UAEYpO7NGyEwOcCtidgr0qb5IdmnYB3Ux2SDNakfJipLvZoVG65B80YZzs7NbIhtpVQtfLa9X1UO4kgpWVa/rL3zQWQHuyugqPaiRFNjl+lRi8G4YJNslxmqIzRxHmzJgMcDaZcUoONSAL8TQ0oaQ0/1hiqjx3b+P1N7Bc5Ijr4SAR5bC7suH2deGCy0LzSLhisBaeNt64TlY1lWpYYttK6ggYdEIIwsdqQq23srrPk1g8JxwIiaiNpVhxVgSW4RyytVe+YQe0TCiQPEEf2ZjanUpIUHjY/ton9B1EERl7Z3UAN/073k93wVouCKAZ+FtbjGuopRTzmGHCIbryeDUmcShC8pnv7m+qSQYUYaVJ2pggtGd3pOG60pD5d7pwZ5dTgpVTHdaOFxW3cYyAUNZh6SIqeZuBFWvZI7PyYsZk1kBRaYBaEswifLWxHgL93gD6OgIfhJszvKA2mHOGoMsxADs16AQ0/bUcmSLRPWn3yR1KixSE0HoTJMQeim53JlgigPrjJ9RbzvD37ft34t6oIXWU7ZjyAPIM+GDpcGR+225SkdV50LgIYtT0FnUnbBpt6gWZH/qbg6AgRV2r3vRfp2e/VIOf61qHTdVMxRTKS0kN/0zETUoBSEzTZ7fUxd5pe5U8hkH2OhUqIYlzC4hX2g9sq5uNFRYcRIiQUGQW5o8BDLwW5x6w7OgdFrprBoQVdfKxjl5V/ECCxW1UmE47VUIdst4iYfm9/KrXLt7q5axP25+HMdN5/IWY3Bx2+jEjkTFo26MPfv4RJ3uti2YU9Q8ilWergWZeSiNoAfxBsauUD2361am7nPal7BMGUqSVK82Y4ZN1/5LuwAMF9xyeTrAlk2gJt139agNG2kC8MZY0pnc1SWthd/8UKVdlghP3eNckjVxSxBKDznN4nuqF8/tc00ICKptcbQiAkRMtLXUWc+v7YzbNx/DujTD/fAzKBPYGU2Ix8pcSuCRlbaG/1IxqUT+k/qwYnp7duyu9KHj/JBrh4/xGeg2vnR5bLTVWe80OujtCWVdiwOowDHspMTRQYSbU6mnIXC/a2t17Ddb2FtyaMGeYi93m2viDiOdRrYskMc9969vzyY6oTM7VEg9BeKlRcTk9y91ooqjaCxGkPwFZAbWu0aVeoMrinyk2IQ5Dn4xtpGYXlGNujLxfES2R7WqT10+E+/kRmGLhZlirF8PRW7j/WPg7suadOa60B9PWn9Xt+pFcwgvoMuk=", "1; BLUPR0701MB1652;\n\t6:Tbk6kZwOpvsK8yPIgppcT8TfQ9+ca3w4l9qNuHwn1afK++0D/7Xx45CBkR4nY+QJDoA19s4yzCzUmrTc+Wbv/Qa+G+1DSo6eW+v+RstqTOlVK8xcFh577nyBhSDXJzmlWh9dnNn+JUicxYsKAEMeBoeBLfsjq+yvuLrm90nHaatdH2Kie1+cxWrQY9h/AK5elS2/GN20ba8YRglQ+nyIkg+c1BMQSTzHL90z8v3Gfc1juOdaaRqlvO+pASoNbXBef4rAgJs2M3buzSpH+ZTMrr7QuN+l+ztPjf7ChTzQy0jdYMMYKQhsTIu3/vYMSr8geQJtkV/iMD2N6+uLxfS2XiLutW7wKyc8wHmFVdpuJJYGEuAR5G7wcw6FEX2POte2Nz4rVykOQz5bVYXCGbSxatJUSbNQd0pny28XK2HBovBIg2bNG2YHYR7N4g1EIvo+hJg9QdZ5MBB9MHeu7vUjcA==;\n\t5:lupS8oW2eymQMpGAQXRiovGUefUT+Ob0AuED3R7dMmiE9PnHq+hLOBD3xIaXow+HMbPGh4jn5HEjCTVt49R4CzRd56AaPu+wVZtfkKFQrFZtGzuqwS+2k0pXv6H7rjEnENibqRGaZL/y8CBIA/Lg9/U2EBMHozPwe4H+Js3RDgE=;\n\t7:5cVRq3k2F7L7XAPGIWFhW71pcp/dquXY6+HQ3DiokxH/HsI2qN56UvpbFWaFfzLhDQWPUXpeV8WM3RbayejM9x4aN+gr+LE7lgUyhbx42+aY802JdBedtx4+QF2f/51CfO0XinkH5ZigpdPxdtYkT6Wd3FP60RCkyT5oOcdi0Rszeos9oVdF+ebp5Ff3Z2n+yxFttn1HoX+8TmD2YnSXIu0e2ozGTX3jn8NsukScPi/oAEyWiWiBBXGwK+mT8sAc" ], "X-MS-TrafficTypeDiagnostic": "BLUPR0701MB1652:", "X-Microsoft-Antispam-PRVS": "<BLUPR0701MB1652302A46B58E159171589098000@BLUPR0701MB1652.namprd07.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-MS-Exchange-SenderADCheck": "1", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(3231311)(944501410)(52105095)(10201501046)(3002001)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123558120)(20161123562045)(20161123564045)(20161123560045)(201708071742011)(7699050);\n\tSRVR:BLUPR0701MB1652; BCL:0; PCL:0; RULEID:; SRVR:BLUPR0701MB1652; ", "X-Forefront-PRVS": "07880C4932", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(39850400004)(396003)(376002)(366004)(346002)(136003)(189003)(199004)(81156014)(81166006)(44832011)(8936002)(2351001)(486006)(106356001)(2361001)(105586002)(446003)(2906002)(50226002)(476003)(11346002)(956004)(2616005)(305945005)(7736002)(16586007)(316002)(54906003)(14444005)(16526019)(66066001)(26005)(7696005)(52116002)(8676002)(51416003)(76176011)(186003)(386003)(68736007)(478600001)(6666003)(6916009)(6486002)(5660300001)(53936002)(47776003)(4326008)(25786009)(86362001)(48376002)(50466002)(575784001)(72206003)(6116002)(97736004)(36756003)(3846002)(2004002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR0701MB1652;\n\tH:ubuntubox.rdc.aquantia.com; \n\tFPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; ", "Received-SPF": "None (protection.outlook.com: aquantia.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "G1zr/RgPSPqEtPn0zMVVXpq/bz8oUMaEplWzgUVkWOszKcLhrAXS0Tc0Qy4BF5uUi3E7rftJlaHXjN4RW7Zglry11H6KVdVvDlpIPLIxNaimF8aVwDUzZJL2haOgZ0NxH/Wy9h7Ve4ne2HvYk5D1fDUoWHtuwY5nz/aZzGzrG30v7/uOlkqXdwMByPyCOmdbZs1LMjs0GlSbvbOTpwPZGkAiljKAwgPE+A70EpLF+nqoMuxmjeVFYAqRobiMoKdyNDmwCggxRfm/xQy6EJeeKdHMRyuIB81C9aGulN8pp+lQwHT8hHdTEYl75E6fe7jAN3RvRyrPeWgw05Zs7x407qn22qIreyS6svJFpxNUycw=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "aquantia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Sep 2018 15:23:10.1601\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "35b483ca-60b1-42b0-1d6b-08d614d5d2b4", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "83e2e134-991c-4ede-8ced-34d47e38e6b1", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR0701MB1652", "Subject": "[dpdk-dev] [PATCH 05/21] net/atlantic: b0 hardware layer main logic", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This is hw_atl logic layer derived from linux atlantic\ndriver. It contains RX/TX hardware initialization\nsequences, various hw configuration.\n\nSigned-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\n---\n drivers/net/atlantic/hw_atl/hw_atl_b0.c | 504 +++++++++++++++++++++++\n drivers/net/atlantic/hw_atl/hw_atl_b0.h | 45 ++\n drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h | 151 +++++++\n 3 files changed, 700 insertions(+)\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.c\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0.h\n create mode 100644 drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h", "diff": "diff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/atlantic/hw_atl/hw_atl_b0.c\nnew file mode 100644\nindex 000000000..71f5b0633\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.c\n@@ -0,0 +1,504 @@\n+/*\n+ * aQuantia Corporation Network Driver\n+ * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ */\n+\n+/* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */\n+\n+#include \"../atl_types.h\"\n+#include \"hw_atl_b0.h\"\n+\n+#include \"../atl_hw_regs.h\"\n+#include \"hw_atl_utils.h\"\n+#include \"hw_atl_llh.h\"\n+#include \"hw_atl_b0_internal.h\"\n+#include \"hw_atl_llh_internal.h\"\n+#include \"../atl_logs.h\"\n+\n+int hw_atl_b0_hw_rss_hash_type_set(struct aq_hw_s *self);\n+\n+int hw_atl_b0_hw_reset(struct aq_hw_s *self)\n+{\n+\tint err = 0;\n+\n+\terr = hw_atl_utils_soft_reset(self);\n+\tif (err)\n+\t\treturn err;\n+\n+\tself->aq_fw_ops->set_state(self, MPI_RESET);\n+\n+\treturn err;\n+}\n+\n+static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)\n+{\n+\tu32 tc = 0U;\n+\tu32 buff_size = 0U;\n+\tunsigned int i_priority = 0U;\n+\tbool is_rx_flow_control = false;\n+\n+\t/* TPS Descriptor rate init */\n+\thw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);\n+\thw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);\n+\n+\t/* TPS VM init */\n+\thw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);\n+\n+\t/* TPS TC credits init */\n+\thw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);\n+\thw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);\n+\n+\thw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);\n+\thw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);\n+\thw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);\n+\thw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);\n+\n+\t/* Tx buf size */\n+\tbuff_size = HW_ATL_B0_TXBUF_MAX;\n+\n+\thw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);\n+\thw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024 / 32U) * 66U) /\n+\t\t\t\t\t\t 100U, tc);\n+\thw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024 / 32U) * 50U) /\n+\t\t\t\t\t\t 100U, tc);\n+\n+\t/* QoS Rx buf size per TC */\n+\ttc = 0;\n+\tis_rx_flow_control = 0;//TODO (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);\n+\tbuff_size = HW_ATL_B0_RXBUF_MAX;\n+\n+\thw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);\n+\thw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024U / 32U) * 66U) /\n+\t\t\t\t\t\t 100U, tc);\n+\thw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,\n+\t\t\t\t\t\t (buff_size *\n+\t\t\t\t\t\t (1024U / 32U) * 50U) /\n+\t\t\t\t\t\t 100U, tc);\n+\thw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);\n+\n+\t/* QoS 802.1p priority -> TC mapping */\n+\tfor (i_priority = 8U; i_priority--;)\n+\t\thw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,\n+\t\t\t\t struct aq_rss_parameters *rss_params)\n+{\n+\tstruct aq_hw_cfg_s *cfg = self->aq_nic_cfg;\n+\tint err = 0;\n+\tunsigned int i = 0U;\n+\tunsigned int addr = 0U;\n+\n+\tfor (i = 10, addr = 0U; i--; ++addr) {\n+\t\tu32 key_data = cfg->is_rss ?\n+\t\t\thtonl(rss_params->hash_secret_key[i]) : 0U;\n+\t\thw_atl_rpf_rss_key_wr_data_set(self, key_data);\n+\t\thw_atl_rpf_rss_key_addr_set(self, addr);\n+\t\thw_atl_rpf_rss_key_wr_en_set(self, 1U);\n+\t\tAQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,\n+\t\t\t 1000U, 10U);\n+\t\tif (err < 0)\n+\t\t\tgoto err_exit;\n+\t}\n+\n+\t/* RSS Ring selection */\n+\thw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ? 0xB3333333U : 0x00000000U);\n+\thw_atl_b0_hw_rss_hash_type_set(self);\n+\n+\terr = aq_hw_err_from_flags(self);\n+\n+err_exit:\n+\treturn err;\n+}\n+\n+\n+int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,\n+\t\t\tstruct aq_rss_parameters *rss_params)\n+{\n+\tu8 *indirection_table = rss_params->indirection_table;\n+\tu32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);\n+\tu32 i = 0;\n+\tu32 addr = 0;\n+\tu32 val = 0;\n+\tu32 shift = 0;\t\n+\tint err = 0;\n+\n+\tfor (i = 0; i < HW_ATL_B0_RSS_REDIRECTION_MAX; i++) {\n+\t\tval |= (u32)(indirection_table[i] % num_rss_queues) << shift;\n+\t\tshift += 3;\n+\n+\t\tif (shift < 16)\n+\t\t\tcontinue;\n+\n+\t\thw_atl_rpf_rss_redir_tbl_wr_data_set(self, val & 0xffff);\n+\t\thw_atl_rpf_rss_redir_tbl_addr_set(self, addr);\n+\n+\t\thw_atl_rpf_rss_redir_wr_en_set(self, 1U);\n+\t\tAQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,\n+\t\t\t1000U, 10U);\n+\n+\t\t if (err < 0)\n+\t\t\tgoto err_exit;\n+\n+\t\tshift -= 16;\n+\t\tval >>= 16;\n+\t\taddr++;\n+\t}\n+\n+err_exit:\n+\treturn err;\n+}\t\t\n+\n+static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self)\n+\t\t\t\t /*struct aq_nic_cfg_s *aq_nic_cfg)*/\n+{\n+\tunsigned int i;\n+\n+\t/* TX checksums offloads*/\n+\thw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);\n+\thw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);\n+\n+\t/* RX checksums offloads*/\n+\thw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);\n+\thw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);\n+\n+\t/* LSO offloads*/\n+\thw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);\n+\n+/* LRO offloads */\n+\t{\n+\t\tunsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :\n+\t\t\t((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :\n+\t\t\t((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));\n+\n+\t\tfor (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)\n+\t\t\thw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);\n+\n+\t\thw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);\n+\t\thw_atl_rpo_lro_inactive_interval_set(self, 0);\n+\t\thw_atl_rpo_lro_max_coalescing_interval_set(self, 2);\n+\n+\t\thw_atl_rpo_lro_qsessions_lim_set(self, 1U);\n+\n+\t\thw_atl_rpo_lro_total_desc_lim_set(self, 2U);\n+\n+\t\thw_atl_rpo_lro_patch_optimization_en_set(self, 0U);\n+\n+\t\thw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);\n+\n+\t\thw_atl_rpo_lro_pkt_lim_set(self, 1U);\n+\n+\t\thw_atl_rpo_lro_en_set(self, self->aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);\n+\t}\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+static\n+int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)\n+{\n+\t/* Tx TC/RSS number config */\n+\thw_atl_rpb_tps_tx_tc_mode_set(self, 1U);\n+\n+\thw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);\n+\thw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);\n+\thw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);\n+\n+\t/* Tx interrupts */\n+\thw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);\n+\n+\t/* misc */\n+\taq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?\n+\t\t\t0x00010000U : 0x00000000U);\n+\thw_atl_tdm_tx_dca_en_set(self, 0U);\n+\thw_atl_tdm_tx_dca_mode_set(self, 0U);\n+\n+\thw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+static\n+int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)\n+{\n+\tstruct aq_hw_cfg_s *cfg = self->aq_nic_cfg;\n+\tint i;\n+\n+\t/* Rx TC/RSS number config */\n+\thw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U); /* 1: 4TC/8Queues */\n+\n+\t/* Rx flow control */\n+\thw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);\n+\n+\t/* RSS Ring selection */\n+\thw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?\n+\t\t\t\t\t0xB3333333U : 0x00000000U);\n+\n+\t/* Multicast filters */\n+\tfor (i = HW_ATL_B0_MAC_MAX; i--;) {\n+\t\thw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);\n+\t\thw_atl_rpfl2unicast_flr_act_set(self, 1U, i);\n+\t}\n+\n+\thw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);\n+\thw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);\n+\n+\t/* Vlan filters */\n+\thw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);\n+\thw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);\n+\n+\t/* VLAN proimisc bu defauld */\n+\thw_atl_rpf_vlan_prom_mode_en_set(self, 1);\n+\n+\t/* Rx Interrupts */\n+\thw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);\n+\n+\thw_atl_b0_hw_rss_hash_type_set(self);\n+\n+\thw_atl_rpfl2broadcast_flr_act_set(self, 1U);\n+\thw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));\n+\n+\thw_atl_rdm_rx_dca_en_set(self, 0U);\n+\thw_atl_rdm_rx_dca_mode_set(self, 0U);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+#define pif_rpf_rss_ipv4_hdr_only_i (1 << 4) //calc hash only in IPv4 header, regardless of presence of TCP\n+#define pif_rpf_rss_ipv4_tcp_hdr_only_i (1 << 3) //calc hash only if TCP header and IPv4\n+#define pif_rpf_rss_ipv6_hdr_only_i (1 << 2) //calc hash only in IPv6 header, regardless of presence of TCP\n+#define pif_rpf_rss_ipv6_tcp_hdr_only_i (1 << 1) //calc hash only if TCP header and IPv4\n+#define pif_rpf_rss_dont_use_udp_i (1 << 0) //bug 5124 - rss hashing types - FIXME\n+\n+\n+int hw_atl_b0_hw_rss_hash_type_set(struct aq_hw_s *self)\n+{\n+\t/* misc */\n+\tunsigned int control_reg_val = IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U;\n+\n+\t/* RSS hash type set for IP/TCP */\n+\tcontrol_reg_val |= pif_rpf_rss_ipv4_hdr_only_i;//0x1EU;\n+\n+\taq_hw_write_reg(self, 0x5040U, control_reg_val);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)\n+{\n+\tint err = 0;\n+\tunsigned int h = 0U;\n+\tunsigned int l = 0U;\n+\n+\tif (!mac_addr) {\n+\t\terr = -EINVAL;\n+\t\tgoto err_exit;\n+\t}\n+\th = (mac_addr[0] << 8) | (mac_addr[1]);\n+\tl = (mac_addr[2] << 24) | (mac_addr[3] << 16) |\n+\t\t(mac_addr[4] << 8) | mac_addr[5];\n+\n+\thw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);\n+\thw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);\n+\thw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);\n+\thw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);\n+\n+\terr = aq_hw_err_from_flags(self);\n+\n+err_exit:\n+\treturn err;\n+}\n+\n+int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)\n+{\n+\tstatic u32 aq_hw_atl_igcr_table_[4][2] = {\n+\t\t{ 0x20000080U, 0x20000080U }, /* AQ_IRQ_INVALID */\n+\t\t{ 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */\n+\t\t{ 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */\n+\t\t{ 0x200000A2U, 0x200000A6U } /* AQ_IRQ_MSIX */\n+\t};\n+\n+\tint err = 0;\n+\tu32 val;\n+\n+\tstruct aq_hw_cfg_s *aq_nic_cfg = self->aq_nic_cfg;\n+\n+\thw_atl_b0_hw_init_tx_path(self);\n+\thw_atl_b0_hw_init_rx_path(self);\n+\n+\thw_atl_b0_hw_mac_addr_set(self, mac_addr);\n+\n+\t// TODO: Isnt that link up is too early?\n+\tself->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);\n+\tself->aq_fw_ops->set_state(self, MPI_INIT);\n+\n+\thw_atl_b0_hw_qos_set(self);\n+\thw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);\n+\thw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);\n+\n+\t/* Force limit MRRS on RDM/TDM to 2K */\n+\tval = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);\n+\taq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,\n+\t\t\t(val & ~0x707) | 0x404);\n+\n+\t/* TX DMA total request limit. B0 hardware is not capable to\n+\t * handle more than (8K-MRRS) incoming DMA data.\n+\t * Value 24 in 256byte units\n+\t */\n+\taq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);\n+\n+\t/* Reset link status and read out initial hardware counters */\n+\tself->aq_link_status.mbps = 0;\n+\tself->aq_fw_ops->update_stats(self);\n+\n+\terr = aq_hw_err_from_flags(self);\n+\tif (err < 0)\n+\t\tgoto err_exit;\n+\n+\t/* Interrupts */\n+\thw_atl_reg_irq_glb_ctl_set(self, aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]\n+\t\t\t\t\t\t [(aq_nic_cfg->vecs > 1U) ?\n+\t\t\t\t\t\t 1 : 0]);\n+\n+\thw_atl_itr_irq_auto_masklsw_set(self, 0xffffffff);//aq_nic_cfg->irq_mask);\n+\n+\t/* Interrupts */\n+\thw_atl_reg_gen_irq_map_set(self, 0, 0);\n+\thw_atl_reg_gen_irq_map_set(self, 0x80 | ATL_IRQ_CAUSE_LINK, 3);\n+\n+\thw_atl_b0_hw_offload_set(self);//, aq_nic_cfg);\n+\n+err_exit:\n+\treturn err;\n+}\n+\n+int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_tdm_tx_desc_en_set(self, 1, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_rdm_rx_desc_en_set(self, 1, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_start(struct aq_hw_s *self)\n+{\n+\thw_atl_tpb_tx_buff_en_set(self, 1);\n+\thw_atl_rpb_rx_buff_en_set(self, 1);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index)\n+{\n+\thw_atl_reg_tx_dma_desc_tail_ptr_set(self, tail, index);\n+\treturn 0;\n+}\n+\n+int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr,\n+\t\tint index, int size, int buff_size, int cpu, int vec)\n+{\n+\tu32 dma_desc_addr_lsw = (u32)base_addr;\n+\tu32 dma_desc_addr_msw = (u32)(base_addr >> 32);\n+\n+\thw_atl_rdm_rx_desc_en_set(self, false, index);\n+\n+\thw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index);\n+\n+\thw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw, index);\n+\n+\thw_atl_reg_rx_dma_desc_base_addressmswset(self, dma_desc_addr_msw, index);\n+\n+\thw_atl_rdm_rx_desc_len_set(self, size / 8U, index);\n+\n+\thw_atl_rdm_rx_desc_data_buff_size_set(self, buff_size / 1024U, index);\n+\n+\thw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, index);\n+\thw_atl_rdm_rx_desc_head_splitting_set(self, 0U, index);\n+\thw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, index);\n+\n+\t/* Rx ring set mode */\n+\n+\t/* Mapping interrupt vector */\n+\thw_atl_itr_irq_map_rx_set(self, vec, index);\n+\thw_atl_itr_irq_map_en_rx_set(self, true, index);\n+\n+\thw_atl_rdm_cpu_id_set(self, cpu, index);\n+\thw_atl_rdm_rx_desc_dca_en_set(self, 0U, index);\n+\thw_atl_rdm_rx_head_dca_en_set(self, 0U, index);\n+\thw_atl_rdm_rx_pld_dca_en_set(self, 0U, index);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr, int index, int size, int cpu, int vec)\n+{\n+\tu32 dma_desc_lsw_addr = (u32)base_addr;\n+\tu32 dma_desc_msw_addr = (u32)(base_addr >> 32);\n+\n+\thw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr, index);\n+\n+\thw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr, index);\n+\n+\thw_atl_tdm_tx_desc_len_set(self, size / 8U, index);\n+\n+\thw_atl_b0_hw_tx_ring_tail_update(self, 0, index);\n+\n+\t/* Set Tx threshold */\n+\thw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, index);\n+\n+\t/* Mapping interrupt vector */\n+\thw_atl_itr_irq_map_tx_set(self, vec, index);\n+\thw_atl_itr_irq_map_en_tx_set(self, true, index);\n+\n+\thw_atl_tdm_cpu_id_set(self, cpu, index);\n+\thw_atl_tdm_tx_desc_dca_en_set(self, 0U, index);\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)\n+{\n+\thw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)\n+{\n+\thw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));\n+\thw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));\n+\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)\n+{\n+\t*mask = hw_atl_itr_irq_statuslsw_get(self);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_tdm_tx_desc_en_set(self, 0U, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\n+int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index)\n+{\n+\thw_atl_rdm_rx_desc_en_set(self, 0U, index);\n+\treturn aq_hw_err_from_flags(self);\n+}\n+\ndiff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/atlantic/hw_atl/hw_atl_b0.h\nnew file mode 100644\nindex 000000000..d50b2de5f\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_b0.h\n@@ -0,0 +1,45 @@\n+/*\n+ * aQuantia Corporation Network Driver\n+ * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ */\n+\n+/* File hw_atl_b0.h: Declaration of abstract interface for Atlantic hardware\n+ * specific functions.\n+ */\n+\n+#ifndef HW_ATL_B0_H\n+#define HW_ATL_B0_H\n+\n+int hw_atl_b0_hw_reset(struct aq_hw_s *self);\n+int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr);\n+\n+int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self, uint64_t base_addr, int index, int size, int cpu, int vec);\n+int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self, uint64_t base_addr,\n+\t\tint index, int size, int buff_size, int cpu, int vec);\n+\n+int hw_atl_b0_hw_start(struct aq_hw_s *self);\n+\n+int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self, int index);\n+int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self, int index);\n+\n+\n+int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, int index);\n+int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, int index);\n+\n+\n+int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self, int tail, int index);\n+\n+int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,\n+\t\t\t\t struct aq_rss_parameters *rss_params);\n+int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,\n+\t\t\t\tstruct aq_rss_parameters *rss_params);\n+\n+int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask);\n+int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask);\n+int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask);\n+\n+#endif /* HW_ATL_B0_H */\ndiff --git a/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h\nnew file mode 100644\nindex 000000000..95b4b8320\n--- /dev/null\n+++ b/drivers/net/atlantic/hw_atl/hw_atl_b0_internal.h\n@@ -0,0 +1,151 @@\n+/*\n+ * aQuantia Corporation Network Driver\n+ * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ */\n+\n+/* File hw_atl_b0_internal.h: Definition of Atlantic B0 chip specific\n+ * constants.\n+ */\n+\n+#ifndef HW_ATL_B0_INTERNAL_H\n+#define HW_ATL_B0_INTERNAL_H\n+\n+\n+#define HW_ATL_B0_MTU_JUMBO 16352U\n+#define HW_ATL_B0_MTU 1514U\n+\n+#define HW_ATL_B0_TX_RINGS 4U\n+#define HW_ATL_B0_RX_RINGS 4U\n+\n+#define HW_ATL_B0_RINGS_MAX 32U\n+#define HW_ATL_B0_TXD_SIZE (16U)\n+#define HW_ATL_B0_RXD_SIZE (16U)\n+\n+#define HW_ATL_B0_MAC 0U\n+#define HW_ATL_B0_MAC_MIN 1U\n+#define HW_ATL_B0_MAC_MAX 33U\n+\n+/* Maximum supported VLAN filters */\n+#define HW_ATL_B0_MAX_VLAN_IDS 16\n+\n+/* UCAST/MCAST filters */\n+#define HW_ATL_B0_UCAST_FILTERS_MAX 38\n+#define HW_ATL_B0_MCAST_FILTERS_MAX 8\n+\n+/* interrupts */\n+#define HW_ATL_B0_ERR_INT 8U\n+#define HW_ATL_B0_INT_MASK (0xFFFFFFFFU)\n+\n+#define HW_ATL_B0_TXD_CTL2_LEN (0xFFFFC000)\n+#define HW_ATL_B0_TXD_CTL2_CTX_EN (0x00002000)\n+#define HW_ATL_B0_TXD_CTL2_CTX_IDX (0x00001000)\n+\n+#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD (0x00000001)\n+#define HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC (0x00000002)\n+#define HW_ATL_B0_TXD_CTL_BLEN (0x000FFFF0)\n+#define HW_ATL_B0_TXD_CTL_DD (0x00100000)\n+#define HW_ATL_B0_TXD_CTL_EOP (0x00200000)\n+\n+#define HW_ATL_B0_TXD_CTL_CMD_X (0x3FC00000)\n+\n+#define HW_ATL_B0_TXD_CTL_CMD_VLAN BIT(22)\n+#define HW_ATL_B0_TXD_CTL_CMD_FCS BIT(23)\n+#define HW_ATL_B0_TXD_CTL_CMD_IPCSO BIT(24)\n+#define HW_ATL_B0_TXD_CTL_CMD_TUCSO BIT(25)\n+#define HW_ATL_B0_TXD_CTL_CMD_LSO BIT(26)\n+#define HW_ATL_B0_TXD_CTL_CMD_WB BIT(27)\n+#define HW_ATL_B0_TXD_CTL_CMD_VXLAN BIT(28)\n+\n+#define HW_ATL_B0_TXD_CTL_CMD_IPV6 BIT(21)\n+#define HW_ATL_B0_TXD_CTL_CMD_TCP BIT(22)\n+\n+#define HW_ATL_B0_MPI_CONTROL_ADR 0x0368U\n+#define HW_ATL_B0_MPI_STATE_ADR 0x036CU\n+\n+#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU\n+#define HW_ATL_B0_MPI_SPEED_SHIFT 16U\n+\n+#define HW_ATL_B0_TXBUF_MAX 160U\n+#define HW_ATL_B0_RXBUF_MAX 320U\n+\n+#define HW_ATL_B0_RXD_BUF_SIZE_MAX (16*1024)\n+\n+#define HW_ATL_B0_RSS_REDIRECTION_MAX 64U\n+#define HW_ATL_B0_RSS_REDIRECTION_BITS 3U\n+#define HW_ATL_B0_RSS_HASHKEY_BITS 320U\n+\n+#define HW_ATL_B0_TCRSS_4_8 1\n+#define HW_ATL_B0_TC_MAX 1U\n+#define HW_ATL_B0_RSS_MAX 8U\n+\n+#define HW_ATL_B0_LRO_RXD_MAX 2U\n+#define HW_ATL_B0_RS_SLIP_ENABLED 0U\n+\n+/* (256k -1(max pay_len) - 54(header)) */\n+#define HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE 262089U\n+\n+/* (256k -1(max pay_len) - 74(header)) */\n+#define HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE 262069U\n+\n+#define HW_ATL_B0_CHIP_REVISION_B0 0xA0U\n+#define HW_ATL_B0_CHIP_REVISION_UNKNOWN 0xFFU\n+\n+#define HW_ATL_B0_FW_SEMA_RAM 0x2U\n+\n+#define HW_ATL_B0_TXC_LEN_TUNLEN (0x0000FF00)\n+#define HW_ATL_B0_TXC_LEN_OUTLEN (0xFFFF0000)\n+\n+#define HW_ATL_B0_TXC_CTL_DESC_TYPE (0x00000007)\n+#define HW_ATL_B0_TXC_CTL_CTX_ID (0x00000008)\n+#define HW_ATL_B0_TXC_CTL_VLAN (0x000FFFF0)\n+#define HW_ATL_B0_TXC_CTL_CMD (0x00F00000)\n+#define HW_ATL_B0_TXC_CTL_L2LEN (0x7F000000)\n+\n+#define HW_ATL_B0_TXC_CTL_L3LEN (0x80000000)\t/* L3LEN lsb */\n+#define HW_ATL_B0_TXC_LEN2_L3LEN (0x000000FF)\t/* L3LE upper bits */\n+#define HW_ATL_B0_TXC_LEN2_L4LEN (0x0000FF00)\n+#define HW_ATL_B0_TXC_LEN2_MSSLEN (0xFFFF0000)\n+\n+#define HW_ATL_B0_RXD_DD (0x1)\n+#define HW_ATL_B0_RXD_NCEA0 (0x1)\n+\n+#define HW_ATL_B0_RXD_WB_STAT_RSSTYPE (0x0000000F)\n+#define HW_ATL_B0_RXD_WB_STAT_PKTTYPE (0x00000FF0)\n+#define HW_ATL_B0_RXD_WB_STAT_RXCTRL (0x00180000)\n+#define HW_ATL_B0_RXD_WB_STAT_SPLHDR (0x00200000)\n+#define HW_ATL_B0_RXD_WB_STAT_HDRLEN (0xFFC00000)\n+\n+#define HW_ATL_B0_RXD_WB_STAT2_DD (0x0001)\n+#define HW_ATL_B0_RXD_WB_STAT2_EOP (0x0002)\n+#define HW_ATL_B0_RXD_WB_STAT2_RXSTAT (0x003C)\n+#define HW_ATL_B0_RXD_WB_STAT2_MACERR (0x0004)\n+#define HW_ATL_B0_RXD_WB_STAT2_IP4ERR (0x0008)\n+#define HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR (0x0010)\n+#define HW_ATL_B0_RXD_WB_STAT2_RXESTAT (0x0FC0)\n+#define HW_ATL_B0_RXD_WB_STAT2_RSCCNT (0xF000)\n+\n+#define L2_FILTER_ACTION_DISCARD (0x0)\n+#define L2_FILTER_ACTION_HOST (0x1)\n+\n+#define HW_ATL_B0_UCP_0X370_REG (0x370)\n+\n+#define HW_ATL_B0_FLUSH() AQ_HW_READ_REG(self, 0x10)\n+\n+#define HW_ATL_INTR_MODER_MAX 0x1FF\n+#define HW_ATL_INTR_MODER_MIN 0xFF\n+\n+#define HW_ATL_B0_MIN_RXD \\\n+\t(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))\n+#define HW_ATL_B0_MIN_TXD \\\n+\t(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))\n+\n+#define HW_ATL_B0_MAX_RXD 8184U\n+#define HW_ATL_B0_MAX_TXD 8184U\n+\n+/* HW layer capabilities */\n+\n+#endif /* HW_ATL_B0_INTERNAL_H */\n", "prefixes": [ "05/21" ] }