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GET /api/patches/44253/?format=api
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{
    "id": 44253,
    "url": "http://patches.dpdk.org/api/patches/44253/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536069590-2675-2-git-send-email-tdu@semihalf.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1536069590-2675-2-git-send-email-tdu@semihalf.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1536069590-2675-2-git-send-email-tdu@semihalf.com",
    "date": "2018-09-04T13:59:48",
    "name": "[1/3] doc: update mvsam documentation",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "adefb2fc7bc21e698e6359053b1662136a2ca037",
    "submitter": {
        "id": 846,
        "url": "http://patches.dpdk.org/api/people/846/?format=api",
        "name": "Tomasz Duszynski",
        "email": "tdu@semihalf.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536069590-2675-2-git-send-email-tdu@semihalf.com/mbox/",
    "series": [
        {
            "id": 1172,
            "url": "http://patches.dpdk.org/api/series/1172/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1172",
            "date": "2018-09-04T13:59:47",
            "name": "crypto/mvsam: align with MUSDK 18.09",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/1172/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/44253/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/44253/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
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            "from mail-lj1-f194.google.com (mail-lj1-f194.google.com\n\t[209.85.208.194]) by dpdk.org (Postfix) with ESMTP id 55E505A\n\tfor <dev@dpdk.org>; Tue,  4 Sep 2018 15:59:59 +0200 (CEST)",
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        ],
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        "X-Gm-Message-State": "APzg51DWQQaExUaRCGrBJCraeoN5fv890qT92S3N2ZOaWHNlS5KdAerP\n\tQ9GbaUV7WRcDohzHY7V9s1SWMsjWsex1Ig==",
        "X-Google-Smtp-Source": "ANB0VdagANJx0tlZo5YHHc4yvmrZU3JPMq59XFom1uwXN5Sv70LzO9aTRRTo+LPlh6ysM1ogqonrKQ==",
        "X-Received": "by 2002:a2e:658a:: with SMTP id\n\te10-v6mr18516636ljf.99.1536069598743; \n\tTue, 04 Sep 2018 06:59:58 -0700 (PDT)",
        "From": "Tomasz Duszynski <tdu@semihalf.com>",
        "To": "dev@dpdk.org",
        "Cc": "nsamsono@marvell.com, mw@semihalf.com, Dmitri Epshtein <dima@marvell.com>,\n\tTomasz Duszynski <tdu@semihalf.com>",
        "Date": "Tue,  4 Sep 2018 15:59:48 +0200",
        "Message-Id": "<1536069590-2675-2-git-send-email-tdu@semihalf.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1536069590-2675-1-git-send-email-tdu@semihalf.com>",
        "References": "<1536069590-2675-1-git-send-email-tdu@semihalf.com>",
        "Subject": "[dpdk-dev] [PATCH 1/3] doc: update mvsam documentation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Dmitri Epshtein <dima@marvell.com>\n\nUpdate mvsam documentation.\n\nSigned-off-by: Dmitri Epshtein <dima@marvell.com>\nSigned-off-by: Tomasz Duszynski <tdu@semihalf.com>\nSigned-off-by: Natalie Samsonov <nsamsono@marvell.com>\n---\n doc/guides/cryptodevs/features/mvsam.ini |  10 +++\n doc/guides/cryptodevs/mvsam.rst          | 147 ++++++++++---------------------\n 2 files changed, 57 insertions(+), 100 deletions(-)",
    "diff": "diff --git a/doc/guides/cryptodevs/features/mvsam.ini b/doc/guides/cryptodevs/features/mvsam.ini\nindex b7c105a..dd17a4c 100644\n--- a/doc/guides/cryptodevs/features/mvsam.ini\n+++ b/doc/guides/cryptodevs/features/mvsam.ini\n@@ -5,17 +5,22 @@\n [Features]\n Symmetric crypto       = Y\n Sym operation chaining = Y\n+HW Accelerated         = Y\n \n ;\n ; Supported crypto algorithms of a default crypto driver.\n ;\n [Cipher]\n+NULL           = Y\n AES CBC (128)  = Y\n AES CBC (192)  = Y\n AES CBC (256)  = Y\n AES CTR (128)  = Y\n AES CTR (192)  = Y\n AES CTR (256)  = Y\n+AES ECB (128)  = Y\n+AES ECB (192)  = Y\n+AES ECB (256)  = Y\n 3DES CBC       = Y\n 3DES CTR       = Y\n \n@@ -23,10 +28,13 @@ AES CTR (256)  = Y\n ; Supported authentication algorithms of a default crypto driver.\n ;\n [Auth]\n+NULL         = Y\n MD5          = Y\n MD5 HMAC     = Y\n SHA1         = Y\n SHA1 HMAC    = Y\n+SHA224       = Y\n+SHA224 HMAC  = Y\n SHA256       = Y\n SHA256 HMAC  = Y\n SHA384       = Y\n@@ -40,3 +48,5 @@ AES GMAC     = Y\n ;\n [AEAD]\n AES GCM (128) = Y\n+AES GCM (192) = Y\n+AES GCM (256) = Y\ndiff --git a/doc/guides/cryptodevs/mvsam.rst b/doc/guides/cryptodevs/mvsam.rst\nindex fd418c2..7acae19 100644\n--- a/doc/guides/cryptodevs/mvsam.rst\n+++ b/doc/guides/cryptodevs/mvsam.rst\n@@ -37,32 +37,50 @@ support by utilizing MUSDK library, which provides cryptographic operations\n acceleration by using Security Acceleration Engine (EIP197) directly from\n user-space with minimum overhead and high performance.\n \n+Detailed information about SoCs that use MVSAM crypto driver can be obtained here:\n+\n+* https://www.marvell.com/embedded-processors/armada-70xx/\n+* https://www.marvell.com/embedded-processors/armada-80xx/\n+* https://www.marvell.com/embedded-processors/armada-3700/\n+\n+\n Features\n --------\n \n MVSAM CRYPTO PMD has support for:\n \n-* Symmetric crypto\n-* Sym operation chaining\n-* AES CBC (128)\n-* AES CBC (192)\n-* AES CBC (256)\n-* AES CTR (128)\n-* AES CTR (192)\n-* AES CTR (256)\n-* 3DES CBC\n-* 3DES CTR\n-* MD5\n-* MD5 HMAC\n-* SHA1\n-* SHA1 HMAC\n-* SHA256\n-* SHA256 HMAC\n-* SHA384\n-* SHA384 HMAC\n-* SHA512\n-* SHA512 HMAC\n-* AES GCM (128)\n+Cipher algorithms:\n+\n+* ``RTE_CRYPTO_CIPHER_NULL``\n+* ``RTE_CRYPTO_CIPHER_AES_CBC``\n+* ``RTE_CRYPTO_CIPHER_AES_CTR``\n+* ``RTE_CRYPTO_CIPHER_AES_ECB``\n+* ``RTE_CRYPTO_CIPHER_3DES_CBC``\n+* ``RTE_CRYPTO_CIPHER_3DES_CTR``\n+* ``RTE_CRYPTO_CIPHER_3DES_ECB``\n+\n+Hash algorithms:\n+\n+* ``RTE_CRYPTO_AUTH_NULL``\n+* ``RTE_CRYPTO_AUTH_MD5``\n+* ``RTE_CRYPTO_AUTH_MD5_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA1``\n+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA224``\n+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA256``\n+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA384``\n+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``\n+* ``RTE_CRYPTO_AUTH_SHA512``\n+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``\n+* ``RTE_CRYPTO_AUTH_AES_GMAC``\n+\n+AEAD algorithms:\n+\n+* ``RTE_CRYPTO_AEAD_AES_GCM``\n+\n+For supported feature flags please consult :doc:`overview`.\n \n Limitations\n -----------\n@@ -77,25 +95,18 @@ MVSAM CRYPTO PMD driver compilation is disabled by default due to external depen\n Currently there are two driver specific compilation options in\n ``config/common_base`` available:\n \n-- ``CONFIG_RTE_LIBRTE_MVSAM_CRYPTO`` (default ``n``)\n+- ``CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO`` (default: ``n``)\n \n     Toggle compilation of the librte_pmd_mvsam driver.\n \n-- ``CONFIG_RTE_LIBRTE_MVSAM_CRYPTO_DEBUG`` (default ``n``)\n-\n-    Toggle display of debugging messages.\n-\n-For a list of prerequisites please refer to `Prerequisites` section in\n-:ref:`MVPP2 Poll Mode Driver <mvpp2_poll_mode_driver>` guide.\n-\n MVSAM CRYPTO PMD requires MUSDK built with EIP197 support thus following\n extra option must be passed to the library configuration script:\n \n .. code-block:: console\n \n-   --enable-sam\n+   --enable-sam [--enable-sam-statistics] [--enable-sam-debug]\n \n-For `crypto_safexcel.ko` module build instructions please refer\n+For instructions how to build required kernel modules please refer\n to `doc/musdk_get_started.txt`.\n \n Initialization\n@@ -106,17 +117,15 @@ loaded:\n \n .. code-block:: console\n \n-   insmod musdk_uio.ko\n-   insmod mvpp2x_sysfs.ko\n-   insmod mv_pp_uio.ko\n+   insmod musdk_cma.ko\n+   insmod crypto_safexcel.ko rings=0,0\n    insmod mv_sam_uio.ko\n-   insmod crypto_safexcel.ko\n \n The following parameters (all optional) are exported by the driver:\n \n-* max_nb_queue_pairs: maximum number of queue pairs in the device (8 by default).\n-* max_nb_sessions: maximum number of sessions that can be created (2048 by default).\n-* socket_id: socket on which to allocate the device resources on.\n+- ``max_nb_queue_pairs``: maximum number of queue pairs in the device (default: 8 - A8K, 4 - A7K/A3K).\n+- ``max_nb_sessions``: maximum number of sessions that can be created (default: 2048).\n+- ``socket_id``: socket on which to allocate the device resources on.\n \n l2fwd-crypto example application can be used to verify MVSAM CRYPTO PMD\n operation:\n@@ -129,65 +138,3 @@ operation:\n      --auth_op GENERATE --auth_algo sha1-hmac \\\n      --auth_key 10:11:12:13:14:15:16:17:18:19:1a:1b:1c:1d:1e:1f\n \n-Example output:\n-\n-.. code-block:: console\n-\n-   [...]\n-   AAD: at [0x7f253ceb80], len=\n-   P ID 0 configuration ----\n-   Port mode               : KR\n-   MAC status              : disabled\n-   Link status             : link up\n-   Port speed              : 10G\n-   Port duplex             : full\n-   Port: Egress enable tx_port_num=16 qmap=0x1\n-   PORT: Port0 - link\n-   P ID 0 configuration ----\n-   Port mode               : KR\n-   MAC status              : disabled\n-   Link status             : link down\n-   Port speed              : 10G\n-   Port duplex             : full\n-   Port: Egress enable tx_port_num=16 qmap=0x1\n-   Port 0, MAC address: 00:50:43:02:21:20\n-\n-\n-   Checking link statusdone\n-   Port 0 Link Up - speed 0 Mbps - full-duplex\n-   Lcore 0: RX port 0\n-   Allocated session pool on socket 0\n-   eip197: 0:0 registers: paddr: 0xf2880000, vaddr: 0x0x7f56a80000\n-   DMA buffer (131136 bytes) for CDR #0 allocated: paddr = 0xb0585e00, vaddr = 0x7f09384e00\n-   DMA buffer (131136 bytes) for RDR #0 allocated: paddr = 0xb05a5f00, vaddr = 0x7f093a4f00\n-   DMA buffers allocated for 2049 operations. Tokens - 256 bytes\n-   Lcore 0: cryptodev 0\n-   L2FWD: lcore 1 has nothing to do\n-   L2FWD: lcore 2 has nothing to do\n-   L2FWD: lcore 3 has nothing to do\n-   L2FWD: entering main loop on lcore 0\n-   L2FWD:  -- lcoreid=0 portid=0\n-   L2FWD:  -- lcoreid=0 cryptoid=0\n-   Options:-\n-   nportmask: ffffffff\n-   ports per lcore: 1\n-   refresh period : 10000\n-   single lcore mode: disabled\n-   stats_printing: enabled\n-   sessionless crypto: disabled\n-\n-   Crypto chain: Input --> Encrypt --> Auth generate --> Output\n-\n-   ---- Cipher information ---\n-   Algorithm: aes-cbc\n-   Cipher key: at [0x7f56db4e80], len=16\n-   00000000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F | ................\n-   IV: at [0x7f56db4b80], len=16\n-   00000000: 20 F0 63 0E 45 EB 2D 84 72 D4 13 6E 36 B5 AF FE |  .c.E.-.r..n6...\n-\n-   ---- Authentication information ---\n-   Algorithm: sha1-hmac\n-   Auth key: at [0x7f56db4d80], len=16\n-   00000000: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F | ................\n-   IV: at [0x7f56db4a80], len=0\n-   AAD: at [0x7f253ceb80], len=\n",
    "prefixes": [
        "1/3"
    ]
}