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GET /api/patches/44190/?format=api
{ "id": 44190, "url": "http://patches.dpdk.org/api/patches/44190/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-16-git-send-email-ajoseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1536033560-21541-16-git-send-email-ajoseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1536033560-21541-16-git-send-email-ajoseph@caviumnetworks.com", "date": "2018-09-04T03:59:02", "name": "[v2,15/33] crypto/octeontx: add queue pair functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "681b0bd2ed1a86952dab83ec888e99c653c1cc5a", "submitter": { "id": 891, "url": "http://patches.dpdk.org/api/people/891/?format=api", "name": "Anoob Joseph", "email": "ajoseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1536033560-21541-16-git-send-email-ajoseph@caviumnetworks.com/mbox/", "series": [ { "id": 1164, "url": "http://patches.dpdk.org/api/series/1164/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1164", "date": "2018-09-04T03:58:47", "name": "Adding Cavium's OcteonTX crypto PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/1164/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/44190/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/44190/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D636D5F33;\n\tTue, 4 Sep 2018 06:03:28 +0200 (CEST)", "from NAM01-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam01on0082.outbound.protection.outlook.com [104.47.32.82])\n\tby dpdk.org (Postfix) with ESMTP id 4D77B2F4F\n\tfor <dev@dpdk.org>; Tue, 4 Sep 2018 06:03:09 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBYAPR07MB4902.namprd07.prod.outlook.com (2603:10b6:a02:ef::25) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1101.15; Tue, 4 Sep 2018 04:02:48 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=XDVm2Utbs+/rL/oAPdwJ63Ehq8k8eKKhnXnHrxVlfHk=;\n\tb=auLthpT7cT3rex6lpMRQzzwpATm7EVr8VUd1PiiUTs2VYA1j3/L0DCnV+dSAOUTVXe0VlRbo69mB0dOBbW5HVE6NQaD8j9B+bidWcbshB+eKKBnZuHMSqn5bjpE3oLG3wumc7Fht+4PWJAw0IEz/GCn+pM/DSiC0Myi4wSn46RE=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <ajoseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tdev@dpdk.org, Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>", "Date": "Tue, 4 Sep 2018 09:29:02 +0530", "Message-Id": "<1536033560-21541-16-git-send-email-ajoseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BMXPR01CA0023.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:d::33) To BYAPR07MB4902.namprd07.prod.outlook.com\n\t(2603:10b6:a02:ef::25)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e69e54ab-1ca4-4a45-0e10-08d6121b4990", "X-Microsoft-Antispam": "BCL:0; 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"DH4k0j+xOkrfUM0DUyXBxmCokWR/wBgTS6qISbrka27kr1OSsuCHcPTH2pNA1BoC9mEJSoXqwW+O1Vw5s2Oq9ceF4dK/BclS9jl3qVe06jI8sCEsnU0vdrW+QBvHbrdHjw4xucZeFf4vULZ/NHIgzKil6YBM7MGbRJDLM7yZlcEfYqHuY2Qp8Qpt5cibg2tW3cvxPZgZJTt2drtgtyThEgl0dH+jvNdUFp1CaEKyiBGmhFr7udrdzxoRP0CfTXVA9CsvYxkqbb4LQmGYroKUY92R0/SaVRwF7iGyAscqky9Omuol6MAnqE0A3ULUa+VG2YnD5GEW3IIQAxn/mlPvfxFTR7kq/lEmhHMyGihFBZQ=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Sep 2018 04:02:48.8348\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "e69e54ab-1ca4-4a45-0e10-08d6121b4990", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB4902", "Subject": "[dpdk-dev] [PATCH v2 15/33] crypto/octeontx: add queue pair\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\n\nAdding queue pair setup and release functions\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 285 ++++++++++++++++++++++\n drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 8 +\n drivers/crypto/octeontx/otx_cryptodev_ops.c | 82 ++++++-\n 3 files changed, 373 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\nindex d8b8872..fe054e6 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n@@ -1,11 +1,14 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(c) 2018 Cavium, Inc\n */\n+#include <assert.h>\n #include <string.h>\n #include <unistd.h>\n \n #include <rte_branch_prediction.h>\n #include <rte_common.h>\n+#include <rte_errno.h>\n+#include <rte_memzone.h>\n \n #include \"otx_cryptodev_hw_access.h\"\n #include \"otx_cryptodev_mbox.h\"\n@@ -180,6 +183,136 @@ otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)\n \t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n }\n \n+/* Write to VQX_CTL register\n+ */\n+static void\n+otx_cpt_write_vq_ctl(struct cpt_vf *cptvf, bool val)\n+{\n+\tcptx_vqx_ctl_t vqx_ctl;\n+\n+\tvqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_CTL(0, 0));\n+\tvqx_ctl.s.ena = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_CTL(0, 0), vqx_ctl.u);\n+}\n+\n+/* Write to VQX_INPROG register\n+ */\n+static void\n+otx_cpt_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val)\n+{\n+\tcptx_vqx_inprog_t vqx_inprg;\n+\n+\tvqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_INPROG(0, 0));\n+\tvqx_inprg.s.inflight = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_INPROG(0, 0), vqx_inprg.u);\n+}\n+\n+/* Write to VQX_DONE_WAIT NUMWAIT register\n+ */\n+static void\n+otx_cpt_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val)\n+{\n+\tcptx_vqx_done_wait_t vqx_dwait;\n+\n+\tvqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_DONE_WAIT(0, 0));\n+\tvqx_dwait.s.num_wait = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);\n+}\n+\n+/* Write to VQX_DONE_WAIT NUM_WAIT register\n+ */\n+static void\n+otx_cpt_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val)\n+{\n+\tcptx_vqx_done_wait_t vqx_dwait;\n+\n+\tvqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_DONE_WAIT(0, 0));\n+\tvqx_dwait.s.time_wait = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);\n+}\n+\n+/* Write to VQX_SADDR register\n+ */\n+static void\n+otx_cpt_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val)\n+{\n+\tcptx_vqx_saddr_t vqx_saddr;\n+\n+\tvqx_saddr.u = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_SADDR(0, 0), vqx_saddr.u);\n+}\n+\n+static void\n+otx_cpt_vfvq_init(struct cpt_vf *cptvf)\n+{\n+\tuint64_t base_addr = 0;\n+\n+\t/* Disable the VQ */\n+\totx_cpt_write_vq_ctl(cptvf, 0);\n+\n+\t/* Reset the doorbell */\n+\totx_cpt_write_vq_doorbell(cptvf, 0);\n+\t/* Clear inflight */\n+\totx_cpt_write_vq_inprog(cptvf, 0);\n+\n+\t/* Write VQ SADDR */\n+\tbase_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr);\n+\totx_cpt_write_vq_saddr(cptvf, base_addr);\n+\n+\t/* Configure timerhold / coalescence */\n+\totx_cpt_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD);\n+\totx_cpt_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD);\n+\n+\t/* Enable the VQ */\n+\totx_cpt_write_vq_ctl(cptvf, 1);\n+\n+\t/* Flag the VF ready */\n+\tcptvf->flags |= CPT_FLAG_DEVICE_READY;\n+}\n+\n+static int\n+cpt_vq_init(struct cpt_vf *cptvf, uint8_t group)\n+{\n+\tint err;\n+\n+\t/* Convey VQ LEN to PF */\n+\terr = otx_cpt_send_vq_size_msg(cptvf);\n+\tif (err) {\n+\t\tCPT_LOG_ERR(\"%s: PF not responding to QLEN msg\",\n+\t\t\t cptvf->dev_name);\n+\t\terr = -EBUSY;\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* CPT VF device initialization */\n+\totx_cpt_vfvq_init(cptvf);\n+\n+\t/* Send msg to PF to assign currnet Q to required group */\n+\tcptvf->vfgrp = group;\n+\terr = otx_cpt_send_vf_grp_msg(cptvf, group);\n+\tif (err) {\n+\t\tCPT_LOG_ERR(\"%s: PF not responding to VF_GRP msg\",\n+\t\t\t cptvf->dev_name);\n+\t\terr = -EBUSY;\n+\t\tgoto cleanup;\n+\t}\n+\n+\tCPT_LOG_DP_DEBUG(\"%s: %s done\", cptvf->dev_name, __func__);\n+\treturn 0;\n+\n+cleanup:\n+\treturn err;\n+}\n+\n void\n otx_cpt_poll_misc(struct cpt_vf *cptvf)\n {\n@@ -268,6 +401,158 @@ otx_cpt_deinit_device(void *dev)\n }\n \n int\n+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance)\n+{\n+\tint ret = -ENOENT, len, qlen, i;\n+\tint chunk_len, chunks, chunk_size;\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)dev;\n+\tstruct cpt_instance *cpt_instance;\n+\tstruct command_chunk *chunk_head = NULL, *chunk_prev = NULL;\n+\tstruct command_chunk *chunk = NULL;\n+\tuint8_t *mem;\n+\tconst struct rte_memzone *rz;\n+\tuint64_t dma_addr = 0, alloc_len, used_len;\n+\tuint64_t *next_ptr;\n+\tuint64_t pg_sz = sysconf(_SC_PAGESIZE);\n+\n+\tCPT_LOG_DP_DEBUG(\"Initializing cpt resource %s\", cptvf->dev_name);\n+\n+\tcpt_instance = &cptvf->instance;\n+\n+\tmemset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue));\n+\tmemset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue));\n+\n+\t/* Chunks are of fixed size buffers */\n+\tchunks = DEFAULT_CMD_QCHUNKS;\n+\tchunk_len = DEFAULT_CMD_QCHUNK_SIZE;\n+\n+\tqlen = chunks * chunk_len;\n+\t/* Chunk size includes 8 bytes of next chunk ptr */\n+\tchunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE;\n+\n+\t/* For command chunk structures */\n+\tlen = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);\n+\n+\t/* For pending queue */\n+\tlen += qlen * RTE_ALIGN(sizeof(struct rid), 8);\n+\n+\t/* So that instruction queues start as pg size aligned */\n+\tlen = RTE_ALIGN(len, pg_sz);\n+\n+\t/* For Instruction queues */\n+\tlen += chunks * RTE_ALIGN(chunk_size, 128);\n+\n+\t/* Wastage after instruction queues */\n+\tlen = RTE_ALIGN(len, pg_sz);\n+\n+\trz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node,\n+\t\t\t\t\t RTE_MEMZONE_SIZE_HINT_ONLY |\n+\t\t\t\t\t RTE_MEMZONE_256MB,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!rz) {\n+\t\tret = rte_errno;\n+\t\tgoto cleanup;\n+\t}\n+\n+\tmem = rz->addr;\n+\tdma_addr = rz->phys_addr;\n+\talloc_len = len;\n+\n+\tmemset(mem, 0, len);\n+\n+\tcpt_instance->rsvd = (uintptr_t)rz;\n+\n+\t/* Pending queue setup */\n+\tcptvf->pqueue.rid_queue = (struct rid *)mem;\n+\tcptvf->pqueue.soft_qlen = qlen;\n+\tcptvf->pqueue.enq_tail = 0;\n+\tcptvf->pqueue.deq_head = 0;\n+\tcptvf->pqueue.pending_count = 0;\n+\n+\tmem += qlen * RTE_ALIGN(sizeof(struct rid), 8);\n+\tlen -= qlen * RTE_ALIGN(sizeof(struct rid), 8);\n+\tdma_addr += qlen * RTE_ALIGN(sizeof(struct rid), 8);\n+\n+\t/* Alignment wastage */\n+\tused_len = alloc_len - len;\n+\tmem += RTE_ALIGN(used_len, pg_sz) - used_len;\n+\tlen -= RTE_ALIGN(used_len, pg_sz) - used_len;\n+\tdma_addr += RTE_ALIGN(used_len, pg_sz) - used_len;\n+\n+\t/* Init instruction queues */\n+\tchunk_head = &cptvf->cqueue.chead[0];\n+\ti = qlen;\n+\n+\tchunk_prev = NULL;\n+\tfor (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) {\n+\t\tint csize;\n+\n+\t\tchunk = &cptvf->cqueue.chead[i];\n+\t\tchunk->head = mem;\n+\t\tchunk->dma_addr = dma_addr;\n+\n+\t\tcsize = RTE_ALIGN(chunk_size, 128);\n+\t\tmem += csize;\n+\t\tdma_addr += csize;\n+\t\tlen -= csize;\n+\n+\t\tif (chunk_prev) {\n+\t\t\tnext_ptr = (uint64_t *)(chunk_prev->head +\n+\t\t\t\t\t\tchunk_size - 8);\n+\t\t\t*next_ptr = (uint64_t)chunk->dma_addr;\n+\t\t}\n+\t\tchunk_prev = chunk;\n+\t}\n+\t/* Circular loop */\n+\tnext_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8);\n+\t*next_ptr = (uint64_t)chunk_head->dma_addr;\n+\n+\tassert(!len);\n+\n+\tcptvf->qlen = qlen;\n+\t/* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */\n+\tcptvf->qsize = chunk_size / 8;\n+\tcptvf->cqueue.qhead = chunk_head->head;\n+\tcptvf->cqueue.idx = 0;\n+\tcptvf->cqueue.cchunk = 0;\n+\n+\tif (cpt_vq_init(cptvf, group)) {\n+\t\tCPT_LOG_ERR(\"Failed to initialize CPT VQ of device %s\",\n+\t\t\t cptvf->dev_name);\n+\t\tret = -EBUSY;\n+\t\tgoto cleanup;\n+\t}\n+\n+\t*instance = cpt_instance;\n+\n+\tCPT_LOG_DP_DEBUG(\"Crypto device (%s) initialized\", cptvf->dev_name);\n+\n+\treturn 0;\n+cleanup:\n+\trte_memzone_free(rz);\n+\t*instance = NULL;\n+\treturn ret;\n+}\n+\n+int\n+otx_cpt_put_resource(struct cpt_instance *instance)\n+{\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n+\tstruct rte_memzone *rz;\n+\n+\tif (!cptvf) {\n+\t\tCPT_LOG_ERR(\"Invalid CPTVF handle\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tCPT_LOG_DP_DEBUG(\"Releasing cpt device %s\", cptvf->dev_name);\n+\n+\trz = (struct rte_memzone *)instance->rsvd;\n+\trte_memzone_free(rz);\n+\treturn 0;\n+}\n+\n+int\n otx_cpt_start_device(void *dev)\n {\n \tint rc;\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex 7dbc41e..b9a634b 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -15,11 +15,13 @@\n \n /* Flags to indicate the features supported */\n #define CPT_FLAG_VF_DRIVER\t\t(uint16_t)(1 << 3)\n+#define CPT_FLAG_DEVICE_READY\t\t(uint16_t)(1 << 4)\n \n #define CPT_INTR_POLL_INTERVAL_MS\t(50)\n \n /* Default command queue length */\n #define DEFAULT_CMD_QCHUNKS\t2\n+#define DEFAULT_CMD_QCHUNK_SIZE\t\t1023\n \n #define CPT_CSR_REG_BASE(cpt)\t\t((cpt)->reg_base)\n \n@@ -152,6 +154,12 @@ int\n otx_cpt_deinit_device(void *dev);\n \n int\n+otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance);\n+\n+int\n+otx_cpt_put_resource(struct cpt_instance *instance);\n+\n+int\n otx_cpt_start_device(void *cptvf);\n \n void\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c\nindex 2bbf82f..e6b2ed9 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c\n@@ -28,6 +28,11 @@ static struct rte_mempool *otx_cpt_meta_pool;\n static int otx_cpt_op_mlen;\n static int otx_cpt_op_sb_mlen;\n \n+/* Forward declarations */\n+\n+static int\n+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id);\n+\n /*\n * Initializes global variables used by fast-path code\n *\n@@ -136,9 +141,16 @@ static int\n otx_cpt_dev_close(struct rte_cryptodev *c_dev)\n {\n \tvoid *cptvf = c_dev->data->dev_private;\n+\tint i, ret;\n \n \tCPT_PMD_INIT_FUNC_TRACE();\n \n+\tfor (i = 0; i < c_dev->data->nb_queue_pairs; i++) {\n+\t\tret = otx_cpt_que_pair_release(c_dev, i);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \totx_cpt_periodic_alarm_stop(cptvf);\n \totx_cpt_deinit_device(cptvf);\n \n@@ -173,6 +185,72 @@ otx_cpt_stats_reset(struct rte_cryptodev *dev __rte_unused)\n \tCPT_PMD_INIT_FUNC_TRACE();\n }\n \n+static int\n+otx_cpt_que_pair_setup(struct rte_cryptodev *dev,\n+\t\t uint16_t que_pair_id,\n+\t\t const struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t int socket_id __rte_unused,\n+\t\t struct rte_mempool *session_pool __rte_unused)\n+{\n+\tvoid *cptvf = dev->data->dev_private;\n+\tstruct cpt_instance *instance = NULL;\n+\tstruct rte_pci_device *pci_dev;\n+\tint ret = -1;\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\tif (dev->data->queue_pairs[que_pair_id] != NULL) {\n+\t\tret = otx_cpt_que_pair_release(dev, que_pair_id);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tif (qp_conf->nb_descriptors > DEFAULT_CMD_QLEN) {\n+\t\tCPT_LOG_INFO(\"Number of descriptors too big %d, using default \"\n+\t\t\t \"queue length of %d\", qp_conf->nb_descriptors,\n+\t\t\t DEFAULT_CMD_QLEN);\n+\t}\n+\n+\tpci_dev = RTE_DEV_TO_PCI(dev->device);\n+\n+\tif (pci_dev->mem_resource[0].addr == NULL) {\n+\t\tCPT_PMD_DRV_LOG(ERR, \"PCI mem address null\");\n+\t\treturn -EIO;\n+\t}\n+\n+\tret = otx_cpt_get_resource(cptvf, 0, &instance);\n+\tif (ret != 0) {\n+\t\tCPT_LOG_ERR(\"Error getting instance handle from device %s : \"\n+\t\t\t \"ret = %d\", dev->data->name, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tinstance->queue_id = que_pair_id;\n+\tdev->data->queue_pairs[que_pair_id] = instance;\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx_cpt_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)\n+{\n+\tstruct cpt_instance *instance = dev->data->queue_pairs[que_pair_id];\n+\tint ret;\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\tret = otx_cpt_put_resource(instance);\n+\tif (ret != 0) {\n+\t\tCPT_PMD_DRV_LOG(ERR, \"Error putting instance handle\"\n+\t\t\t \" of device %s : ret = %d\\n\", dev->data->name, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tdev->data->queue_pairs[que_pair_id] = NULL;\n+\n+\treturn 0;\n+}\n+\n static struct rte_cryptodev_ops cptvf_ops = {\n \t/* Device related operations */\n \t.dev_configure = otx_cpt_dev_config,\n@@ -183,8 +261,8 @@ static struct rte_cryptodev_ops cptvf_ops = {\n \n \t.stats_get = otx_cpt_stats_get,\n \t.stats_reset = otx_cpt_stats_reset,\n-\t.queue_pair_setup = NULL,\n-\t.queue_pair_release = NULL,\n+\t.queue_pair_setup = otx_cpt_que_pair_setup,\n+\t.queue_pair_release = otx_cpt_que_pair_release,\n \t.queue_pair_count = NULL,\n \n \t/* Crypto related operations */\n", "prefixes": [ "v2", "15/33" ] }