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GET /api/patches/43531/?format=api
{ "id": 43531, "url": "http://patches.dpdk.org/api/patches/43531/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1533222566-17685-3-git-send-email-tomaszx.jozwiak@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1533222566-17685-3-git-send-email-tomaszx.jozwiak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1533222566-17685-3-git-send-email-tomaszx.jozwiak@intel.com", "date": "2018-08-02T15:09:26", "name": "[2/2] common/qat: fix offset greater than first sgl segment", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2607f10db3311bcc2d1a2ad12138929b9fdc60da", "submitter": { "id": 949, "url": "http://patches.dpdk.org/api/people/949/?format=api", "name": "Tomasz Jozwiak", "email": "tomaszx.jozwiak@intel.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1533222566-17685-3-git-send-email-tomaszx.jozwiak@intel.com/mbox/", "series": [ { "id": 881, "url": "http://patches.dpdk.org/api/series/881/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=881", "date": "2018-08-02T15:09:24", "name": "common/qat: handle offset greater than first sgl segment", "version": 1, "mbox": "http://patches.dpdk.org/series/881/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/43531/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/43531/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 51FC81B4E4;\n\tThu, 2 Aug 2018 17:09:37 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id 1F0321B4D6\n\tfor <dev@dpdk.org>; Thu, 2 Aug 2018 17:09:32 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t02 Aug 2018 08:09:32 -0700", "from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.43])\n\tby fmsmga001.fm.intel.com with ESMTP; 02 Aug 2018 08:09:31 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,436,1526367600\"; d=\"scan'208\";a=\"77750120\"", "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>", "To": "pablo.de.lara.guarch@intel.com, dev@dpdk.org, fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com", "Date": "Thu, 2 Aug 2018 17:09:26 +0200", "Message-Id": "<1533222566-17685-3-git-send-email-tomaszx.jozwiak@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1533222566-17685-1-git-send-email-tomaszx.jozwiak@intel.com>", "References": "<1533222566-17685-1-git-send-email-tomaszx.jozwiak@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/2] common/qat: fix offset greater than first\n\tsgl segment", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch fixes sgl filling to handle offset\ngreater than first sgl segment\n\nFixes: 1947bd18580b (\"compress/qat: support scatter-gather buffers\")\n\nSigned-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>\nAcked-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n drivers/common/qat/qat_common.c | 77 +++++++++++++++++------------------------\n drivers/common/qat/qat_common.h | 2 +-\n drivers/compress/qat/qat_comp.c | 11 +++---\n drivers/crypto/qat/qat_sym.c | 18 +++++-----\n 4 files changed, 48 insertions(+), 60 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_common.c b/drivers/common/qat/qat_common.c\nindex bc04c07..4753866 100644\n--- a/drivers/common/qat/qat_common.c\n+++ b/drivers/common/qat/qat_common.c\n@@ -7,79 +7,66 @@\n #include \"qat_logs.h\"\n \n int\n-qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,\n+qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,\n \t\tvoid *list_in, uint32_t data_len,\n \t\tconst uint16_t max_segs)\n {\n-\tint nr = 1;\n+\tint res = -EINVAL;\n+\tuint32_t buf_len, nr;\n \tstruct qat_sgl *list = (struct qat_sgl *)list_in;\n-\t/* buf_start allows the first buffer to start at an address before or\n-\t * after the mbuf data start. It's used to either optimally align the\n-\t * dma to 64 or to start dma from an offset.\n-\t */\n-\tuint32_t buf_len;\n-\tuint32_t first_buf_len = rte_pktmbuf_data_len(buf) +\n-\t\t\t(rte_pktmbuf_mtophys(buf) - buf_start);\n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n \tuint8_t *virt_addr[max_segs];\n-\tvirt_addr[0] = rte_pktmbuf_mtod(buf, uint8_t*) +\n-\t\t\t(rte_pktmbuf_mtophys(buf) - buf_start);\n #endif\n \n-\tlist->buffers[0].addr = buf_start;\n-\tlist->buffers[0].resrvd = 0;\n-\tlist->buffers[0].len = first_buf_len;\n-\n-\tif (data_len <= first_buf_len) {\n-\t\tlist->num_bufs = nr;\n-\t\tlist->buffers[0].len = data_len;\n-\t\tgoto sgl_end;\n-\t}\n-\n-\tbuf = buf->next;\n-\tbuf_len = first_buf_len;\n-\twhile (buf) {\n-\t\tif (unlikely(nr == max_segs)) {\n-\t\t\tQAT_DP_LOG(ERR, \"Exceeded max segments in QAT SGL (%u)\",\n-\t\t\t\t\tmax_segs);\n-\t\t\treturn -EINVAL;\n+\tfor (nr = buf_len = 0; buf && nr < max_segs; buf = buf->next) {\n+\t\tif (offset >= rte_pktmbuf_data_len(buf)) {\n+\t\t\toffset -= rte_pktmbuf_data_len(buf);\n+\t\t\tcontinue;\n \t\t}\n \n-\t\tlist->buffers[nr].len = rte_pktmbuf_data_len(buf);\n+\t\tlist->buffers[nr].len = rte_pktmbuf_data_len(buf) - offset;\n \t\tlist->buffers[nr].resrvd = 0;\n-\t\tlist->buffers[nr].addr = rte_pktmbuf_mtophys(buf);\n+\t\tlist->buffers[nr].addr = rte_pktmbuf_iova_offset(buf, offset);\n+\n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t\tvirt_addr[nr] = rte_pktmbuf_mtod(buf, uint8_t*);\n+\t\tvirt_addr[nr] = rte_pktmbuf_mtod_offset(buf, uint8_t*, offset);\n #endif\n+\t\toffset = 0;\n \t\tbuf_len += list->buffers[nr].len;\n-\t\tbuf = buf->next;\n \n \t\tif (buf_len >= data_len) {\n-\t\t\tlist->buffers[nr].len -=\n-\t\t\t\tbuf_len - data_len;\n-\t\t\tbuf = NULL;\n+\t\t\tlist->buffers[nr].len -= buf_len - data_len;\n+\t\t\tres = 0;\n+\t\t\tbreak;\n \t\t}\n \t\t++nr;\n \t}\n-\tlist->num_bufs = nr;\n \n-sgl_end:\n+\tif (unlikely(res != 0)) {\n+\t\tif (nr == max_segs) {\n+\t\t\tQAT_DP_LOG(ERR, \"Exceeded max segments in QAT SGL (%u)\",\n+\t\t\t\t max_segs);\n+\t\t} else {\n+\t\t\tQAT_DP_LOG(ERR, \"Mbuf chain is too short\");\n+\t\t}\n+\t} else {\n+\n+\t\tlist->num_bufs = ++nr;\n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n-\t{\n-\t\tuint16_t i;\n \t\tQAT_DP_LOG(INFO, \"SGL with %d buffers:\", list->num_bufs);\n-\t\tfor (i = 0; i < list->num_bufs; i++) {\n+\t\tfor (nr = 0; nr < list->num_bufs; nr++) {\n \t\t\tQAT_DP_LOG(INFO,\n \t\t\t\t\"QAT SGL buf %d, len = %d, iova = 0x%012\"PRIx64,\n-\t\t\t\ti, list->buffers[i].len,\n-\t\t\t\tlist->buffers[i].addr);\n+\t\t\t\t nr, list->buffers[nr].len,\n+\t\t\t\t list->buffers[nr].addr);\n \t\t\tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat SGL\",\n-\t\t\t\t\tvirt_addr[i], list->buffers[i].len);\n+\t\t\t\t\t virt_addr[nr],\n+\t\t\t\t\t list->buffers[nr].len);\n \t\t}\n-\t}\n #endif\n+\t}\n \n-\treturn 0;\n+\treturn res;\n }\n \n void qat_stats_get(struct qat_pci_device *dev,\ndiff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex b26aa26..d4bef53 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -65,7 +65,7 @@ struct qat_common_stats {\n struct qat_pci_device;\n \n int\n-qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,\n+qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset,\n \t\tvoid *list_in, uint32_t data_len,\n \t\tconst uint16_t max_segs);\n void\ndiff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c\nindex 522edfc..38c8a5b 100644\n--- a/drivers/compress/qat/qat_comp.c\n+++ b/drivers/compress/qat/qat_comp.c\n@@ -53,25 +53,24 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg,\n \n \t\tICP_QAT_FW_COMN_PTR_TYPE_SET(comp_req->comn_hdr.comn_req_flags,\n \t\t\t\tQAT_COMN_PTR_TYPE_SGL);\n+\n \t\tret = qat_sgl_fill_array(op->m_src,\n-\t\t\t\trte_pktmbuf_mtophys_offset(op->m_src,\n-\t\t\t\t\t\t\top->src.offset),\n+\t\t\t\top->src.offset,\n \t\t\t\t&cookie->qat_sgl_src,\n \t\t\t\top->src.length,\n \t\t\t\tRTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);\n \t\tif (ret) {\n-\t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill sgl array\");\n+\t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill source sgl array\");\n \t\t\treturn ret;\n \t\t}\n \n \t\tret = qat_sgl_fill_array(op->m_dst,\n-\t\t\t\trte_pktmbuf_mtophys_offset(op->m_dst,\n-\t\t\t\t\t\t\top->dst.offset),\n+\t\t\t\top->dst.offset,\n \t\t\t\t&cookie->qat_sgl_dst,\n \t\t\t\tcomp_req->comp_pars.out_buffer_sz,\n \t\t\t\tRTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS);\n \t\tif (ret) {\n-\t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill sgl array\");\n+\t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill dest. sgl array\");\n \t\t\treturn ret;\n \t\t}\n \ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 8273968..10cdf2e 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -494,10 +494,11 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \n \t\tICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,\n \t\t\t\tQAT_COMN_PTR_TYPE_SGL);\n-\t\tret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,\n-\t\t\t\t\t&cookie->qat_sgl_src,\n-\t\t\t\t\tqat_req->comn_mid.src_length,\n-\t\t\t\t\tQAT_SYM_SGL_MAX_NUMBER);\n+\t\tret = qat_sgl_fill_array(op->sym->m_src,\n+\t\t (int64_t)(src_buf_start - rte_pktmbuf_iova(op->sym->m_src)),\n+\t\t &cookie->qat_sgl_src,\n+\t\t qat_req->comn_mid.src_length,\n+\t\t QAT_SYM_SGL_MAX_NUMBER);\n \n \t\tif (unlikely(ret)) {\n \t\t\tQAT_DP_LOG(ERR, \"QAT PMD Cannot fill sgl array\");\n@@ -510,10 +511,11 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\t\tcookie->qat_sgl_src_phys_addr;\n \t\telse {\n \t\t\tret = qat_sgl_fill_array(op->sym->m_dst,\n-\t\t\t\t\t\t dst_buf_start,\n-\t\t\t\t\t\t &cookie->qat_sgl_dst,\n-\t\t\t\t\t\t qat_req->comn_mid.dst_length,\n-\t\t\t\t\t\t QAT_SYM_SGL_MAX_NUMBER);\n+\t\t\t\t(int64_t)(dst_buf_start -\n+\t\t\t\t\t rte_pktmbuf_iova(op->sym->m_dst)),\n+\t\t\t\t &cookie->qat_sgl_dst,\n+\t\t\t\t qat_req->comn_mid.dst_length,\n+\t\t\t\t QAT_SYM_SGL_MAX_NUMBER);\n \n \t\t\tif (unlikely(ret)) {\n \t\t\t\tQAT_DP_LOG(ERR, \"QAT PMD can't fill sgl array\");\n", "prefixes": [ "2/2" ] }