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GET /api/patches/43359/?format=api
{ "id": 43359, "url": "http://patches.dpdk.org/api/patches/43359/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180725170456.3319-2-Ashish.Gupta@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180725170456.3319-2-Ashish.Gupta@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180725170456.3319-2-Ashish.Gupta@caviumnetworks.com", "date": "2018-07-25T17:04:51", "name": "[v4,1/6] compress/octeontx: add octeontx zip PMD", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b32f8b3fb2c220790a4b6988552e304e56fc0f92", "submitter": { "id": 1089, "url": "http://patches.dpdk.org/api/people/1089/?format=api", "name": "Ashish Gupta", "email": "Ashish.Gupta@caviumnetworks.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180725170456.3319-2-Ashish.Gupta@caviumnetworks.com/mbox/", "series": [ { "id": 773, "url": "http://patches.dpdk.org/api/series/773/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=773", "date": "2018-07-25T17:04:50", "name": "compress: add Octeontx ZIP compression PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/773/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/43359/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/43359/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 991CF326C;\n\tWed, 25 Jul 2018 18:43:03 +0200 (CEST)", "from NAM01-BN3-obe.outbound.protection.outlook.com\n\t(mail-bn3nam01hn0200.outbound.protection.outlook.com [104.47.33.200])\n\tby dpdk.org (Postfix) with ESMTP id 538FD3257\n\tfor <dev@dpdk.org>; Wed, 25 Jul 2018 18:43:01 +0200 (CEST)", "from hyd1agupta-dt.caveonetworks.com (115.113.156.2) by\n\tCY4PR07MB3062.namprd07.prod.outlook.com (2603:10b6:903:d1::15) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.973.21; Wed, 25 Jul 2018 16:42:57 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=UPu7PzbYasOi78w3HJnM/90pffLI21FbNS5O9DLQZu8=;\n\tb=ZCJTNT9eTKMCeizHx39fgzbthjPracoGc9Wkjw0hxaicqwO2cVf7Zg1f37TA9E5Ef1XpaDcQKwWUIp81Lsxw66XWE2j7DONbRZn8fZGLeTUMbiIad6dayDLXUUQmL8UxsyCNa8Y83tvdZVtI7yf/8oVGTLkMSxm2XumKQyKHfSs=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Ashish.Gupta@cavium.com; ", "From": "Ashish Gupta <Ashish.Gupta@caviumnetworks.com>", "To": "pablo.de.lara.guarch@intel.com", "Cc": "dev@dpdk.org, narayanaprasad.athreya@cavium.com,\n\tmahipal.challa@cavium.com, \n\tfiona.trahe@intel.com, Sunila Sahu <sunila.sahu@caviumnetworks.com>, \n\tShally Verma <shally.verma@caviumnetworks.com>", "Date": "Wed, 25 Jul 2018 22:34:51 +0530", "Message-Id": "<20180725170456.3319-2-Ashish.Gupta@caviumnetworks.com>", "X-Mailer": "git-send-email 2.14.3", "In-Reply-To": "<20180725170456.3319-1-Ashish.Gupta@caviumnetworks.com>", "References": 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"SFV:SPM;\n\tSFS:(10009020)(396003)(376002)(346002)(136003)(366004)(39860400002)(189003)(199004)(2616005)(956004)(446003)(25786009)(69596002)(6486002)(2351001)(53416004)(81156014)(8676002)(11346002)(47776003)(105586002)(4326008)(66066001)(81166006)(486006)(8936002)(476003)(2361001)(26005)(186003)(16526019)(42882007)(7736002)(106356001)(68736007)(386003)(305945005)(6506007)(53946003)(50226002)(107886003)(6512007)(51416003)(48376002)(52116002)(54906003)(72206003)(14444005)(50466002)(6666003)(97736004)(6916009)(5660300001)(478600001)(76176011)(16586007)(53936002)(3846002)(36756003)(2906002)(6116002)(55236004)(1076002)(316002)(59010400001);\n\tDIR:OUT; SFP:1501; SCL:5; SRVR:CY4PR07MB3062;\n\tH:hyd1agupta-dt.caveonetworks.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "zrQSV/KTYSIK/Dbd5Bk4WMLHZ6K50vBG0lQJBne6ggFzRIMWvYKyamT/yplKBGDHvUFco+1NrX6f9Dz+nPXsj1wO1kg7n+pWRkszQHRcjahgd96/EgA1PicMhyVCF2YXMw2R5MCttE4dIiz8HJqeGJW18SXmkNMTA5+oAXz4qBnU9H1xq1EfEHiOeXRRpQd+9xDvAghvLlnvwBrNXyWdeiDo7FLQeOnDq2lUNzCVzl+8yaf+G8Pg0JhayCnAKVcuQUUWtHYX9vT8VN6n1/3JAT/7R9DgxCVNWx6FL3J0d4uutg3W/ofmCSpu+9ybq/GvyHQr1RreAwuFsp1nMeoVfHu9AOWdyAiwirU3+fG5w/7xrvP6z5ey6gtiDjJpLsXCtgLlGIv3agPg3sEKUy4/DWzTK7nMRQ2fg+uJlbbL6zL6Af1cvcV0Y5KruP2pVZhHF51TfTPhSv2L53E+UJVJAqiGw3QNBidKMVNr7HivdNcBR5uACRjAPXAZmF+yFjwG+69NMDTFuRgLnaX3OobXVmCFrYF/QYqcvhrhGyil70PhtKu6Eo1S9hNgIA0kld+jGquhNO4EchsLijhFFrz/XMeV6j077V+zaQTDj+qUVvQlT5/YdguHf9m8b9RV2Lu2dXizRt/rQH4lCjAOBrcLP1lnfFwlBCKyaCzXepOjaZGMN/FiacumRolPCb54g69IefQfrpbmjW1M0QOYlH0b3g==", "SpamDiagnosticOutput": "1:22", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Jul 2018 16:42:57.0426\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "44c93e92-0138-45d9-5070-08d5f24dae45", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR07MB3062", "Subject": "[dpdk-dev] [PATCH v4 1/6] compress/octeontx: add octeontx zip PMD", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunila Sahu <sunila.sahu@caviumnetworks.com>\n\nOctentx zipvf PMD provides hardware acceleration for\ndeflate and lzs compression and decompression operations\nusing Octeontx zip co-processor, which provide 8\nvirtualized zip devices.\n\nThis patch add basic initialization routine to register zip VFs\nto compressdev library.\n\nSigned-off-by: Ashish Gupta <Ashish.Gupta@caviumnetworks.com>\nSigned-off-by: Shally Verma <shally.verma@caviumnetworks.com>\nSigned-off-by: Sunila Sahu <sunila.sahu@caviumnetworks.com>\n---\n MAINTAINERS | 3 +\n config/common_base | 5 +\n drivers/compress/Makefile | 1 +\n drivers/compress/meson.build | 2 +-\n drivers/compress/octeontx/Makefile | 30 +\n drivers/compress/octeontx/include/zip_regs.h | 711 +++++++++++++++++++++\n drivers/compress/octeontx/meson.build | 9 +\n drivers/compress/octeontx/otx_zip.c | 62 ++\n drivers/compress/octeontx/otx_zip.h | 113 ++++\n drivers/compress/octeontx/otx_zip_pmd.c | 118 ++++\n .../octeontx/rte_pmd_octeontx_compress_version.map | 3 +\n mk/rte.app.mk | 1 +\n 12 files changed, 1057 insertions(+), 1 deletion(-)", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 7e3c450..16cbfd0 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -855,6 +855,9 @@ F: drivers/crypto/zuc/\n F: doc/guides/cryptodevs/zuc.rst\n F: doc/guides/cryptodevs/features/zuc.ini\n \n+Cavium OCTEONTX zipvf\n+M: Ashish Gupta <ashish.gupta@cavium.com>\n+F: drivers/compress/octeontx\n \n Compression Drivers\n -------------------\ndiff --git a/config/common_base b/config/common_base\nindex 662da4d..4bcbaf9 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -578,6 +578,11 @@ CONFIG_RTE_COMPRESS_MAX_DEVS=64\n CONFIG_RTE_COMPRESSDEV_TEST=n\n \n #\n+# Compile PMD for Octeontx ZIPVF compression device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF=y\n+\n+#\n # Compile PMD for ISA-L compression device\n #\n CONFIG_RTE_LIBRTE_PMD_ISAL=n\ndiff --git a/drivers/compress/Makefile b/drivers/compress/Makefile\nindex 1f159a5..af26060 100644\n--- a/drivers/compress/Makefile\n+++ b/drivers/compress/Makefile\n@@ -5,5 +5,6 @@ include $(RTE_SDK)/mk/rte.vars.mk\n \n DIRS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += isal\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_ZLIB) += zlib\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += octeontx\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/compress/meson.build b/drivers/compress/meson.build\nindex d2ca8fc..0b428ba 100644\n--- a/drivers/compress/meson.build\n+++ b/drivers/compress/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2018 Intel Corporation\n \n-drivers = ['isal', 'qat', 'zlib']\n+drivers = ['isal', 'qat', 'zlib', 'octeontx']\n \n std_deps = ['compressdev'] # compressdev pulls in all other needed deps\n config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'\ndiff --git a/drivers/compress/octeontx/Makefile b/drivers/compress/octeontx/Makefile\nnew file mode 100644\nindex 0000000..f34424c\n--- /dev/null\n+++ b/drivers/compress/octeontx/Makefile\n@@ -0,0 +1,30 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Cavium, Inc\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_octeontx_zip.a\n+\n+# library version\n+LIBABIVER := 1\n+\n+# build flags\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -O3\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+CFLAGS += -I$(RTE_SDK)/drivers/compress/octeontx/include\n+\n+# external library include paths\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_compressdev\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+\n+# library source files\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += otx_zip_pmd.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += otx_zip.c\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_octeontx_compress_version.map\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/compress/octeontx/include/zip_regs.h b/drivers/compress/octeontx/include/zip_regs.h\nnew file mode 100644\nindex 0000000..1e74db4\n--- /dev/null\n+++ b/drivers/compress/octeontx/include/zip_regs.h\n@@ -0,0 +1,711 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _RTE_OCTEONTX_ZIP_REGS_H_\n+#define _RTE_OCTEONTX_ZIP_REGS_H_\n+\n+\n+/**\n+ * Enumeration zip_cc\n+ *\n+ * ZIP compression coding Enumeration\n+ * Enumerates ZIP_INST_S[CC].\n+ */\n+enum {\n+\tZIP_CC_DEFAULT = 0,\n+\tZIP_CC_DYN_HUFF,\n+\tZIP_CC_FIXED_HUFF,\n+\tZIP_CC_LZS\n+} zip_cc;\n+\n+/**\n+ * Register (NCB) zip_vq#_ena\n+ *\n+ * ZIP VF Queue Enable Register\n+ * If a queue is disabled, ZIP CTL stops fetching instructions from the queue.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct zip_vqx_ena_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_1_63 : 63;\n+\t\tuint64_t ena : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t ena : 1;\n+\t\tuint64_t reserved_1_63 : 63;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_vqx_ena_s cn; */\n+} zip_vqx_ena_t;\n+\n+/**\n+ * Register (NCB) zip_vq#_sbuf_addr\n+ *\n+ * ZIP VF Queue Starting Buffer Address Registers\n+ * These registers set the buffer parameters for the instruction queues.\n+ * When quiescent (i.e.\n+ * outstanding doorbell count is 0), it is safe to rewrite this register\n+ * to effectively reset the\n+ * command buffer state machine.\n+ * These registers must be programmed after software programs the\n+ * corresponding ZIP_QUE()_SBUF_CTL.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct zip_vqx_sbuf_addr_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_49_63 : 15;\n+\t\tuint64_t ptr : 42;\n+\t\tuint64_t off : 7;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t off : 7;\n+\t\tuint64_t ptr : 42;\n+\t\tuint64_t reserved_49_63 : 15;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_vqx_sbuf_addr_s cn; */\n+} zip_vqx_sbuf_addr_t;\n+\n+/**\n+ * Register (NCB) zip_que#_doorbell\n+ *\n+ * ZIP Queue Doorbell Registers\n+ * Doorbells for the ZIP instruction queues.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct zip_quex_doorbell_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\tuint64_t dbell_cnt : 20;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t dbell_cnt : 20;\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_quex_doorbell_s cn; */\n+} zip_quex_doorbell_t;\n+\n+/**\n+ * Structure zip_nptr_s\n+ *\n+ * ZIP Instruction Next-Chunk-Buffer Pointer (NPTR) Structure\n+ * This structure is used to chain all the ZIP instruction buffers\n+ * together. ZIP instruction buffers are managed\n+ * (allocated and released) by software.\n+ */\n+union zip_nptr_s {\n+\tuint64_t u;\n+\tstruct zip_nptr_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t addr : 64;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t addr : 64;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_nptr_s_s cn83xx; */\n+};\n+\n+/**\n+ * generic ptr address\n+ */\n+union zip_zptr_addr_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u;\n+\t/** generic ptr address */\n+\tstruct {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t addr : 64;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t addr : 64;\n+#endif /* Word 0 - End */\n+\t} s;\n+};\n+\n+/**\n+ * generic ptr ctl\n+ */\n+union zip_zptr_ctl_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u;\n+\t/** generic ptr ctl */\n+\tstruct {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\tuint64_t reserved_112_127 : 16;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\tuint64_t fw : 1;\n+\t\tuint64_t nc : 1;\n+\t\tuint64_t data_be : 1;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t data_be : 1;\n+\t\tuint64_t nc : 1;\n+\t\tuint64_t fw : 1;\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t reserved_112_127 : 16;\n+#endif /* Word 1 - End */\n+\t} s;\n+\n+};\n+\n+/**\n+ * Structure zip_inst_s\n+ *\n+ * ZIP Instruction Structure\n+ * Each ZIP instruction has 16 words (they are called IWORD0 to IWORD15\n+ * within the structure).\n+ */\n+union zip_inst_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u[16];\n+\t/** ZIP Instruction Structure */\n+\tstruct zip_inst_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** Done interrupt */\n+\t\tuint64_t doneint : 1;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\t/** Total output length */\n+\t\tuint64_t totaloutputlength : 24;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\t/** EXNUM */\n+\t\tuint64_t exn : 3;\n+\t\t/** HASH IV */\n+\t\tuint64_t iv : 1;\n+\t\t/** EXBITS */\n+\t\tuint64_t exbits : 7;\n+\t\t/** Hash more-in-file */\n+\t\tuint64_t hmif : 1;\n+\t\t/** Hash Algorithm and enable */\n+\t\tuint64_t halg : 3;\n+\t\t/** Sync flush*/\n+\t\tuint64_t sf : 1;\n+\t\t/** Compression speed/storage */\n+\t\tuint64_t ss : 2;\n+\t\t/** Compression coding */\n+\t\tuint64_t cc : 2;\n+\t\t/** End of input data */\n+\t\tuint64_t ef : 1;\n+\t\t/** Beginning of file */\n+\t\tuint64_t bf : 1;\n+\t\t// uint64_t reserved_3_4 : 2;\n+\t\t/** Comp/decomp operation */\n+\t\tuint64_t op : 2;\n+\t\t/** Data sactter */\n+\t\tuint64_t ds : 1;\n+\t\t/** Data gather */\n+\t\tuint64_t dg : 1;\n+\t\t/** History gather */\n+\t\tuint64_t hg : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t hg : 1;\n+\t\tuint64_t dg : 1;\n+\t\tuint64_t ds : 1;\n+\t\t//uint64_t reserved_3_4 : 2;\n+\t\tuint64_t op : 2;\n+\t\tuint64_t bf : 1;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t cc : 2;\n+\t\tuint64_t ss : 2;\n+\t\tuint64_t sf : 1;\n+\t\tuint64_t halg : 3;\n+\t\tuint64_t hmif : 1;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t iv : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\tuint64_t totaloutputlength : 24;\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\tuint64_t doneint : 1;\n+\n+#endif /* Word 0 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** History length */\n+\t\tuint64_t historylength : 16;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\t/** adler/crc32 checksum*/\n+\t\tuint64_t adlercrc32 : 32;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t adlercrc32 : 32;\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\tuint64_t historylength : 16;\n+#endif /* Word 1 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */\n+\t\t/** Decompression Context Pointer Address */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#else /* Word 2 - Little Endian */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#endif /* Word 2 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Decompression Context Pointer Control */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#else /* Word 3 - Little Endian */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#endif /* Word 3 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Decompression history pointer address */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#else /* Word 4 - Little Endian */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#endif /* Word 4 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Decompression history pointer control */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#else /* Word 5 - Little Endian */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#endif /* Word 5 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Input and compression history pointer address */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#else /* Word 6 - Little Endian */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#endif /* Word 6 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Input and compression history pointer control */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#else /* Word 7 - Little Endian */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#endif /* Word 7 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Output pointer address */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#else /* Word 8 - Little Endian */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#endif /* Word 8 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Output pointer control */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#else /* Word 9 - Little Endian */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#endif /* Word 9 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Result pointer address */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#else /* Word 10 - Little Endian */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#endif /* Word 10 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Result pointer control */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#else /* Word 11 - Little Endian */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#endif /* Word 11 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 12 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_812_831 : 20;\n+\t\t/** SSO guest group */\n+\t\tuint64_t ggrp : 10;\n+\t\t/** SSO tag type */\n+\t\tuint64_t tt : 2;\n+\t\t/** SSO tag */\n+\t\tuint64_t tag : 32;\n+#else /* Word 12 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t ggrp : 10;\n+\t\tuint64_t reserved_812_831 : 20;\n+#endif /* Word 12 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 13 - Big Endian */\n+\t\t/** Work queue entry pointer */\n+\t\tuint64_t wq_ptr : 64;\n+#else /* Word 13 - Little Endian */\n+\t\tuint64_t wq_ptr : 64;\n+#endif /* Word 13 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** reserved */\n+\t\tuint64_t reserved_896_959 : 64;\n+#else /* Word 14 - Little Endian */\n+\t\tuint64_t reserved_896_959 : 64;\n+#endif /* Word 14 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Hash structure pointer */\n+\t\tuint64_t hash_ptr : 64;\n+#else /* Word 15 - Little Endian */\n+\t\tuint64_t hash_ptr : 64;\n+#endif /* Word 15 - End */\n+\t} /** ZIP 88xx Instruction Structure */zip88xx;\n+\n+\t/** ZIP Instruction Structure */\n+\tstruct zip_inst_s_cn83xx {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** Done interrupt */\n+\t\tuint64_t doneint : 1;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\t/** Total output length */\n+\t\tuint64_t totaloutputlength : 24;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\t/** EXNUM */\n+\t\tuint64_t exn : 3;\n+\t\t/** HASH IV */\n+\t\tuint64_t iv : 1;\n+\t\t/** EXBITS */\n+\t\tuint64_t exbits : 7;\n+\t\t/** Hash more-in-file */\n+\t\tuint64_t hmif : 1;\n+\t\t/** Hash Algorithm and enable */\n+\t\tuint64_t halg : 3;\n+\t\t/** Sync flush*/\n+\t\tuint64_t sf : 1;\n+\t\t/** Compression speed/storage */\n+\t\tuint64_t ss : 2;\n+\t\t/** Compression coding */\n+\t\tuint64_t cc : 2;\n+\t\t/** End of input data */\n+\t\tuint64_t ef : 1;\n+\t\t/** Beginning of file */\n+\t\tuint64_t bf : 1;\n+\t\t/** Comp/decomp operation */\n+\t\tuint64_t op : 2;\n+\t\t/** Data sactter */\n+\t\tuint64_t ds : 1;\n+\t\t/** Data gather */\n+\t\tuint64_t dg : 1;\n+\t\t/** History gather */\n+\t\tuint64_t hg : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t hg : 1;\n+\t\tuint64_t dg : 1;\n+\t\tuint64_t ds : 1;\n+\t\tuint64_t op : 2;\n+\t\tuint64_t bf : 1;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t cc : 2;\n+\t\tuint64_t ss : 2;\n+\t\tuint64_t sf : 1;\n+\t\tuint64_t halg : 3;\n+\t\tuint64_t hmif : 1;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t iv : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\tuint64_t totaloutputlength : 24;\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\tuint64_t doneint : 1;\n+#endif /* Word 0 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** History length */\n+\t\tuint64_t historylength : 16;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\t/** adler/crc32 checksum*/\n+\t\tuint64_t adlercrc32 : 32;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t adlercrc32 : 32;\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\tuint64_t historylength : 16;\n+#endif /* Word 1 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */\n+\t\t/** Decompression Context Pointer Address */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#else /* Word 2 - Little Endian */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#endif /* Word 2 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 3 - Big Endian */\n+\t\t/** Decompression Context Pointer Control */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#else /* Word 3 - Little Endian */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#endif /* Word 3 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 4 - Big Endian */\n+\t\t/** Decompression history pointer address */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#else /* Word 4 - Little Endian */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#endif /* Word 4 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 5 - Big Endian */\n+\t\t/** Decompression history pointer control */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#else /* Word 5 - Little Endian */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#endif /* Word 5 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 6 - Big Endian */\n+\t\t/** Input and compression history pointer address */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#else /* Word 6 - Little Endian */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#endif /* Word 6 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 7 - Big Endian */\n+\t\t/** Input and compression history pointer control */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#else /* Word 7 - Little Endian */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#endif /* Word 7 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 8 - Big Endian */\n+\t\t/** Output pointer address */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#else /* Word 8 - Little Endian */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#endif /* Word 8 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 9 - Big Endian */\n+\t\t/** Output pointer control */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#else /* Word 9 - Little Endian */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#endif /* Word 9 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 10 - Big Endian */\n+\t\t/** Result pointer address */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#else /* Word 10 - Little Endian */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#endif /* Word 10 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 11 - Big Endian */\n+\t\t/** Result pointer control */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#else /* Word 11 - Little Endian */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#endif /* Word 11 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 12 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_812_831 : 20;\n+\t\t/** SSO guest group */\n+\t\tuint64_t ggrp : 10;\n+\t\t/** SSO tag type */\n+\t\tuint64_t tt : 2;\n+\t\t/** SSO tag */\n+\t\tuint64_t tag : 32;\n+#else /* Word 12 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t ggrp : 10;\n+\t\tuint64_t reserved_812_831 : 20;\n+#endif /* Word 12 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 13 - Big Endian */\n+\t\t/** Work queue entry pointer */\n+\t\tuint64_t wq_ptr : 64;\n+#else /* Word 13 - Little Endian */\n+\t\tuint64_t wq_ptr : 64;\n+#endif /* Word 13 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 14 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_896_959 : 64;\n+#else /* Word 14 - Little Endian */\n+\t\tuint64_t reserved_896_959 : 64;\n+#endif /* Word 14 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 15 - Big Endian */\n+\t\t/** Hash structure pointer */\n+\t\tuint64_t hash_ptr : 64;\n+#else /* Word 15 - Little Endian */\n+\t\tuint64_t hash_ptr : 64;\n+#endif /* Word 15 - End */\n+\t} /** ZIP 83xx Instruction Structure */s;\n+};\n+\n+/**\n+ * Structure zip_zres_s\n+ *\n+ * ZIP Result Structure\n+ * The ZIP coprocessor writes the result structure after it completes the\n+ * invocation. The result structure is exactly 24 bytes, and each invocation\n+ * of the ZIP coprocessor produces exactly one result structure.\n+ */\n+union zip_zres_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u[8];\n+\t/** ZIP Result Structure */\n+\tstruct zip_zres_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** crc32 checksum of uncompressed stream */\n+\t\tuint64_t crc32 : 32;\n+\t\t/** adler32 checksum of uncompressed stream*/\n+\t\tuint64_t adler32 : 32;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t adler32 : 32;\n+\t\tuint64_t crc32 : 32;\n+#endif /* Word 0 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** Total numer of Bytes produced in output stream */\n+\t\tuint64_t totalbyteswritten : 32;\n+\t\t/** Total number of bytes processed from the input stream */\n+\t\tuint64_t totalbytesread : 32;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t totalbytesread : 32;\n+\t\tuint64_t totalbyteswritten : 32;\n+#endif /* Word 1 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */\n+\t\t/** Total number of compressed input bits\n+\t\t * consumed to decompress all blocks in the file\n+\t\t */\n+\t\tuint64_t totalbitsprocessed : 32;\n+\t\t/** Done interrupt*/\n+\t\tuint64_t doneint : 1;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_155_158 : 4;\n+\t\t/** EXNUM */\n+\t\tuint64_t exn : 3;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_151 : 1;\n+\t\t/** EXBITS */\n+\t\tuint64_t exbits : 7;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_137_143 : 7;\n+\t\t/** End of file */\n+\t\tuint64_t ef : 1;\n+\t\t/** Completion/error code */\n+\t\tuint64_t compcode : 8;\n+#else /* Word 2 - Little Endian */\n+\t\tuint64_t compcode : 8;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t reserved_137_143 : 7;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t reserved_151 : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t reserved_155_158 : 4;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t totalbitsprocessed : 32;\n+#endif /* Word 2 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 3 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_253_255 : 3;\n+\t\t/** Hash length in bytes */\n+\t\tuint64_t hshlen : 61;\n+#else /* Word 3 - Little Endian */\n+\t\tuint64_t hshlen : 61;\n+\t\tuint64_t reserved_253_255 : 3;\n+#endif /* Word 3 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 4 - Big Endian */\n+\t\t/** Double-word 0 of computed hash */\n+\t\tuint64_t hash0 : 64;\n+#else /* Word 4 - Little Endian */\n+\t\tuint64_t hash0 : 64;\n+#endif /* Word 4 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 5 - Big Endian */\n+\t\t/** Double-word 1 of computed hash */\n+\t\tuint64_t hash1 : 64;\n+#else /* Word 5 - Little Endian */\n+\t\tuint64_t hash1 : 64;\n+#endif /* Word 5 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 6 - Big Endian */\n+\t\t/** Double-word 2 of computed hash */\n+\t\tuint64_t hash2 : 64;\n+#else /* Word 6 - Little Endian */\n+\t\tuint64_t hash2 : 64;\n+#endif /* Word 6 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 7 - Big Endian */\n+\t\t/** Double-word 3 of computed hash */\n+\t\tuint64_t hash3 : 64;\n+#else /* Word 7 - Little Endian */\n+\t\tuint64_t hash3 : 64;\n+#endif /* Word 7 - End */\n+\t} /** ZIP Result Structure */s;\n+\n+\t/* struct zip_zres_s_s cn83xx; */\n+};\n+\n+/**\n+ * Structure zip_zptr_s\n+ *\n+ * ZIP Generic Pointer Structure\n+ * This structure is the generic format of pointers in ZIP_INST_S.\n+ */\n+union zip_zptr_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u[2];\n+\t/** ZIP Generic Pointer Structure */\n+\tstruct zip_zptr_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** Pointer to Data or scatter-gather list */\n+\t\tuint64_t addr : 64;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t addr : 64;\n+#endif /* Word 0 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_112_127 : 16;\n+\t\t/** Length of Data or scatter-gather list*/\n+\t\tuint64_t length : 16;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\t/** Full-block write */\n+\t\tuint64_t fw : 1;\n+\t\t/** No cache allocation */\n+\t\tuint64_t nc : 1;\n+\t\t/** reserved */\n+\t\tuint64_t data_be : 1;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t data_be : 1;\n+\t\tuint64_t nc : 1;\n+\t\tuint64_t fw : 1;\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t reserved_112_127 : 16;\n+#endif /* Word 1 - End */\n+\t} /** ZIP Generic Pointer Structure */s;\n+};\n+\n+/**\n+ * Enumeration zip_comp_e\n+ *\n+ * ZIP Completion Enumeration\n+ * Enumerates the values of ZIP_ZRES_S[COMPCODE].\n+ */\n+#define ZIP_COMP_E_NOTDONE (0)\n+#define ZIP_COMP_E_SUCCESS (1)\n+#define ZIP_COMP_E_DTRUNC (2)\n+#define ZIP_COMP_E_DSTOP (3)\n+#define ZIP_COMP_E_ITRUNC (4)\n+#define ZIP_COMP_E_RBLOCK (5)\n+#define ZIP_COMP_E_NLEN (6)\n+#define ZIP_COMP_E_BADCODE (7)\n+#define ZIP_COMP_E_BADCODE2 (8)\n+#define ZIP_COMP_E_ZERO_LEN (9)\n+#define ZIP_COMP_E_PARITY (0xa)\n+#define ZIP_COMP_E_FATAL (0xb)\n+#define ZIP_COMP_E_TIMEOUT (0xc)\n+#define ZIP_COMP_E_INSTR_ERR (0xd)\n+#define ZIP_COMP_E_HCTX_ERR (0xe)\n+#define ZIP_COMP_E_STOP (3)\n+\n+/**\n+ * Enumeration zip_op_e\n+ *\n+ * ZIP Operation Enumeration\n+ * Enumerates ZIP_INST_S[OP].\n+ * Internal:\n+ */\n+#define ZIP_OP_E_DECOMP (0)\n+#define ZIP_OP_E_NOCOMP (1)\n+#define ZIP_OP_E_COMP (2)\n+\n+/**\n+ * Enumeration zip compression levels\n+ *\n+ * ZIP Compression Level Enumeration\n+ * Enumerates ZIP_INST_S[SS].\n+ * Internal:\n+ */\n+#define ZIP_COMP_E_LEVEL_MAX (0)\n+#define ZIP_COMP_E_LEVEL_MED (1)\n+#define ZIP_COMP_E_LEVEL_LOW (2)\n+#define ZIP_COMP_E_LEVEL_MIN (3)\n+\n+#endif\t/* _RTE_ZIP_REGS_H_ */\ndiff --git a/drivers/compress/octeontx/meson.build b/drivers/compress/octeontx/meson.build\nnew file mode 100644\nindex 0000000..7cd202d\n--- /dev/null\n+++ b/drivers/compress/octeontx/meson.build\n@@ -0,0 +1,9 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Cavium, Inc\n+\n+name = 'octeontx_compress'\n+sources = files('otx_zip.c', 'otx_zip_pmd.c')\n+allow_experimental_apis = true\n+includes += include_directories('include')\n+deps += ['mempool_octeontx', 'bus_pci']\n+ext_deps += dep\ndiff --git a/drivers/compress/octeontx/otx_zip.c b/drivers/compress/octeontx/otx_zip.c\nnew file mode 100644\nindex 0000000..7a1dd58\n--- /dev/null\n+++ b/drivers/compress/octeontx/otx_zip.c\n@@ -0,0 +1,62 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#include \"otx_zip.h\"\n+\n+uint64_t\n+zip_reg_read64(uint8_t *hw_addr, uint64_t offset)\n+{\n+\tuint8_t *base = hw_addr;\n+\treturn *(volatile uint64_t *)(base + offset);\n+}\n+\n+void\n+zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val)\n+{\n+\tuint8_t *base = hw_addr;\n+\t*(uint64_t *)(base + offset) = val;\n+}\n+\n+int\n+zipvf_create(struct rte_compressdev *compressdev)\n+{\n+\tstruct rte_pci_device *pdev = RTE_DEV_TO_PCI(compressdev->device);\n+\tstruct zip_vf *zipvf = NULL;\n+\tchar *dev_name = compressdev->data->name;\n+\tvoid *vbar0;\n+\tuint64_t reg;\n+\n+\tif (pdev->mem_resource[0].phys_addr == 0ULL)\n+\t\treturn -EIO;\n+\n+\tvbar0 = pdev->mem_resource[0].addr;\n+\tif (!vbar0) {\n+\t\tZIP_PMD_ERR(\"Failed to map BAR0 of %s\", dev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tzipvf = (struct zip_vf *)(compressdev->data->dev_private);\n+\n+\tif (!zipvf)\n+\t\treturn -ENOMEM;\n+\n+\tzipvf->vbar0 = vbar0;\n+\treg = zip_reg_read64(zipvf->vbar0, ZIP_VF_PF_MBOXX(0));\n+\t/* Storing domain in local to ZIP VF */\n+\tzipvf->dom_sdom = reg;\n+\tzipvf->pdev = pdev;\n+\tzipvf->max_nb_queue_pairs = ZIP_MAX_VF_QUEUE;\n+\treturn 0;\n+}\n+\n+int\n+zipvf_destroy(struct rte_compressdev *compressdev)\n+{\n+\tstruct zip_vf *vf = (struct zip_vf *)(compressdev->data->dev_private);\n+\n+\t/* Rewriting the domain_id in ZIP_VF_MBOX for app rerun */\n+\tzip_reg_write64(vf->vbar0, ZIP_VF_PF_MBOXX(0), vf->dom_sdom);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/compress/octeontx/otx_zip.h b/drivers/compress/octeontx/otx_zip.h\nnew file mode 100644\nindex 0000000..8a58f31\n--- /dev/null\n+++ b/drivers/compress/octeontx/otx_zip.h\n@@ -0,0 +1,113 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _RTE_OCTEONTX_ZIP_VF_H_\n+#define _RTE_OCTEONTX_ZIP_VF_H_\n+\n+#include <unistd.h>\n+\n+#include <rte_bus_pci.h>\n+#include <rte_comp.h>\n+#include <rte_compressdev.h>\n+#include <rte_compressdev_pmd.h>\n+#include <rte_malloc.h>\n+#include <rte_memory.h>\n+#include <rte_spinlock.h>\n+\n+#include <zip_regs.h>\n+\n+int octtx_zip_logtype_driver;\n+\n+/* ZIP VF Control/Status registers (CSRs): */\n+/* VF_BAR0: */\n+#define ZIP_VQ_ENA (0x10)\n+#define ZIP_VQ_SBUF_ADDR (0x20)\n+#define ZIP_VF_PF_MBOXX(x) (0x400 | (x)<<3)\n+#define ZIP_VQ_DOORBELL (0x1000)\n+\n+/**< Vendor ID */\n+#define PCI_VENDOR_ID_CAVIUM\t0x177D\n+/**< PCI device id of ZIP VF */\n+#define PCI_DEVICE_ID_OCTEONTX_ZIPVF\t0xA037\n+\n+/* maxmum number of zip vf devices */\n+#define ZIP_MAX_VFS 8\n+\n+/* max size of one chunk */\n+#define ZIP_MAX_CHUNK_SIZE\t8192\n+\n+/* each instruction is fixed 128 bytes */\n+#define ZIP_CMD_SIZE\t\t128\n+\n+#define ZIP_CMD_SIZE_WORDS\t(ZIP_CMD_SIZE >> 3) /* 16 64_bit words */\n+\n+/* size of next chunk buffer pointer */\n+#define ZIP_MAX_NCBP_SIZE\t8\n+\n+/* size of instruction queue in units of instruction size */\n+#define ZIP_MAX_NUM_CMDS\t((ZIP_MAX_CHUNK_SIZE - ZIP_MAX_NCBP_SIZE) / \\\n+\t\t\t\tZIP_CMD_SIZE) /* 63 */\n+\n+/* size of instruct queue in bytes */\n+#define ZIP_MAX_CMDQ_SIZE\t((ZIP_MAX_NUM_CMDS * ZIP_CMD_SIZE) + \\\n+\t\t\t\tZIP_MAX_NCBP_SIZE)/* ~8072ull */\n+\n+#define ZIP_BUF_SIZE\t256\n+\n+#define ZIP_SGPTR_ALIGN\t16\n+#define ZIP_CMDQ_ALIGN\t128\n+#define MAX_SG_LEN\t((ZIP_BUF_SIZE - ZIP_SGPTR_ALIGN) / sizeof(void *))\n+\n+/**< ZIP PMD specified queue pairs */\n+#define ZIP_MAX_VF_QUEUE\t1\n+\n+#define ZIP_ALIGN_ROUNDUP(x, _align) \\\n+\t((_align) * (((x) + (_align) - 1) / (_align)))\n+\n+/**< ZIP PMD device name */\n+#define COMPRESSDEV_NAME_ZIP_PMD\tcompress_octeonx\n+\n+#define ZIP_PMD_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, \\\n+\tocttx_zip_logtype_driver, \"%s(): \"fmt \"\\n\", \\\n+\t__func__, ##args)\n+\n+#define ZIP_PMD_INFO(fmt, args...) \\\n+\tZIP_PMD_LOG(INFO, fmt, ## args)\n+#define ZIP_PMD_ERR(fmt, args...) \\\n+\tZIP_PMD_LOG(ERR, fmt, ## args)\n+#define ZIP_PMD_WARN(fmt, args...) \\\n+\tZIP_PMD_LOG(WARNING, fmt, ## args)\n+\n+/**\n+ * ZIP VF device structure.\n+ */\n+struct zip_vf {\n+\tint vfid;\n+\t/* vf index */\n+\tstruct rte_pci_device *pdev;\n+\t/* pci device */\n+\tvoid *vbar0;\n+\t/* CSR base address for underlying BAR0 VF.*/\n+\tuint64_t dom_sdom;\n+\t/* Storing mbox domain and subdomain id for app rerun*/\n+\tuint32_t max_nb_queue_pairs;\n+\t/* pointer to device qps */\n+\tstruct rte_mempool *zip_mp;\n+\t/* pointer to pools */\n+} __rte_cache_aligned;\n+\n+int\n+zipvf_create(struct rte_compressdev *compressdev);\n+\n+int\n+zipvf_destroy(struct rte_compressdev *compressdev);\n+\n+uint64_t\n+zip_reg_read64(uint8_t *hw_addr, uint64_t offset);\n+\n+void\n+zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val);\n+\n+#endif /* _RTE_ZIP_VF_H_ */\ndiff --git a/drivers/compress/octeontx/otx_zip_pmd.c b/drivers/compress/octeontx/otx_zip_pmd.c\nnew file mode 100644\nindex 0000000..4d92c9d\n--- /dev/null\n+++ b/drivers/compress/octeontx/otx_zip_pmd.c\n@@ -0,0 +1,118 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#include <string.h>\n+\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_cpuflags.h>\n+#include <rte_malloc.h>\n+\n+#include \"otx_zip.h\"\n+\n+struct rte_compressdev_ops octtx_zip_pmd_ops = {\n+\n+};\n+\n+static int\n+zip_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\tstruct rte_pci_device *pci_dev)\n+{\n+\tint ret = 0;\n+\tchar compressdev_name[RTE_COMPRESSDEV_NAME_MAX_LEN];\n+\tstruct rte_compressdev *compressdev;\n+\tstruct rte_compressdev_pmd_init_params init_params = {\n+\t\t\"\",\n+\t\trte_socket_id(),\n+\t};\n+\n+\tZIP_PMD_INFO(\"vendor_id=0x%x device_id=0x%x\",\n+\t\t\t(unsigned int)pci_dev->id.vendor_id,\n+\t\t\t(unsigned int)pci_dev->id.device_id);\n+\n+\trte_pci_device_name(&pci_dev->addr, compressdev_name,\n+\t\t\t sizeof(compressdev_name));\n+\n+\tcompressdev = rte_compressdev_pmd_create(compressdev_name,\n+\t\t&pci_dev->device, sizeof(struct zip_vf), &init_params);\n+\tif (compressdev == NULL) {\n+\t\tZIP_PMD_ERR(\"driver %s: create failed\", init_params.name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/*\n+\t * create only if proc_type is primary.\n+\t */\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\t/* create vf dev with given pmd dev id */\n+\t\tret = zipvf_create(compressdev);\n+\t\tif (ret < 0) {\n+\t\t\tZIP_PMD_ERR(\"Device creation failed\");\n+\t\t\trte_compressdev_pmd_destroy(compressdev);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tcompressdev->dev_ops = &octtx_zip_pmd_ops;\n+\t/* register rx/tx burst functions for data path */\n+\tcompressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n+\treturn ret;\n+}\n+\n+static int\n+zip_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_compressdev *compressdev;\n+\tchar compressdev_name[RTE_COMPRESSDEV_NAME_MAX_LEN];\n+\n+\tif (pci_dev == NULL) {\n+\t\tZIP_PMD_ERR(\" Invalid PCI Device\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\trte_pci_device_name(&pci_dev->addr, compressdev_name,\n+\t\t\tsizeof(compressdev_name));\n+\n+\tcompressdev = rte_compressdev_pmd_get_named_dev(compressdev_name);\n+\tif (compressdev == NULL)\n+\t\treturn -ENODEV;\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\tif (zipvf_destroy(compressdev) < 0)\n+\t\t\treturn -ENODEV;\n+\t}\n+\treturn rte_compressdev_pmd_destroy(compressdev);\n+}\n+\n+static struct rte_pci_id pci_id_octtx_zipvf_table[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\tPCI_DEVICE_ID_OCTEONTX_ZIPVF),\n+\t},\n+\t{\n+\t\t.device_id = 0\n+\t},\n+};\n+\n+/**\n+ * Structure that represents a PCI driver\n+ */\n+static struct rte_pci_driver octtx_zip_pmd = {\n+\t.id_table = pci_id_octtx_zipvf_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = zip_pci_probe,\n+\t.remove = zip_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(COMPRESSDEV_NAME_ZIP_PMD, octtx_zip_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(COMPRESSDEV_NAME_ZIP_PMD, pci_id_octtx_zipvf_table);\n+\n+RTE_INIT(octtx_zip_init_log);\n+\n+static void\n+octtx_zip_init_log(void)\n+{\n+\tocttx_zip_logtype_driver = rte_log_register(\"pmd.compress.octeontx\");\n+\tif (octtx_zip_logtype_driver >= 0)\n+\t\trte_log_set_level(octtx_zip_logtype_driver, RTE_LOG_INFO);\n+}\ndiff --git a/drivers/compress/octeontx/rte_pmd_octeontx_compress_version.map b/drivers/compress/octeontx/rte_pmd_octeontx_compress_version.map\nnew file mode 100644\nindex 0000000..ad6e191\n--- /dev/null\n+++ b/drivers/compress/octeontx/rte_pmd_octeontx_compress_version.map\n@@ -0,0 +1,3 @@\n+DPDK_18.08 {\n+\tlocal: *;\n+};\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 5b7c684..429b8ba 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -222,6 +222,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += -lrte_pmd_virtio_crypto\n endif # CONFIG_RTE_LIBRTE_CRYPTODEV\n \n ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += -lrte_pmd_octeontx_zip\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lrte_pmd_isal_comp\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lisal\n # Link QAT driver if it has not been linked yet\n", "prefixes": [ "v4", "1/6" ] }