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{
    "id": 43058,
    "url": "http://patches.dpdk.org/api/patches/43058/",
    "web_url": "http://patches.dpdk.org/patch/43058/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<20180713142302.34576-5-david.hunt@intel.com>",
    "date": "2018-07-13T14:22:57",
    "name": "[v4,4/9] examples/vm_power: allow greater than 64 cores",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "2e3ab5536a4a8b03c46a0d921ecdaa962ba91e5c",
    "submitter": {
        "id": 342,
        "url": "http://patches.dpdk.org/api/people/342/",
        "name": "David Hunt",
        "email": "david.hunt@intel.com"
    },
    "delegate": {
        "id": 22,
        "url": "http://patches.dpdk.org/api/users/22/",
        "username": "pdelarag",
        "first_name": "Pablo",
        "last_name": "de Lara Guarch",
        "email": "pablo.de.lara.guarch@intel.com"
    },
    "mbox": "http://patches.dpdk.org/patch/43058/mbox/",
    "series": [
        {
            "id": 568,
            "url": "http://patches.dpdk.org/api/series/568/",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=568",
            "date": "2018-07-13T14:22:53",
            "name": "examples/vm_power: 100% Busy Polling",
            "version": 4,
            "mbox": "http://patches.dpdk.org/series/568/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/43058/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/43058/checks/",
    "tags": {},
    "headers": {
        "X-Mailman-Version": "2.1.15",
        "X-ExtLoop1": "1",
        "Errors-To": "dev-bounces@dpdk.org",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Mailer": "git-send-email 2.17.1",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5B41431FC;\n\tFri, 13 Jul 2018 16:23:30 +0200 (CEST)",
            "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id 8F9AD2BE5\n\tfor <dev@dpdk.org>; Fri, 13 Jul 2018 16:23:23 +0200 (CEST)",
            "from orsmga007.jf.intel.com ([10.7.209.58])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Jul 2018 07:23:23 -0700",
            "from silpixa00399952.ir.intel.com (HELO\n\tsilpixa00399952.ger.corp.intel.com) ([10.237.223.64])\n\tby orsmga007.jf.intel.com with ESMTP; 13 Jul 2018 07:23:22 -0700"
        ],
        "References": "<20180626092317.11031-2-david.hunt@intel.com>\n\t<20180713142302.34576-1-david.hunt@intel.com>",
        "X-Amp-File-Uploaded": "False",
        "X-BeenThere": "dev@dpdk.org",
        "Message-Id": "<20180713142302.34576-5-david.hunt@intel.com>",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,347,1526367600\"; d=\"scan'208\";a=\"56278206\"",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Precedence": "list",
        "From": "David Hunt <david.hunt@intel.com>",
        "X-Original-To": "patchwork@dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "In-Reply-To": "<20180713142302.34576-1-david.hunt@intel.com>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "To": "dev@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Date": "Fri, 13 Jul 2018 15:22:57 +0100",
        "Cc": "david.hunt@intel.com,\n\tthomas@monjalon.net",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "Subject": "[dpdk-dev] [PATCH v4 4/9] examples/vm_power: allow greater than 64\n\tcores"
    },
    "content": "To facilitate more info per core, change the global_cpu_mask\nfrom a uint64_t to an array. This also removes the limit on\n64 cores, allocing the aray at run-time based on the number of\ncores found in the system.\n\nSigned-off-by: David Hunt <david.hunt@intel.com>\nAcked-by: Radu Nicolau <radu.nicolau@intel.com>\n---\n examples/vm_power_manager/power_manager.c | 115 +++++++++++-----------\n 1 file changed, 58 insertions(+), 57 deletions(-)",
    "diff": "diff --git a/examples/vm_power_manager/power_manager.c b/examples/vm_power_manager/power_manager.c\nindex a7849e48a..4bdde23da 100644\n--- a/examples/vm_power_manager/power_manager.c\n+++ b/examples/vm_power_manager/power_manager.c\n@@ -19,14 +19,14 @@\n #include <rte_power.h>\n #include <rte_spinlock.h>\n \n+#include \"channel_manager.h\"\n #include \"power_manager.h\"\n-\n-#define RTE_LOGTYPE_POWER_MANAGER RTE_LOGTYPE_USER1\n+#include \"oob_monitor.h\"\n \n #define POWER_SCALE_CORE(DIRECTION, core_num , ret) do { \\\n-\tif (core_num >= POWER_MGR_MAX_CPUS) \\\n+\tif (core_num >= ci.core_count) \\\n \t\treturn -1; \\\n-\tif (!(global_enabled_cpus & (1ULL << core_num))) \\\n+\tif (!(ci.cd[core_num].global_enabled_cpus)) \\\n \t\treturn -1; \\\n \trte_spinlock_lock(&global_core_freq_info[core_num].power_sl); \\\n \tret = rte_power_freq_##DIRECTION(core_num); \\\n@@ -37,7 +37,7 @@\n \tint i; \\\n \tfor (i = 0; core_mask; core_mask &= ~(1 << i++)) { \\\n \t\tif ((core_mask >> i) & 1) { \\\n-\t\t\tif (!(global_enabled_cpus & (1ULL << i))) \\\n+\t\t\tif (!(ci.cd[i].global_enabled_cpus)) \\\n \t\t\t\tcontinue; \\\n \t\t\trte_spinlock_lock(&global_core_freq_info[i].power_sl); \\\n \t\t\tif (rte_power_freq_##DIRECTION(i) != 1) \\\n@@ -56,28 +56,9 @@ struct freq_info {\n static struct freq_info global_core_freq_info[POWER_MGR_MAX_CPUS];\n \n struct core_info ci;\n-static uint64_t global_enabled_cpus;\n \n #define SYSFS_CPU_PATH \"/sys/devices/system/cpu/cpu%u/topology/core_id\"\n \n-static unsigned\n-set_host_cpus_mask(void)\n-{\n-\tchar path[PATH_MAX];\n-\tunsigned i;\n-\tunsigned num_cpus = 0;\n-\n-\tfor (i = 0; i < POWER_MGR_MAX_CPUS; i++) {\n-\t\tsnprintf(path, sizeof(path), SYSFS_CPU_PATH, i);\n-\t\tif (access(path, F_OK) == 0) {\n-\t\t\tglobal_enabled_cpus |= 1ULL << i;\n-\t\t\tnum_cpus++;\n-\t\t} else\n-\t\t\treturn num_cpus;\n-\t}\n-\treturn num_cpus;\n-}\n-\n struct core_info *\n get_core_info(void)\n {\n@@ -110,38 +91,45 @@ core_info_init(void)\n int\n power_manager_init(void)\n {\n-\tunsigned int i, num_cpus, num_freqs;\n-\tuint64_t cpu_mask;\n+\tunsigned int i, num_cpus = 0, num_freqs = 0;\n \tint ret = 0;\n+\tstruct core_info *ci;\n+\n+\trte_power_set_env(PM_ENV_ACPI_CPUFREQ);\n \n-\tnum_cpus = set_host_cpus_mask();\n-\tif (num_cpus == 0) {\n-\t\tRTE_LOG(ERR, POWER_MANAGER, \"Unable to detected host CPUs, please \"\n-\t\t\t\"ensure that sufficient privileges exist to inspect sysfs\\n\");\n+\tci = get_core_info();\n+\tif (!ci) {\n+\t\tRTE_LOG(ERR, POWER_MANAGER,\n+\t\t\t\t\"Failed to get core info!\\n\");\n \t\treturn -1;\n \t}\n-\trte_power_set_env(PM_ENV_ACPI_CPUFREQ);\n-\tcpu_mask = global_enabled_cpus;\n-\tfor (i = 0; cpu_mask; cpu_mask &= ~(1 << i++)) {\n-\t\tif (rte_power_init(i) < 0)\n-\t\t\tRTE_LOG(ERR, POWER_MANAGER,\n-\t\t\t\t\t\"Unable to initialize power manager \"\n-\t\t\t\t\t\"for core %u\\n\", i);\n-\t\tnum_freqs = rte_power_freqs(i, global_core_freq_info[i].freqs,\n+\n+\tfor (i = 0; i < ci->core_count; i++) {\n+\t\tif (ci->cd[i].global_enabled_cpus) {\n+\t\t\tif (rte_power_init(i) < 0)\n+\t\t\t\tRTE_LOG(ERR, POWER_MANAGER,\n+\t\t\t\t\t\t\"Unable to initialize power manager \"\n+\t\t\t\t\t\t\"for core %u\\n\", i);\n+\t\t\tnum_cpus++;\n+\t\t\tnum_freqs = rte_power_freqs(i,\n+\t\t\t\t\tglobal_core_freq_info[i].freqs,\n \t\t\t\t\tRTE_MAX_LCORE_FREQS);\n-\t\tif (num_freqs == 0) {\n-\t\t\tRTE_LOG(ERR, POWER_MANAGER,\n-\t\t\t\t\"Unable to get frequency list for core %u\\n\",\n-\t\t\t\ti);\n-\t\t\tglobal_enabled_cpus &= ~(1 << i);\n-\t\t\tnum_cpus--;\n-\t\t\tret = -1;\n+\t\t\tif (num_freqs == 0) {\n+\t\t\t\tRTE_LOG(ERR, POWER_MANAGER,\n+\t\t\t\t\t\"Unable to get frequency list for core %u\\n\",\n+\t\t\t\t\ti);\n+\t\t\t\tci->cd[i].oob_enabled = 0;\n+\t\t\t\tret = -1;\n+\t\t\t}\n+\t\t\tglobal_core_freq_info[i].num_freqs = num_freqs;\n+\n+\t\t\trte_spinlock_init(&global_core_freq_info[i].power_sl);\n \t\t}\n-\t\tglobal_core_freq_info[i].num_freqs = num_freqs;\n-\t\trte_spinlock_init(&global_core_freq_info[i].power_sl);\n+\t\tif (ci->cd[i].oob_enabled)\n+\t\t\tadd_core_to_monitor(i);\n \t}\n-\tRTE_LOG(INFO, POWER_MANAGER, \"Detected %u host CPUs , enabled core mask:\"\n-\t\t\t\t\t\" 0x%\"PRIx64\"\\n\", num_cpus, global_enabled_cpus);\n+\tRTE_LOG(INFO, POWER_MANAGER, \"Managing %u cores out of %u available host cores\\n\",\n+\t\t\tnum_cpus, ci->core_count);\n \treturn ret;\n \n }\n@@ -156,7 +144,7 @@ power_manager_get_current_frequency(unsigned core_num)\n \t\t\t\tcore_num, POWER_MGR_MAX_CPUS-1);\n \t\treturn -1;\n \t}\n-\tif (!(global_enabled_cpus & (1ULL << core_num)))\n+\tif (!(ci.cd[core_num].global_enabled_cpus))\n \t\treturn 0;\n \n \trte_spinlock_lock(&global_core_freq_info[core_num].power_sl);\n@@ -175,15 +163,26 @@ power_manager_exit(void)\n {\n \tunsigned int i;\n \tint ret = 0;\n+\tstruct core_info *ci;\n \n-\tfor (i = 0; global_enabled_cpus; global_enabled_cpus &= ~(1 << i++)) {\n-\t\tif (rte_power_exit(i) < 0) {\n-\t\t\tRTE_LOG(ERR, POWER_MANAGER, \"Unable to shutdown power manager \"\n-\t\t\t\t\t\"for core %u\\n\", i);\n-\t\t\tret = -1;\n+\tci = get_core_info();\n+\tif (!ci) {\n+\t\tRTE_LOG(ERR, POWER_MANAGER,\n+\t\t\t\t\"Failed to get core info!\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tfor (i = 0; i < ci->core_count; i++) {\n+\t\tif (ci->cd[i].global_enabled_cpus) {\n+\t\t\tif (rte_power_exit(i) < 0) {\n+\t\t\t\tRTE_LOG(ERR, POWER_MANAGER, \"Unable to shutdown power manager \"\n+\t\t\t\t\t\t\"for core %u\\n\", i);\n+\t\t\t\tret = -1;\n+\t\t\t}\n+\t\t\tci->cd[i].global_enabled_cpus = 0;\n \t\t}\n+\t\tremove_core_from_monitor(i);\n \t}\n-\tglobal_enabled_cpus = 0;\n \treturn ret;\n }\n \n@@ -299,10 +298,12 @@ int\n power_manager_scale_core_med(unsigned int core_num)\n {\n \tint ret = 0;\n+\tstruct core_info *ci;\n \n+\tci = get_core_info();\n \tif (core_num >= POWER_MGR_MAX_CPUS)\n \t\treturn -1;\n-\tif (!(global_enabled_cpus & (1ULL << core_num)))\n+\tif (!(ci->cd[core_num].global_enabled_cpus))\n \t\treturn -1;\n \trte_spinlock_lock(&global_core_freq_info[core_num].power_sl);\n \tret = rte_power_set_freq(core_num,\n",
    "prefixes": [
        "v4",
        "4/9"
    ]
}