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GET /api/patches/42569/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 42569,
    "url": "http://patches.dpdk.org/api/patches/42569/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1530906406-289697-8-git-send-email-yipeng1.wang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1530906406-289697-8-git-send-email-yipeng1.wang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1530906406-289697-8-git-send-email-yipeng1.wang@intel.com",
    "date": "2018-07-06T19:46:45",
    "name": "[v3,7/8] test: add test case for read write concurrency",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "913743dc60ca4256bd3f21e4a2261abf0b5f3c48",
    "submitter": {
        "id": 754,
        "url": "http://patches.dpdk.org/api/people/754/?format=api",
        "name": "Wang, Yipeng1",
        "email": "yipeng1.wang@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1530906406-289697-8-git-send-email-yipeng1.wang@intel.com/mbox/",
    "series": [
        {
            "id": 463,
            "url": "http://patches.dpdk.org/api/series/463/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=463",
            "date": "2018-07-06T19:46:38",
            "name": "Add read-write concurrency to rte_hash library",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/463/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/42569/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/42569/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3E9361BE3E;\n\tSat,  7 Jul 2018 04:54:08 +0200 (CEST)",
            "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id 522241BE1D\n\tfor <dev@dpdk.org>; Sat,  7 Jul 2018 04:53:57 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t06 Jul 2018 19:53:55 -0700",
            "from skx-yipeng.jf.intel.com ([10.54.81.175])\n\tby FMSMGA003.fm.intel.com with ESMTP; 06 Jul 2018 19:53:45 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,319,1526367600\"; d=\"scan'208\";a=\"62888556\"",
        "From": "Yipeng Wang <yipeng1.wang@intel.com>",
        "To": "pablo.de.lara.guarch@intel.com",
        "Cc": "dev@dpdk.org, yipeng1.wang@intel.com, bruce.richardson@intel.com,\n\thonnappa.nagarahalli@arm.com, vguvva@caviumnetworks.com,\n\tbrijesh.s.singh@gmail.com",
        "Date": "Fri,  6 Jul 2018 12:46:45 -0700",
        "Message-Id": "<1530906406-289697-8-git-send-email-yipeng1.wang@intel.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1530906406-289697-1-git-send-email-yipeng1.wang@intel.com>",
        "References": "<1528455078-328182-1-git-send-email-yipeng1.wang@intel.com>\n\t<1530906406-289697-1-git-send-email-yipeng1.wang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 7/8] test: add test case for read write\n\tconcurrency",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This commits add a new test case for testing read/write concurrency.\n\nSigned-off-by: Yipeng Wang <yipeng1.wang@intel.com>\n---\n test/test/Makefile              |   1 +\n test/test/test_hash_readwrite.c | 646 ++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 647 insertions(+)\n create mode 100644 test/test/test_hash_readwrite.c",
    "diff": "diff --git a/test/test/Makefile b/test/test/Makefile\nindex eccc8ef..6ce66c9 100644\n--- a/test/test/Makefile\n+++ b/test/test/Makefile\n@@ -113,6 +113,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_perf.c\n SRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_functions.c\n SRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_scaling.c\n SRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_multiwriter.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_readwrite.c\n \n SRCS-$(CONFIG_RTE_LIBRTE_LPM) += test_lpm.c\n SRCS-$(CONFIG_RTE_LIBRTE_LPM) += test_lpm_perf.c\ndiff --git a/test/test/test_hash_readwrite.c b/test/test/test_hash_readwrite.c\nnew file mode 100644\nindex 0000000..39a2bbb\n--- /dev/null\n+++ b/test/test/test_hash_readwrite.c\n@@ -0,0 +1,646 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#include <inttypes.h>\n+#include <locale.h>\n+\n+#include <rte_cycles.h>\n+#include <rte_hash.h>\n+#include <rte_hash_crc.h>\n+#include <rte_jhash.h>\n+#include <rte_launch.h>\n+#include <rte_malloc.h>\n+#include <rte_random.h>\n+#include <rte_spinlock.h>\n+\n+#include \"test.h\"\n+\n+#define RTE_RWTEST_FAIL 0\n+\n+#define TOTAL_ENTRY (16*1024*1024)\n+#define TOTAL_INSERT (15*1024*1024)\n+\n+#define NUM_TEST 3\n+unsigned int core_cnt[NUM_TEST] = {2, 4, 8};\n+\n+struct perf {\n+\tuint32_t single_read;\n+\tuint32_t single_write;\n+\tuint32_t read_only[NUM_TEST];\n+\tuint32_t write_only[NUM_TEST];\n+\tuint32_t read_write_r[NUM_TEST];\n+\tuint32_t read_write_w[NUM_TEST];\n+};\n+\n+static struct perf htm_results, non_htm_results;\n+\n+struct {\n+\tuint32_t *keys;\n+\tuint32_t *found;\n+\tuint32_t num_insert;\n+\tuint32_t rounded_tot_insert;\n+\tstruct rte_hash *h;\n+} tbl_rw_test_param;\n+\n+static rte_atomic64_t gcycles;\n+static rte_atomic64_t ginsertions;\n+\n+static rte_atomic64_t gread_cycles;\n+static rte_atomic64_t gwrite_cycles;\n+\n+static rte_atomic64_t greads;\n+static rte_atomic64_t gwrites;\n+\n+static int\n+test_hash_readwrite_worker(__attribute__((unused)) void *arg)\n+{\n+\tuint64_t i, offset;\n+\tuint32_t lcore_id = rte_lcore_id();\n+\tuint64_t begin, cycles;\n+\tint ret;\n+\n+\toffset = (lcore_id - rte_get_master_lcore())\n+\t\t\t* tbl_rw_test_param.num_insert;\n+\n+\tprintf(\"Core #%d inserting and reading %d: %'\"PRId64\" - %'\"PRId64\"\\n\",\n+\t       lcore_id, tbl_rw_test_param.num_insert,\n+\t       offset, offset + tbl_rw_test_param.num_insert);\n+\n+\tbegin = rte_rdtsc_precise();\n+\n+\n+\tfor (i = offset; i < offset + tbl_rw_test_param.num_insert; i++) {\n+\n+\t\tif (rte_hash_lookup(tbl_rw_test_param.h,\n+\t\t\t\ttbl_rw_test_param.keys + i) > 0)\n+\t\t\tbreak;\n+\n+\t\tret = rte_hash_add_key(tbl_rw_test_param.h,\n+\t\t\t\t     tbl_rw_test_param.keys + i);\n+\t\tif (ret < 0)\n+\t\t\tbreak;\n+\n+\t\tif (rte_hash_lookup(tbl_rw_test_param.h,\n+\t\t\t\ttbl_rw_test_param.keys + i) != ret)\n+\t\t\tbreak;\n+\t}\n+\n+\tcycles = rte_rdtsc_precise() - begin;\n+\trte_atomic64_add(&gcycles, cycles);\n+\trte_atomic64_add(&ginsertions, i - offset);\n+\n+\tfor (; i < offset + tbl_rw_test_param.num_insert; i++)\n+\t\ttbl_rw_test_param.keys[i] = RTE_RWTEST_FAIL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+init_params(int use_htm, int use_jhash)\n+{\n+\tunsigned int i;\n+\n+\tuint32_t *keys = NULL;\n+\tuint32_t *found = NULL;\n+\tstruct rte_hash *handle;\n+\n+\tstruct rte_hash_parameters hash_params = {\n+\t\t.entries = TOTAL_ENTRY,\n+\t\t.key_len = sizeof(uint32_t),\n+\t\t.hash_func_init_val = 0,\n+\t\t.socket_id = rte_socket_id(),\n+\t};\n+\tif (use_jhash)\n+\t\thash_params.hash_func = rte_jhash;\n+\telse\n+\t\thash_params.hash_func = rte_hash_crc;\n+\n+\tif (use_htm)\n+\t\thash_params.extra_flag =\n+\t\t\tRTE_HASH_EXTRA_FLAGS_TRANS_MEM_SUPPORT |\n+\t\t\tRTE_HASH_EXTRA_FLAGS_RW_CONCURRENCY;\n+\telse\n+\t\thash_params.extra_flag =\n+\t\t\tRTE_HASH_EXTRA_FLAGS_RW_CONCURRENCY;\n+\n+\thash_params.name = \"tests\";\n+\n+\thandle = rte_hash_create(&hash_params);\n+\tif (handle == NULL) {\n+\t\tprintf(\"hash creation failed\");\n+\t\treturn -1;\n+\t}\n+\n+\ttbl_rw_test_param.h = handle;\n+\tkeys = rte_malloc(NULL, sizeof(uint32_t) * TOTAL_ENTRY, 0);\n+\n+\tif (keys == NULL) {\n+\t\tprintf(\"RTE_MALLOC failed\\n\");\n+\t\tgoto err;\n+\t}\n+\n+\tfound = rte_zmalloc(NULL, sizeof(uint32_t) * TOTAL_ENTRY, 0);\n+\tif (found == NULL) {\n+\t\tprintf(\"RTE_ZMALLOC failed\\n\");\n+\t\tgoto err;\n+\t}\n+\n+\n+\ttbl_rw_test_param.keys = keys;\n+\ttbl_rw_test_param.found = found;\n+\n+\tfor (i = 0; i < TOTAL_ENTRY; i++)\n+\t\tkeys[i] = i;\n+\n+\treturn 0;\n+\n+err:\n+\trte_free(keys);\n+\trte_hash_free(handle);\n+\n+\treturn -1;\n+}\n+\n+static int\n+test_hash_readwrite_functional(int use_htm)\n+{\n+\tunsigned int i;\n+\tconst void *next_key;\n+\tvoid *next_data;\n+\tuint32_t iter = 0;\n+\n+\tuint32_t duplicated_keys = 0;\n+\tuint32_t lost_keys = 0;\n+\tint use_jhash = 1;\n+\n+\trte_atomic64_init(&gcycles);\n+\trte_atomic64_clear(&gcycles);\n+\n+\trte_atomic64_init(&ginsertions);\n+\trte_atomic64_clear(&ginsertions);\n+\n+\tif (init_params(use_htm, use_jhash) != 0)\n+\t\tgoto err;\n+\n+\ttbl_rw_test_param.num_insert =\n+\t\tTOTAL_INSERT / rte_lcore_count();\n+\n+\ttbl_rw_test_param.rounded_tot_insert =\n+\t\ttbl_rw_test_param.num_insert\n+\t\t* rte_lcore_count();\n+\n+\tprintf(\"++++++++Start function tests:+++++++++\\n\");\n+\n+\t/* Fire all threads. */\n+\trte_eal_mp_remote_launch(test_hash_readwrite_worker,\n+\t\t\t\t NULL, CALL_MASTER);\n+\trte_eal_mp_wait_lcore();\n+\n+\twhile (rte_hash_iterate(tbl_rw_test_param.h, &next_key,\n+\t\t\t&next_data, &iter) >= 0) {\n+\t\t/* Search for the key in the list of keys added .*/\n+\t\ti = *(const uint32_t *)next_key;\n+\t\ttbl_rw_test_param.found[i]++;\n+\t}\n+\n+\tfor (i = 0; i < tbl_rw_test_param.rounded_tot_insert; i++) {\n+\t\tif (tbl_rw_test_param.keys[i] != RTE_RWTEST_FAIL) {\n+\t\t\tif (tbl_rw_test_param.found[i] > 1) {\n+\t\t\t\tduplicated_keys++;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (tbl_rw_test_param.found[i] == 0) {\n+\t\t\t\tlost_keys++;\n+\t\t\t\tprintf(\"key %d is lost\\n\", i);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (duplicated_keys > 0) {\n+\t\tprintf(\"%d key duplicated\\n\", duplicated_keys);\n+\t\tgoto err_free;\n+\t}\n+\n+\tif (lost_keys > 0) {\n+\t\tprintf(\"%d key lost\\n\", lost_keys);\n+\t\tgoto err_free;\n+\t}\n+\n+\tprintf(\"No key corrupted during read-write test.\\n\");\n+\n+\tunsigned long long int cycles_per_insertion =\n+\t\trte_atomic64_read(&gcycles) /\n+\t\trte_atomic64_read(&ginsertions);\n+\n+\tprintf(\"cycles per insertion and lookup: %llu\\n\", cycles_per_insertion);\n+\n+\trte_free(tbl_rw_test_param.found);\n+\trte_free(tbl_rw_test_param.keys);\n+\trte_hash_free(tbl_rw_test_param.h);\n+\tprintf(\"+++++++++Complete function tests+++++++++\\n\");\n+\treturn 0;\n+\n+err_free:\n+\trte_free(tbl_rw_test_param.found);\n+\trte_free(tbl_rw_test_param.keys);\n+\trte_hash_free(tbl_rw_test_param.h);\n+err:\n+\treturn -1;\n+}\n+\n+static int\n+test_rw_reader(__attribute__((unused)) void *arg)\n+{\n+\tuint64_t i;\n+\tuint64_t begin, cycles;\n+\tuint64_t read_cnt = (uint64_t)((uintptr_t)arg);\n+\n+\tbegin = rte_rdtsc_precise();\n+\tfor (i = 0; i < read_cnt; i++) {\n+\t\tvoid *data;\n+\t\trte_hash_lookup_data(tbl_rw_test_param.h,\n+\t\t\t\ttbl_rw_test_param.keys + i,\n+\t\t\t\t&data);\n+\t\tif (i != (uint64_t)(uintptr_t)data) {\n+\t\t\tprintf(\"lookup find wrong value %\"PRIu64\",\"\n+\t\t\t\t\"%\"PRIu64\"\\n\", i,\n+\t\t\t\t(uint64_t)(uintptr_t)data);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tcycles = rte_rdtsc_precise() - begin;\n+\trte_atomic64_add(&gread_cycles, cycles);\n+\trte_atomic64_add(&greads, i);\n+\treturn 0;\n+}\n+\n+static int\n+test_rw_writer(__attribute__((unused)) void *arg)\n+{\n+\tuint64_t i;\n+\tuint32_t lcore_id = rte_lcore_id();\n+\tuint64_t begin, cycles;\n+\tint ret;\n+\tuint64_t start_coreid = (uint64_t)(uintptr_t)arg;\n+\tuint64_t offset;\n+\n+\toffset = TOTAL_INSERT / 2 + (lcore_id - start_coreid)\n+\t\t\t\t\t* tbl_rw_test_param.num_insert;\n+\tbegin = rte_rdtsc_precise();\n+\tfor (i = offset; i < offset + tbl_rw_test_param.num_insert; i++) {\n+\t\tret = rte_hash_add_key_data(tbl_rw_test_param.h,\n+\t\t\t\ttbl_rw_test_param.keys + i,\n+\t\t\t\t(void *)((uintptr_t)i));\n+\t\tif (ret < 0) {\n+\t\t\tprintf(\"writer failed %\"PRIu64\"\\n\", i);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tcycles = rte_rdtsc_precise() - begin;\n+\trte_atomic64_add(&gwrite_cycles, cycles);\n+\trte_atomic64_add(&gwrites, tbl_rw_test_param.num_insert);\n+\treturn 0;\n+}\n+\n+static int\n+test_hash_readwrite_perf(struct perf *perf_results, int use_htm,\n+\t\t\t\t\t\t\tint reader_faster)\n+{\n+\tunsigned int n;\n+\tint ret;\n+\tint start_coreid;\n+\tuint64_t i, read_cnt;\n+\n+\tconst void *next_key;\n+\tvoid *next_data;\n+\tuint32_t iter = 0;\n+\tint use_jhash = 0;\n+\n+\tuint32_t duplicated_keys = 0;\n+\tuint32_t lost_keys = 0;\n+\n+\tuint64_t start = 0, end = 0;\n+\n+\trte_atomic64_init(&greads);\n+\trte_atomic64_init(&gwrites);\n+\trte_atomic64_clear(&gwrites);\n+\trte_atomic64_clear(&greads);\n+\n+\trte_atomic64_init(&gread_cycles);\n+\trte_atomic64_clear(&gread_cycles);\n+\trte_atomic64_init(&gwrite_cycles);\n+\trte_atomic64_clear(&gwrite_cycles);\n+\n+\tif (init_params(use_htm, use_jhash) != 0)\n+\t\tgoto err;\n+\n+\t/*\n+\t * Do a readers finish faster or writers finish faster test.\n+\t * When readers finish faster, we timing the readers, and when writers\n+\t * finish faster, we timing the writers.\n+\t * Divided by 10 or 2 is just experimental values to vary the workload\n+\t * of readers.\n+\t */\n+\tif (reader_faster) {\n+\t\tprintf(\"++++++Start perf test: reader++++++++\\n\");\n+\t\tread_cnt = TOTAL_INSERT / 10;\n+\t} else {\n+\t\tprintf(\"++++++Start perf test: writer++++++++\\n\");\n+\t\tread_cnt = TOTAL_INSERT / 2;\n+\t}\n+\n+\n+\t/* We first test single thread performance */\n+\tstart = rte_rdtsc_precise();\n+\t/* Insert half of the keys */\n+\tfor (i = 0; i < TOTAL_INSERT / 2; i++) {\n+\t\tret = rte_hash_add_key_data(tbl_rw_test_param.h,\n+\t\t\t\t     tbl_rw_test_param.keys + i,\n+\t\t\t\t\t(void *)((uintptr_t)i));\n+\t\tif (ret < 0) {\n+\t\t\tprintf(\"Failed to insert half of keys\\n\");\n+\t\t\tgoto err_free;\n+\t\t}\n+\t}\n+\tend = rte_rdtsc_precise() - start;\n+\tperf_results->single_write = end / i;\n+\n+\tstart = rte_rdtsc_precise();\n+\n+\tfor (i = 0; i < read_cnt; i++) {\n+\t\tvoid *data;\n+\t\trte_hash_lookup_data(tbl_rw_test_param.h,\n+\t\t\t\ttbl_rw_test_param.keys + i,\n+\t\t\t\t&data);\n+\t\tif (i != (uint64_t)(uintptr_t)data) {\n+\t\t\tprintf(\"lookup find wrong value\"\n+\t\t\t\t\t\" %\"PRIu64\",%\"PRIu64\"\\n\", i,\n+\t\t\t\t\t(uint64_t)(uintptr_t)data);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tend = rte_rdtsc_precise() - start;\n+\tperf_results->single_read = end / i;\n+\n+\tfor (n = 0; n < NUM_TEST; n++) {\n+\t\tunsigned int tot_lcore = rte_lcore_count();\n+\t\tif (tot_lcore < core_cnt[n] * 2 + 1)\n+\t\t\tgoto finish;\n+\n+\t\trte_atomic64_clear(&greads);\n+\t\trte_atomic64_clear(&gread_cycles);\n+\t\trte_atomic64_clear(&gwrites);\n+\t\trte_atomic64_clear(&gwrite_cycles);\n+\n+\t\trte_hash_reset(tbl_rw_test_param.h);\n+\n+\t\ttbl_rw_test_param.num_insert = TOTAL_INSERT / 2 / core_cnt[n];\n+\t\ttbl_rw_test_param.rounded_tot_insert = TOTAL_INSERT / 2 +\n+\t\t\t\t\t\ttbl_rw_test_param.num_insert *\n+\t\t\t\t\t\tcore_cnt[n];\n+\n+\n+\t\tfor (i = 0; i < TOTAL_INSERT / 2; i++) {\n+\t\t\tret = rte_hash_add_key_data(tbl_rw_test_param.h,\n+\t\t\t\t\ttbl_rw_test_param.keys + i,\n+\t\t\t\t\t(void *)((uintptr_t)i));\n+\t\t\tif (ret < 0) {\n+\t\t\t\tprintf(\"Failed to insert half of keys\\n\");\n+\t\t\t\tgoto err_free;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Then test multiple thread case but only all reads or\n+\t\t * all writes\n+\t\t */\n+\n+\t\t/* Test only reader cases */\n+\t\tfor (i = 1; i <= core_cnt[n]; i++)\n+\t\t\trte_eal_remote_launch(test_rw_reader,\n+\t\t\t\t\t(void *)(uintptr_t)read_cnt, i);\n+\n+\t\trte_eal_mp_wait_lcore();\n+\n+\t\tstart_coreid = i;\n+\t\t/* Test only writer cases */\n+\t\tfor (; i <= core_cnt[n] * 2; i++)\n+\t\t\trte_eal_remote_launch(test_rw_writer,\n+\t\t\t\t\t(void *)((uintptr_t)start_coreid), i);\n+\n+\n+\t\trte_eal_mp_wait_lcore();\n+\n+\t\tif (reader_faster) {\n+\t\t\tunsigned long long int cycles_per_insertion =\n+\t\t\t\trte_atomic64_read(&gread_cycles) /\n+\t\t\t\trte_atomic64_read(&greads);\n+\t\t\tperf_results->read_only[n] = cycles_per_insertion;\n+\t\t\tprintf(\"Reader only: cycles per lookup: %llu\\n\",\n+\t\t\t\t\t\t\tcycles_per_insertion);\n+\t\t}\n+\n+\t\telse {\n+\t\t\tunsigned long long int cycles_per_insertion =\n+\t\t\t\trte_atomic64_read(&gwrite_cycles) /\n+\t\t\t\trte_atomic64_read(&gwrites);\n+\t\t\tperf_results->write_only[n] = cycles_per_insertion;\n+\t\t\tprintf(\"Writer only: cycles per writes: %llu\\n\",\n+\t\t\t\t\t\t\tcycles_per_insertion);\n+\t\t}\n+\n+\t\trte_atomic64_clear(&greads);\n+\t\trte_atomic64_clear(&gread_cycles);\n+\t\trte_atomic64_clear(&gwrites);\n+\t\trte_atomic64_clear(&gwrite_cycles);\n+\n+\t\trte_hash_reset(tbl_rw_test_param.h);\n+\n+\t\tfor (i = 0; i < TOTAL_INSERT / 2; i++) {\n+\t\t\tret = rte_hash_add_key_data(tbl_rw_test_param.h,\n+\t\t\t\t\ttbl_rw_test_param.keys + i,\n+\t\t\t\t\t(void *)((uintptr_t)i));\n+\t\t\tif (ret < 0) {\n+\t\t\t\tprintf(\"Failed to insert half of keys\\n\");\n+\t\t\t\tgoto err_free;\n+\t\t\t}\n+\t\t}\n+\n+\n+\t\tstart_coreid = core_cnt[n] + 1;\n+\n+\t\tif (reader_faster) {\n+\t\t\tfor (i = core_cnt[n] + 1; i <= core_cnt[n] * 2; i++)\n+\t\t\t\trte_eal_remote_launch(test_rw_writer,\n+\t\t\t\t\t(void *)((uintptr_t)start_coreid), i);\n+\t\t\tfor (i = 1; i <= core_cnt[n]; i++)\n+\t\t\t\trte_eal_remote_launch(test_rw_reader,\n+\t\t\t\t\t(void *)(uintptr_t)read_cnt, i);\n+\t\t} else {\n+\t\t\tfor (i = 1; i <= core_cnt[n]; i++)\n+\t\t\t\trte_eal_remote_launch(test_rw_reader,\n+\t\t\t\t\t(void *)(uintptr_t)read_cnt, i);\n+\t\t\tfor (; i <= core_cnt[n] * 2; i++)\n+\t\t\t\trte_eal_remote_launch(test_rw_writer,\n+\t\t\t\t\t(void *)((uintptr_t)start_coreid), i);\n+\t\t}\n+\n+\t\trte_eal_mp_wait_lcore();\n+\n+\t\twhile (rte_hash_iterate(tbl_rw_test_param.h,\n+\t\t\t\t&next_key, &next_data, &iter) >= 0) {\n+\t\t\t/* Search for the key in the list of keys added .*/\n+\t\t\ti = *(const uint32_t *)next_key;\n+\t\t\ttbl_rw_test_param.found[i]++;\n+\t\t}\n+\n+\n+\t\tfor (i = 0; i < tbl_rw_test_param.rounded_tot_insert; i++) {\n+\t\t\tif (tbl_rw_test_param.keys[i] != RTE_RWTEST_FAIL) {\n+\t\t\t\tif (tbl_rw_test_param.found[i] > 1) {\n+\t\t\t\t\tduplicated_keys++;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tif (tbl_rw_test_param.found[i] == 0) {\n+\t\t\t\t\tlost_keys++;\n+\t\t\t\t\tprintf(\"key %\"PRIu64\" is lost\\n\", i);\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (duplicated_keys > 0) {\n+\t\t\tprintf(\"%d key duplicated\\n\", duplicated_keys);\n+\t\t\tgoto err_free;\n+\t\t}\n+\n+\t\tif (lost_keys > 0) {\n+\t\t\tprintf(\"%d key lost\\n\", lost_keys);\n+\t\t\tgoto err_free;\n+\t\t}\n+\n+\t\tprintf(\"No key corrupted during read-write test.\\n\");\n+\n+\t\tif (reader_faster) {\n+\t\t\tunsigned long long int cycles_per_insertion =\n+\t\t\t\trte_atomic64_read(&gread_cycles) /\n+\t\t\t\trte_atomic64_read(&greads);\n+\t\t\tperf_results->read_write_r[n] = cycles_per_insertion;\n+\t\t\tprintf(\"Read-write cycles per lookup: %llu\\n\",\n+\t\t\t\t\t\t\tcycles_per_insertion);\n+\t\t}\n+\n+\t\telse {\n+\t\t\tunsigned long long int cycles_per_insertion =\n+\t\t\t\trte_atomic64_read(&gwrite_cycles) /\n+\t\t\t\trte_atomic64_read(&gwrites);\n+\t\t\tperf_results->read_write_w[n] = cycles_per_insertion;\n+\t\t\tprintf(\"Read-write cycles per writes: %llu\\n\",\n+\t\t\t\t\t\t\tcycles_per_insertion);\n+\t\t}\n+\t}\n+\n+finish:\n+\trte_free(tbl_rw_test_param.found);\n+\trte_free(tbl_rw_test_param.keys);\n+\trte_hash_free(tbl_rw_test_param.h);\n+\treturn 0;\n+\n+err_free:\n+\trte_free(tbl_rw_test_param.found);\n+\trte_free(tbl_rw_test_param.keys);\n+\trte_hash_free(tbl_rw_test_param.h);\n+\n+err:\n+\treturn -1;\n+}\n+\n+static int\n+test_hash_readwrite_main(void)\n+{\n+\t/*\n+\t * Variables used to choose different tests.\n+\t * use_htm indicates if hardware transactional memory should be used.\n+\t * reader_faster indicates if the reader threads should finish earlier\n+\t * than writer threads. This is to timing either reader threads or\n+\t * writer threads for performance numbers.\n+\t */\n+\tint use_htm, reader_faster;\n+\n+\tif (rte_lcore_count() == 1) {\n+\t\tprintf(\"More than one lcore is required \"\n+\t\t\t\"to do read write test\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\n+\tsetlocale(LC_NUMERIC, \"\");\n+\n+\tif (rte_tm_supported()) {\n+\t\tprintf(\"Hardware transactional memory (lock elision) \"\n+\t\t\t\"is supported\\n\");\n+\n+\t\tprintf(\"Test read-write with Hardware transactional memory\\n\");\n+\n+\t\tuse_htm = 1;\n+\t\tif (test_hash_readwrite_functional(use_htm) < 0)\n+\t\t\treturn -1;\n+\n+\t\treader_faster = 1;\n+\t\tif (test_hash_readwrite_perf(&htm_results, use_htm,\n+\t\t\t\t\t\t\treader_faster) < 0)\n+\t\t\treturn -1;\n+\n+\t\treader_faster = 0;\n+\t\tif (test_hash_readwrite_perf(&htm_results, use_htm,\n+\t\t\t\t\t\t\treader_faster) < 0)\n+\t\t\treturn -1;\n+\t} else {\n+\t\tprintf(\"Hardware transactional memory (lock elision) \"\n+\t\t\t\"is NOT supported\\n\");\n+\t}\n+\n+\tprintf(\"Test read-write without Hardware transactional memory\\n\");\n+\tuse_htm = 0;\n+\tif (test_hash_readwrite_functional(use_htm) < 0)\n+\t\treturn -1;\n+\treader_faster = 1;\n+\tif (test_hash_readwrite_perf(&non_htm_results, use_htm,\n+\t\t\t\t\t\t\treader_faster) < 0)\n+\t\treturn -1;\n+\treader_faster = 0;\n+\tif (test_hash_readwrite_perf(&non_htm_results, use_htm,\n+\t\t\t\t\t\t\treader_faster) < 0)\n+\t\treturn -1;\n+\n+\n+\tprintf(\"Results summary:\\n\");\n+\n+\tint i;\n+\n+\tprintf(\"single read: %u\\n\", htm_results.single_read);\n+\tprintf(\"single write: %u\\n\", htm_results.single_write);\n+\tfor (i = 0; i < NUM_TEST; i++) {\n+\t\tprintf(\"core_cnt: %u\\n\", core_cnt[i]);\n+\t\tprintf(\"HTM:\\n\");\n+\t\tprintf(\"read only: %u\\n\", htm_results.read_only[i]);\n+\t\tprintf(\"write only: %u\\n\", htm_results.write_only[i]);\n+\t\tprintf(\"read-write read: %u\\n\", htm_results.read_write_r[i]);\n+\t\tprintf(\"read-write write: %u\\n\", htm_results.read_write_w[i]);\n+\n+\t\tprintf(\"non HTM:\\n\");\n+\t\tprintf(\"read only: %u\\n\", non_htm_results.read_only[i]);\n+\t\tprintf(\"write only: %u\\n\", non_htm_results.write_only[i]);\n+\t\tprintf(\"read-write read: %u\\n\",\n+\t\t\tnon_htm_results.read_write_r[i]);\n+\t\tprintf(\"read-write write: %u\\n\",\n+\t\t\tnon_htm_results.read_write_w[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+REGISTER_TEST_COMMAND(hash_readwrite_autotest, test_hash_readwrite_main);\n",
    "prefixes": [
        "v3",
        "7/8"
    ]
}