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Update a patch.
GET /api/patches/42108/?format=api
{ "id": 42108, "url": "http://patches.dpdk.org/api/patches/42108/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1530550477-22444-2-git-send-email-shally.verma@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1530550477-22444-2-git-send-email-shally.verma@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1530550477-22444-2-git-send-email-shally.verma@caviumnetworks.com", "date": "2018-07-02T16:54:32", "name": "[v2,1/6] compress/octeontx: add octeontx zip PMD support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "75883e11919479490b6acdbfd0c6a6c607a87b80", "submitter": { "id": 960, "url": "http://patches.dpdk.org/api/people/960/?format=api", "name": "Shally Verma", "email": "shally.verma@caviumnetworks.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1530550477-22444-2-git-send-email-shally.verma@caviumnetworks.com/mbox/", "series": [ { "id": 361, "url": "http://patches.dpdk.org/api/series/361/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=361", "date": "2018-07-02T16:54:31", "name": "compress: add Octeontx ZIP compression PMD", "version": 2, "mbox": "http://patches.dpdk.org/series/361/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/42108/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/42108/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 073971B532;\n\tMon, 2 Jul 2018 18:55:52 +0200 (CEST)", "from NAM03-CO1-obe.outbound.protection.outlook.com\n\t(mail-co1nam03hn0226.outbound.protection.outlook.com [104.47.40.226])\n\tby dpdk.org (Postfix) with ESMTP id 335451B523\n\tfor <dev@dpdk.org>; Mon, 2 Jul 2018 18:55:50 +0200 (CEST)", "from hyd1sverma-dt.caveonetworks.com (115.113.156.2) by\n\tMWHPR0701MB3644.namprd07.prod.outlook.com (2603:10b6:301:7d::37) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.906.20;\n\tMon, 2 Jul 2018 16:55:46 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=n0539EFMWv1JxrDLYChJBrmmds0vL4dON7FJxal8KIY=;\n\tb=Xk4TSS1dpzNAACF9Sqkt4bhAfqLXLuBMfFOiwsESqazFN/VaQxrpg1vW20W79RwlHkkLpC9jk/Fg77uHGlvz3ih3kioJkW0bbBhyHPLf1cOuBUlLlpYoTwsF5RxBrjcEAoj7e/q8SnRvxTlGVXgCUCY4tVz6gKMixy4OYclrfEo=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Shally.Verma@cavium.com; ", "From": "Shally Verma <shally.verma@caviumnetworks.com>", "To": "pablo.de.lara.guarch@intel.com", "Cc": "dev@dpdk.org, pathreya@caviumnetworks.com, mchalla@caviumnetworks.com,\n\tSunila Sahu <sunila.sahu@caviumnetworks.com>,\n\tAshish Gupta <Ashish.Gupta@caviumnetworks.com>", "Date": "Mon, 2 Jul 2018 22:24:32 +0530", "Message-Id": "<1530550477-22444-2-git-send-email-shally.verma@caviumnetworks.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1530550477-22444-1-git-send-email-shally.verma@caviumnetworks.com>", "References": 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"b9afe8a6-be85-460c-1885-08d5e03ca964", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR0701MB3644", "Subject": "[dpdk-dev] [PATCH v2 1/6] compress/octeontx: add octeontx zip PMD\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunila Sahu <sunila.sahu@caviumnetworks.com>\n\nAdd octeontx zip pmd support in compressdev driver.\nOcteontx ZIP appears as PCI device.\nAdd device probe and remove support.\nlink zip pmd library in rtp.app.mk\nUpdate meson.build and Makefile to build octeontx zip pmd\n\nSigned-off-by: Ashish Gupta <Ashish.Gupta@caviumnetworks.com>\nSigned-off-by: Shally Verma <shally.verma@caviumnetworks.com>\nSigned-off-by: Sunila Sahu <sunila.sahu@caviumnetworks.com>\n---\n MAINTAINERS | 5 +\n config/common_base | 5 +\n drivers/compress/Makefile | 1 +\n drivers/compress/meson.build | 2 +-\n drivers/compress/octeontx/Makefile | 30 +\n drivers/compress/octeontx/include/zip_regs.h | 721 +++++++++++++++++++++\n drivers/compress/octeontx/meson.build | 11 +\n .../compress/octeontx/rte_pmd_octeontx_version.map | 3 +\n drivers/compress/octeontx/zip_pmd.c | 120 ++++\n drivers/compress/octeontx/zipvf.c | 63 ++\n drivers/compress/octeontx/zipvf.h | 111 ++++\n mk/rte.app.mk | 1 +\n 12 files changed, 1072 insertions(+), 1 deletion(-)", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex bc1607844..78708d8af 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -850,6 +850,11 @@ F: drivers/compress/isal/\n F: doc/guides/compressdevs/isal.rst\n F: doc/guides/compressdevs/features/isal.ini\n \n+Cavium OCTEONTX zipvf\n+M: Ashish Gupta <ashish.gupta@cavium.com>\n+F: drivers/compress/octeontx\n+F: doc/guides/compressdevs/octeontx.rst\n+F: doc/guides/compressdevs/features/octeontx.ini\n \n Eventdev Drivers\n ----------------\ndiff --git a/config/common_base b/config/common_base\nindex 6541ad5b2..396a09682 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -578,6 +578,11 @@ CONFIG_RTE_COMPRESS_MAX_DEVS=64\n #\n CONFIG_RTE_COMPRESSDEV_TEST=n\n \n+#\n+# Compile PMD for Octeontx ZIPVF compression device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF=y\n+\n #\n # Compile PMD for ISA-L compression device\n #\ndiff --git a/drivers/compress/Makefile b/drivers/compress/Makefile\nindex 592497f51..25cced348 100644\n--- a/drivers/compress/Makefile\n+++ b/drivers/compress/Makefile\n@@ -4,5 +4,6 @@\n include $(RTE_SDK)/mk/rte.vars.mk\n \n DIRS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += isal\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += octeontx\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/compress/meson.build b/drivers/compress/meson.build\nindex fb136e1b2..a7d6f3a40 100644\n--- a/drivers/compress/meson.build\n+++ b/drivers/compress/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2018 Intel Corporation\n \n-drivers = ['isal']\n+drivers = ['isal', 'octeontx']\n \n std_deps = ['compressdev'] # compressdev pulls in all other needed deps\n config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'\ndiff --git a/drivers/compress/octeontx/Makefile b/drivers/compress/octeontx/Makefile\nnew file mode 100644\nindex 000000000..a58f3df3a\n--- /dev/null\n+++ b/drivers/compress/octeontx/Makefile\n@@ -0,0 +1,30 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Cavium, Inc\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_octeontx_zip.a\n+\n+# library version\n+LIBABIVER := 1\n+\n+# build flags\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -O3\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+CFLAGS += -I$(RTE_SDK)/drivers/compress/octeontx/include\n+\n+# external library include paths\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_compressdev\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+\n+# library source files\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += zip_pmd.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += zipvf.c\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_octeontx_version.map\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/compress/octeontx/include/zip_regs.h b/drivers/compress/octeontx/include/zip_regs.h\nnew file mode 100644\nindex 000000000..0eec393c3\n--- /dev/null\n+++ b/drivers/compress/octeontx/include/zip_regs.h\n@@ -0,0 +1,721 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _RTE_OCTEONTX_ZIP_REGS_H_\n+#define _RTE_OCTEONTX_ZIP_REGS_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stddef.h>\n+#include <stdint.h>\n+\n+/**\n+ * Enumeration zip_cc\n+ *\n+ * ZIP compression coding Enumeration\n+ * Enumerates ZIP_INST_S[CC].\n+ */\n+enum {\n+\tZIP_CC_DEFAULT = 0,\n+\tZIP_CC_DYN_HUFF,\n+\tZIP_CC_FIXED_HUFF,\n+\tZIP_CC_LZS\n+} zip_cc;\n+\n+/**\n+ * Register (NCB) zip_vq#_ena\n+ *\n+ * ZIP VF Queue Enable Register\n+ * If a queue is disabled, ZIP CTL stops fetching instructions from the queue.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct zip_vqx_ena_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_1_63 : 63;\n+\t\tuint64_t ena : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t ena : 1;\n+\t\tuint64_t reserved_1_63 : 63;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_vqx_ena_s cn; */\n+} zip_vqx_ena_t;\n+\n+/**\n+ * Register (NCB) zip_vq#_sbuf_addr\n+ *\n+ * ZIP VF Queue Starting Buffer Address Registers\n+ * These registers set the buffer parameters for the instruction queues.\n+ * When quiescent (i.e.\n+ * outstanding doorbell count is 0), it is safe to rewrite this register\n+ * to effectively reset the\n+ * command buffer state machine.\n+ * These registers must be programmed after software programs the\n+ * corresponding ZIP_QUE()_SBUF_CTL.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct zip_vqx_sbuf_addr_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_49_63 : 15;\n+\t\tuint64_t ptr : 42;\n+\t\tuint64_t off : 7;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t off : 7;\n+\t\tuint64_t ptr : 42;\n+\t\tuint64_t reserved_49_63 : 15;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_vqx_sbuf_addr_s cn; */\n+} zip_vqx_sbuf_addr_t;\n+\n+/**\n+ * Register (NCB) zip_que#_doorbell\n+ *\n+ * ZIP Queue Doorbell Registers\n+ * Doorbells for the ZIP instruction queues.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct zip_quex_doorbell_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\tuint64_t dbell_cnt : 20;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t dbell_cnt : 20;\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_quex_doorbell_s cn; */\n+} zip_quex_doorbell_t;\n+\n+/**\n+ * Structure zip_nptr_s\n+ *\n+ * ZIP Instruction Next-Chunk-Buffer Pointer (NPTR) Structure\n+ * This structure is used to chain all the ZIP instruction buffers\n+ * together. ZIP instruction buffers are managed\n+ * (allocated and released) by software.\n+ */\n+union zip_nptr_s {\n+\tuint64_t u;\n+\tstruct zip_nptr_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t addr : 64;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t addr : 64;\n+#endif /* Word 0 - End */\n+\t} s;\n+\t/* struct zip_nptr_s_s cn83xx; */\n+};\n+\n+/**\n+ * generic ptr address\n+ */\n+union zip_zptr_addr_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u;\n+\t/** generic ptr address */\n+\tstruct {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\tuint64_t addr : 64;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t addr : 64;\n+#endif /* Word 0 - End */\n+\t} s;\n+};\n+\n+/**\n+ * generic ptr ctl\n+ */\n+union zip_zptr_ctl_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u;\n+\t/** generic ptr ctl */\n+\tstruct {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\tuint64_t reserved_112_127 : 16;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\tuint64_t fw : 1;\n+\t\tuint64_t nc : 1;\n+\t\tuint64_t data_be : 1;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t data_be : 1;\n+\t\tuint64_t nc : 1;\n+\t\tuint64_t fw : 1;\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t reserved_112_127 : 16;\n+#endif /* Word 1 - End */\n+\t} s;\n+\n+};\n+\n+/**\n+ * Structure zip_inst_s\n+ *\n+ * ZIP Instruction Structure\n+ * Each ZIP instruction has 16 words (they are called IWORD0 to IWORD15\n+ * within the structure).\n+ */\n+union zip_inst_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u[16];\n+\t/** ZIP Instruction Structure */\n+\tstruct zip_inst_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** Done interrupt */\n+\t\tuint64_t doneint : 1;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\t/** Total output length */\n+\t\tuint64_t totaloutputlength : 24;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\t/** EXNUM */\n+\t\tuint64_t exn : 3;\n+\t\t/** HASH IV */\n+\t\tuint64_t iv : 1;\n+\t\t/** EXBITS */\n+\t\tuint64_t exbits : 7;\n+\t\t/** Hash more-in-file */\n+\t\tuint64_t hmif : 1;\n+\t\t/** Hash Algorithm and enable */\n+\t\tuint64_t halg : 3;\n+\t\t/** Sync flush*/\n+\t\tuint64_t sf : 1;\n+\t\t/** Compression speed/storage */\n+\t\tuint64_t ss : 2;\n+\t\t/** Compression coding */\n+\t\tuint64_t cc : 2;\n+\t\t/** End of input data */\n+\t\tuint64_t ef : 1;\n+\t\t/** Beginning of file */\n+\t\tuint64_t bf : 1;\n+\t\t// uint64_t reserved_3_4 : 2;\n+\t\t/** Comp/decomp operation */\n+\t\tuint64_t op : 2;\n+\t\t/** Data sactter */\n+\t\tuint64_t ds : 1;\n+\t\t/** Data gather */\n+\t\tuint64_t dg : 1;\n+\t\t/** History gather */\n+\t\tuint64_t hg : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t hg : 1;\n+\t\tuint64_t dg : 1;\n+\t\tuint64_t ds : 1;\n+\t\t//uint64_t reserved_3_4 : 2;\n+\t\tuint64_t op : 2;\n+\t\tuint64_t bf : 1;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t cc : 2;\n+\t\tuint64_t ss : 2;\n+\t\tuint64_t sf : 1;\n+\t\tuint64_t halg : 3;\n+\t\tuint64_t hmif : 1;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t iv : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\tuint64_t totaloutputlength : 24;\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\tuint64_t doneint : 1;\n+\n+#endif /* Word 0 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** History length */\n+\t\tuint64_t historylength : 16;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\t/** adler/crc32 checksum*/\n+\t\tuint64_t adlercrc32 : 32;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t adlercrc32 : 32;\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\tuint64_t historylength : 16;\n+#endif /* Word 1 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */\n+\t\t/** Decompression Context Pointer Address */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#else /* Word 2 - Little Endian */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#endif /* Word 2 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Decompression Context Pointer Control */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#else /* Word 3 - Little Endian */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#endif /* Word 3 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Decompression history pointer address */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#else /* Word 4 - Little Endian */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#endif /* Word 4 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Decompression history pointer control */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#else /* Word 5 - Little Endian */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#endif /* Word 5 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Input and compression history pointer address */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#else /* Word 6 - Little Endian */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#endif /* Word 6 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Input and compression history pointer control */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#else /* Word 7 - Little Endian */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#endif /* Word 7 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Output pointer address */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#else /* Word 8 - Little Endian */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#endif /* Word 8 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Output pointer control */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#else /* Word 9 - Little Endian */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#endif /* Word 9 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Result pointer address */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#else /* Word 10 - Little Endian */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#endif /* Word 10 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Result pointer control */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#else /* Word 11 - Little Endian */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#endif /* Word 11 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 12 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_812_831 : 20;\n+\t\t/** SSO guest group */\n+\t\tuint64_t ggrp : 10;\n+\t\t/** SSO tag type */\n+\t\tuint64_t tt : 2;\n+\t\t/** SSO tag */\n+\t\tuint64_t tag : 32;\n+#else /* Word 12 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t ggrp : 10;\n+\t\tuint64_t reserved_812_831 : 20;\n+#endif /* Word 12 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 13 - Big Endian */\n+\t\t/** Work queue entry pointer */\n+\t\tuint64_t wq_ptr : 64;\n+#else /* Word 13 - Little Endian */\n+\t\tuint64_t wq_ptr : 64;\n+#endif /* Word 13 - End */\n+\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** reserved */\n+\t\tuint64_t reserved_896_959 : 64;\n+#else /* Word 14 - Little Endian */\n+\t\tuint64_t reserved_896_959 : 64;\n+#endif /* Word 14 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD)\n+\t\t/** Hash structure pointer */\n+\t\tuint64_t hash_ptr : 64;\n+#else /* Word 15 - Little Endian */\n+\t\tuint64_t hash_ptr : 64;\n+#endif /* Word 15 - End */\n+\t} /** ZIP 88xx Instruction Structure */zip88xx;\n+\n+\t/** ZIP Instruction Structure */\n+\tstruct zip_inst_s_cn83xx {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** Done interrupt */\n+\t\tuint64_t doneint : 1;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\t/** Total output length */\n+\t\tuint64_t totaloutputlength : 24;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\t/** EXNUM */\n+\t\tuint64_t exn : 3;\n+\t\t/** HASH IV */\n+\t\tuint64_t iv : 1;\n+\t\t/** EXBITS */\n+\t\tuint64_t exbits : 7;\n+\t\t/** Hash more-in-file */\n+\t\tuint64_t hmif : 1;\n+\t\t/** Hash Algorithm and enable */\n+\t\tuint64_t halg : 3;\n+\t\t/** Sync flush*/\n+\t\tuint64_t sf : 1;\n+\t\t/** Compression speed/storage */\n+\t\tuint64_t ss : 2;\n+\t\t/** Compression coding */\n+\t\tuint64_t cc : 2;\n+\t\t/** End of input data */\n+\t\tuint64_t ef : 1;\n+\t\t/** Beginning of file */\n+\t\tuint64_t bf : 1;\n+\t\t/** Comp/decomp operation */\n+\t\tuint64_t op : 2;\n+\t\t/** Data sactter */\n+\t\tuint64_t ds : 1;\n+\t\t/** Data gather */\n+\t\tuint64_t dg : 1;\n+\t\t/** History gather */\n+\t\tuint64_t hg : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t hg : 1;\n+\t\tuint64_t dg : 1;\n+\t\tuint64_t ds : 1;\n+\t\tuint64_t op : 2;\n+\t\tuint64_t bf : 1;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t cc : 2;\n+\t\tuint64_t ss : 2;\n+\t\tuint64_t sf : 1;\n+\t\tuint64_t halg : 3;\n+\t\tuint64_t hmif : 1;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t iv : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t reserved_27_31 : 5;\n+\t\tuint64_t totaloutputlength : 24;\n+\t\tuint64_t reserved_56_62 : 7;\n+\t\tuint64_t doneint : 1;\n+#endif /* Word 0 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** History length */\n+\t\tuint64_t historylength : 16;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\t/** adler/crc32 checksum*/\n+\t\tuint64_t adlercrc32 : 32;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t adlercrc32 : 32;\n+\t\tuint64_t reserved_96_111 : 16;\n+\t\tuint64_t historylength : 16;\n+#endif /* Word 1 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */\n+\t\t/** Decompression Context Pointer Address */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#else /* Word 2 - Little Endian */\n+\t\tunion zip_zptr_addr_s ctx_ptr_addr;\n+#endif /* Word 2 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 3 - Big Endian */\n+\t\t/** Decompression Context Pointer Control */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#else /* Word 3 - Little Endian */\n+\t\tunion zip_zptr_ctl_s ctx_ptr_ctl;\n+#endif /* Word 3 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 4 - Big Endian */\n+\t\t/** Decompression history pointer address */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#else /* Word 4 - Little Endian */\n+\t\tunion zip_zptr_addr_s his_ptr_addr;\n+#endif /* Word 4 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 5 - Big Endian */\n+\t\t/** Decompression history pointer control */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#else /* Word 5 - Little Endian */\n+\t\tunion zip_zptr_ctl_s his_ptr_ctl;\n+#endif /* Word 5 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 6 - Big Endian */\n+\t\t/** Input and compression history pointer address */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#else /* Word 6 - Little Endian */\n+\t\tunion zip_zptr_addr_s inp_ptr_addr;\n+#endif /* Word 6 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 7 - Big Endian */\n+\t\t/** Input and compression history pointer control */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#else /* Word 7 - Little Endian */\n+\t\tunion zip_zptr_ctl_s inp_ptr_ctl;\n+#endif /* Word 7 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 8 - Big Endian */\n+\t\t/** Output pointer address */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#else /* Word 8 - Little Endian */\n+\t\tunion zip_zptr_addr_s out_ptr_addr;\n+#endif /* Word 8 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 9 - Big Endian */\n+\t\t/** Output pointer control */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#else /* Word 9 - Little Endian */\n+\t\tunion zip_zptr_ctl_s out_ptr_ctl;\n+#endif /* Word 9 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 10 - Big Endian */\n+\t\t/** Result pointer address */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#else /* Word 10 - Little Endian */\n+\t\tunion zip_zptr_addr_s res_ptr_addr;\n+#endif /* Word 10 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 11 - Big Endian */\n+\t\t/** Result pointer control */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#else /* Word 11 - Little Endian */\n+\t\tunion zip_zptr_ctl_s res_ptr_ctl;\n+#endif /* Word 11 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 12 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_812_831 : 20;\n+\t\t/** SSO guest group */\n+\t\tuint64_t ggrp : 10;\n+\t\t/** SSO tag type */\n+\t\tuint64_t tt : 2;\n+\t\t/** SSO tag */\n+\t\tuint64_t tag : 32;\n+#else /* Word 12 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t ggrp : 10;\n+\t\tuint64_t reserved_812_831 : 20;\n+#endif /* Word 12 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 13 - Big Endian */\n+\t\t/** Work queue entry pointer */\n+\t\tuint64_t wq_ptr : 64;\n+#else /* Word 13 - Little Endian */\n+\t\tuint64_t wq_ptr : 64;\n+#endif /* Word 13 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 14 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_896_959 : 64;\n+#else /* Word 14 - Little Endian */\n+\t\tuint64_t reserved_896_959 : 64;\n+#endif /* Word 14 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 15 - Big Endian */\n+\t\t/** Hash structure pointer */\n+\t\tuint64_t hash_ptr : 64;\n+#else /* Word 15 - Little Endian */\n+\t\tuint64_t hash_ptr : 64;\n+#endif /* Word 15 - End */\n+\t} /** ZIP 83xx Instruction Structure */s;\n+};\n+\n+/**\n+ * Structure zip_zres_s\n+ *\n+ * ZIP Result Structure\n+ * The ZIP coprocessor writes the result structure after it completes the\n+ * invocation. The result structure is exactly 24 bytes, and each invocation\n+ * of the ZIP coprocessor produces exactly one result structure.\n+ */\n+union zip_zres_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u[8];\n+\t/** ZIP Result Structure */\n+\tstruct zip_zres_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** crc32 checksum of uncompressed stream */\n+\t\tuint64_t crc32 : 32;\n+\t\t/** adler32 checksum of uncompressed stream*/\n+\t\tuint64_t adler32 : 32;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t adler32 : 32;\n+\t\tuint64_t crc32 : 32;\n+#endif /* Word 0 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** Total numer of Bytes produced in output stream */\n+\t\tuint64_t totalbyteswritten : 32;\n+\t\t/** Total number of bytes processed from the input stream */\n+\t\tuint64_t totalbytesread : 32;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t totalbytesread : 32;\n+\t\tuint64_t totalbyteswritten : 32;\n+#endif /* Word 1 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */\n+\t\t/** Total number of compressed input bits\n+\t\t * consumed to decompress all blocks in the file\n+\t\t */\n+\t\tuint64_t totalbitsprocessed : 32;\n+\t\t/** Done interrupt*/\n+\t\tuint64_t doneint : 1;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_155_158 : 4;\n+\t\t/** EXNUM */\n+\t\tuint64_t exn : 3;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_151 : 1;\n+\t\t/** EXBITS */\n+\t\tuint64_t exbits : 7;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_137_143 : 7;\n+\t\t/** End of file */\n+\t\tuint64_t ef : 1;\n+\t\t/** Completion/error code */\n+\t\tuint64_t compcode : 8;\n+#else /* Word 2 - Little Endian */\n+\t\tuint64_t compcode : 8;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t reserved_137_143 : 7;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t reserved_151 : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t reserved_155_158 : 4;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t totalbitsprocessed : 32;\n+#endif /* Word 2 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 3 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_253_255 : 3;\n+\t\t/** Hash length in bytes */\n+\t\tuint64_t hshlen : 61;\n+#else /* Word 3 - Little Endian */\n+\t\tuint64_t hshlen : 61;\n+\t\tuint64_t reserved_253_255 : 3;\n+#endif /* Word 3 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 4 - Big Endian */\n+\t\t/** Double-word 0 of computed hash */\n+\t\tuint64_t hash0 : 64;\n+#else /* Word 4 - Little Endian */\n+\t\tuint64_t hash0 : 64;\n+#endif /* Word 4 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 5 - Big Endian */\n+\t\t/** Double-word 1 of computed hash */\n+\t\tuint64_t hash1 : 64;\n+#else /* Word 5 - Little Endian */\n+\t\tuint64_t hash1 : 64;\n+#endif /* Word 5 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 6 - Big Endian */\n+\t\t/** Double-word 2 of computed hash */\n+\t\tuint64_t hash2 : 64;\n+#else /* Word 6 - Little Endian */\n+\t\tuint64_t hash2 : 64;\n+#endif /* Word 6 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 7 - Big Endian */\n+\t\t/** Double-word 3 of computed hash */\n+\t\tuint64_t hash3 : 64;\n+#else /* Word 7 - Little Endian */\n+\t\tuint64_t hash3 : 64;\n+#endif /* Word 7 - End */\n+\t} /** ZIP Result Structure */s;\n+\n+\t/* struct zip_zres_s_s cn83xx; */\n+};\n+\n+/**\n+ * Structure zip_zptr_s\n+ *\n+ * ZIP Generic Pointer Structure\n+ * This structure is the generic format of pointers in ZIP_INST_S.\n+ */\n+union zip_zptr_s {\n+\t/** This field can be used to set/clear all bits, or do bitwise\n+\t * operations over the entire structure.\n+\t */\n+\tuint64_t u[2];\n+\t/** ZIP Generic Pointer Structure */\n+\tstruct zip_zptr_s_s {\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */\n+\t\t/** Pointer to Data or scatter-gather list */\n+\t\tuint64_t addr : 64;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t addr : 64;\n+#endif /* Word 0 - End */\n+#if defined(__BIG_ENDIAN_BITFIELD) /* Word 1 - Big Endian */\n+\t\t/** reserved */\n+\t\tuint64_t reserved_112_127 : 16;\n+\t\t/** Length of Data or scatter-gather list*/\n+\t\tuint64_t length : 16;\n+\t\t/** reserved */\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\t/** Full-block write */\n+\t\tuint64_t fw : 1;\n+\t\t/** No cache allocation */\n+\t\tuint64_t nc : 1;\n+\t\t/** reserved */\n+\t\tuint64_t data_be : 1;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t data_be : 1;\n+\t\tuint64_t nc : 1;\n+\t\tuint64_t fw : 1;\n+\t\tuint64_t reserved_67_95 : 29;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t reserved_112_127 : 16;\n+#endif /* Word 1 - End */\n+\t} /** ZIP Generic Pointer Structure */s;\n+};\n+\n+/**\n+ * Enumeration zip_comp_e\n+ *\n+ * ZIP Completion Enumeration\n+ * Enumerates the values of ZIP_ZRES_S[COMPCODE].\n+ */\n+#define ZIP_COMP_E_NOTDONE (0)\n+#define ZIP_COMP_E_SUCCESS (1)\n+#define ZIP_COMP_E_DTRUNC (2)\n+#define ZIP_COMP_E_DSTOP (3)\n+#define ZIP_COMP_E_ITRUNC (4)\n+#define ZIP_COMP_E_RBLOCK (5)\n+#define ZIP_COMP_E_NLEN (6)\n+#define ZIP_COMP_E_BADCODE (7)\n+#define ZIP_COMP_E_BADCODE2 (8)\n+#define ZIP_COMP_E_ZERO_LEN (9)\n+#define ZIP_COMP_E_PARITY (0xa)\n+#define ZIP_COMP_E_FATAL (0xb)\n+#define ZIP_COMP_E_TIMEOUT (0xc)\n+#define ZIP_COMP_E_INSTR_ERR (0xd)\n+#define ZIP_COMP_E_HCTX_ERR (0xe)\n+#define ZIP_COMP_E_STOP (3)\n+\n+/**\n+ * Enumeration zip_op_e\n+ *\n+ * ZIP Operation Enumeration\n+ * Enumerates ZIP_INST_S[OP].\n+ * Internal:\n+ */\n+#define ZIP_OP_E_DECOMP (0)\n+#define ZIP_OP_E_NOCOMP (1)\n+#define ZIP_OP_E_COMP (2)\n+\n+/**\n+ * Enumeration zip compression levels\n+ *\n+ * ZIP Compression Level Enumeration\n+ * Enumerates ZIP_INST_S[SS].\n+ * Internal:\n+ */\n+#define ZIP_COMP_E_LEVEL_MAX (0)\n+#define ZIP_COMP_E_LEVEL_MED (1)\n+#define ZIP_COMP_E_LEVEL_LOW (2)\n+#define ZIP_COMP_E_LEVEL_MIN (3)\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+#endif\t/* _RTE_ZIP_REGS_H_ */\n+\ndiff --git a/drivers/compress/octeontx/meson.build b/drivers/compress/octeontx/meson.build\nnew file mode 100644\nindex 000000000..9145cb047\n--- /dev/null\n+++ b/drivers/compress/octeontx/meson.build\n@@ -0,0 +1,11 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Cavium, Inc\n+\n+name = 'octeontx_compress'\n+sources = files('zipvf.c', 'zip_pmd.c')\n+allow_experimental_apis = true\n+includes += include_directories('include')\n+deps += ['mempool_octeontx', 'bus_pci']\n+ext_deps += dep\n+\n+\ndiff --git a/drivers/compress/octeontx/rte_pmd_octeontx_version.map b/drivers/compress/octeontx/rte_pmd_octeontx_version.map\nnew file mode 100644\nindex 000000000..ad6e191e4\n--- /dev/null\n+++ b/drivers/compress/octeontx/rte_pmd_octeontx_version.map\n@@ -0,0 +1,3 @@\n+DPDK_18.08 {\n+\tlocal: *;\n+};\ndiff --git a/drivers/compress/octeontx/zip_pmd.c b/drivers/compress/octeontx/zip_pmd.c\nnew file mode 100644\nindex 000000000..2011db37e\n--- /dev/null\n+++ b/drivers/compress/octeontx/zip_pmd.c\n@@ -0,0 +1,120 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#include \"zipvf.h\"\n+#include <string.h>\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_cpuflags.h>\n+#include <rte_malloc.h>\n+\n+\n+struct rte_compressdev_ops octtx_zip_pmd_ops = {\n+\n+};\n+\n+static int\n+zip_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\tstruct rte_pci_device *pci_dev)\n+{\n+\tint ret = 0;\n+\tchar compressdev_name[RTE_COMPRESSDEV_NAME_MAX_LEN];\n+\tstruct rte_compressdev *compressdev;\n+\tstruct rte_compressdev_pmd_init_params init_params = {\n+\t\t\"\",\n+\t\trte_socket_id(),\n+\t};\n+\n+\tZIP_PMD_INFO(\"vendor_id=0x%x device_id=0x%x\",\n+\t\t\t(unsigned int)pci_dev->id.vendor_id,\n+\t\t\t(unsigned int)pci_dev->id.device_id);\n+\n+\trte_pci_device_name(&pci_dev->addr, compressdev_name,\n+\t\t\t sizeof(compressdev_name));\n+\n+\tcompressdev = rte_compressdev_pmd_create(compressdev_name,\n+\t\t&pci_dev->device, sizeof(struct zip_vf), &init_params);\n+\tif (compressdev == NULL) {\n+\t\tZIP_PMD_ERR(\"driver %s: create failed\", init_params.name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/*\n+\t * create only if proc_type is primary.\n+\t */\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\t/* create vf dev with given pmd dev id */\n+\t\tret = zipvf_create(compressdev);\n+\t\tif (ret < 0) {\n+\t\t\tZIP_PMD_ERR(\"Device creation failed\");\n+\t\t\trte_compressdev_pmd_destroy(compressdev);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tcompressdev->dev_ops = &octtx_zip_pmd_ops;\n+\t/* register rx/tx burst functions for data path */\n+\tcompressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n+\treturn ret;\n+}\n+\n+static int\n+zip_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_compressdev *compressdev;\n+\tchar compressdev_name[RTE_COMPRESSDEV_NAME_MAX_LEN];\n+\n+\tif (pci_dev == NULL) {\n+\t\tZIP_PMD_ERR(\" Invalid PCI Device\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\trte_pci_device_name(&pci_dev->addr, compressdev_name,\n+\t\t\tsizeof(compressdev_name));\n+\n+\tcompressdev = rte_compressdev_pmd_get_named_dev(compressdev_name);\n+\tif (compressdev == NULL)\n+\t\treturn -ENODEV;\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\tif (zipvf_destroy(compressdev) < 0)\n+\t\t\treturn -ENODEV;\n+\t}\n+\treturn rte_compressdev_pmd_destroy(compressdev);\n+}\n+\n+\n+\n+static struct rte_pci_id pci_id_octtx_zipvf_table[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\tPCI_DEVICE_ID_OCTEONTX_ZIPVF),\n+\t},\n+\t{\n+\t\t.device_id = 0\n+\t},\n+};\n+\n+/**\n+ * Structure that represents a PCI driver\n+ */\n+static struct rte_pci_driver octtx_zip_pmd = {\n+\t.id_table = pci_id_octtx_zipvf_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = zip_pci_probe,\n+\t.remove = zip_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(COMPRESSDEV_NAME_ZIP_PMD, octtx_zip_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(COMPRESSDEV_NAME_ZIP_PMD, pci_id_octtx_zipvf_table);\n+\n+RTE_INIT(octtx_zip_init_log);\n+\n+static void\n+octtx_zip_init_log(void)\n+{\n+\tocttx_zip_logtype_driver = rte_log_register(\"comp_octeontx_zip\");\n+\tif (octtx_zip_logtype_driver >= 0)\n+\t\trte_log_set_level(octtx_zip_logtype_driver, RTE_LOG_INFO);\n+}\n+\ndiff --git a/drivers/compress/octeontx/zipvf.c b/drivers/compress/octeontx/zipvf.c\nnew file mode 100644\nindex 000000000..a85d7f323\n--- /dev/null\n+++ b/drivers/compress/octeontx/zipvf.c\n@@ -0,0 +1,63 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#include \"zipvf.h\"\n+\n+uint64_t\n+zip_reg_read64(uint8_t *hw_addr, uint64_t offset)\n+{\n+\tuint8_t *base = hw_addr;\n+\treturn *(volatile uint64_t *)(base + offset);\n+}\n+\n+void\n+zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val)\n+{\n+\tuint8_t *base = hw_addr;\n+\t*(uint64_t *)(base + offset) = val;\n+}\n+\n+int\n+zipvf_create(struct rte_compressdev *compressdev)\n+{\n+\tstruct rte_pci_device *pdev = RTE_DEV_TO_PCI(compressdev->device);\n+\tstruct zip_vf *zipvf = NULL;\n+\tchar *dev_name = compressdev->data->name;\n+\tvoid *vbar0;\n+\tuint64_t reg;\n+\n+\tif (pdev->mem_resource[0].phys_addr == 0ULL)\n+\t\treturn -EIO;\n+\n+\tvbar0 = pdev->mem_resource[0].addr;\n+\tif (!vbar0) {\n+\t\tZIP_PMD_ERR(\"Failed to map BAR0 of %s\", dev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tzipvf = (struct zip_vf *)(compressdev->data->dev_private);\n+\n+\tif (!zipvf)\n+\t\treturn -ENOMEM;\n+\n+\tzipvf->vbar0 = vbar0;\n+\treg = zip_reg_read64(zipvf->vbar0, ZIP_VF_PF_MBOXX(0));\n+\t/* Storing domain in local to ZIP VF */\n+\tzipvf->dom_sdom = reg;\n+\tzipvf->pdev = pdev;\n+\tzipvf->max_nb_queue_pairs = ZIP_MAX_VF_QUEUE;\n+\treturn 0;\n+}\n+\n+int\n+zipvf_destroy(struct rte_compressdev *compressdev)\n+{\n+\tstruct zip_vf *vf = (struct zip_vf *)(compressdev->data->dev_private);\n+\n+\t/* Rewriting the domain_id in ZIP_VF_MBOX for app rerun */\n+\tzip_reg_write64(vf->vbar0, ZIP_VF_PF_MBOXX(0), vf->dom_sdom);\n+\n+\treturn 0;\n+}\n+\ndiff --git a/drivers/compress/octeontx/zipvf.h b/drivers/compress/octeontx/zipvf.h\nnew file mode 100644\nindex 000000000..36c44c8c5\n--- /dev/null\n+++ b/drivers/compress/octeontx/zipvf.h\n@@ -0,0 +1,111 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _RTE_OCTEONTX_ZIP_VF_H_\n+#define _RTE_OCTEONTX_ZIP_VF_H_\n+\n+#include <unistd.h>\n+#include <zip_regs.h>\n+#include <rte_bus_pci.h>\n+#include <rte_comp.h>\n+#include <rte_compressdev.h>\n+#include <rte_compressdev_pmd.h>\n+#include <rte_malloc.h>\n+#include <rte_memory.h>\n+#include <rte_spinlock.h>\n+\n+int octtx_zip_logtype_driver;\n+\n+/* ZIP VF Control/Status registers (CSRs): */\n+/* VF_BAR0: */\n+#define ZIP_VQ_ENA (0x10)\n+#define ZIP_VQ_SBUF_ADDR (0x20)\n+#define ZIP_VF_PF_MBOXX(x) (0x400 | (x)<<3)\n+#define ZIP_VQ_DOORBELL (0x1000)\n+\n+/**< Vendor ID */\n+#define PCI_VENDOR_ID_CAVIUM\t0x177D\n+/**< PCI device id of ZIP VF */\n+#define PCI_DEVICE_ID_OCTEONTX_ZIPVF\t0xA037\n+\n+/* maxmum number of zip vf devices */\n+#define ZIP_MAX_VFS 8\n+\n+/* max size of one chunk */\n+#define ZIP_MAX_CHUNK_SIZE\t8192\n+\n+/* each instruction is fixed 128 bytes */\n+#define ZIP_CMD_SIZE\t\t128\n+\n+#define ZIP_CMD_SIZE_WORDS\t(ZIP_CMD_SIZE >> 3) /* 16 64_bit words */\n+\n+/* size of next chunk buffer pointer */\n+#define ZIP_MAX_NCBP_SIZE\t8\n+\n+/* size of instruction queue in units of instruction size */\n+#define ZIP_MAX_NUM_CMDS\t((ZIP_MAX_CHUNK_SIZE - ZIP_MAX_NCBP_SIZE) / \\\n+\t\t\t\tZIP_CMD_SIZE) /* 63 */\n+\n+/* size of instruct queue in bytes */\n+#define ZIP_MAX_CMDQ_SIZE\t((ZIP_MAX_NUM_CMDS * ZIP_CMD_SIZE) + \\\n+\t\t\t\tZIP_MAX_NCBP_SIZE)/* ~8072ull */\n+\n+#define ZIP_BUF_SIZE\t256\n+\n+#define ZIP_SGPTR_ALIGN\t16\n+#define ZIP_CMDQ_ALIGN\t128\n+#define MAX_SG_LEN\t((ZIP_BUF_SIZE - ZIP_SGPTR_ALIGN) / sizeof(void *))\n+\n+/**< ZIP PMD specified queue pairs */\n+#define ZIP_MAX_VF_QUEUE\t1\n+\n+#define ZIP_ALIGN_ROUNDUP(x, _align) \\\n+\t((_align) * (((x) + (_align) - 1) / (_align)))\n+\n+/**< ZIP PMD device name */\n+#define COMPRESSDEV_NAME_ZIP_PMD\tcompress_octtx_zipvf\n+\n+#define ZIP_PMD_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, \\\n+\tocttx_zip_logtype_driver, \"%s(): \"fmt \"\\n\", \\\n+\t__func__, ##args)\n+\n+#define ZIP_PMD_INFO(fmt, args...) \\\n+\tZIP_PMD_LOG(INFO, fmt, ## args)\n+#define ZIP_PMD_ERR(fmt, args...) \\\n+\tZIP_PMD_LOG(ERR, fmt, ## args)\n+#define ZIP_PMD_WARN(fmt, args...) \\\n+\tZIP_PMD_LOG(WARNING, fmt, ## args)\n+\n+/**\n+ * ZIP VF device structure.\n+ */\n+struct zip_vf {\n+\tint vfid;\n+\t/* vf index */\n+\tstruct rte_pci_device *pdev;\n+\t/* pci device */\n+\tvoid *vbar0;\n+\t/* CSR base address for underlying BAR0 VF.*/\n+\tuint64_t dom_sdom;\n+\t/* Storing mbox domain and subdomain id for app rerun*/\n+\tuint32_t max_nb_queue_pairs;\n+\t/* pointer to device qps */\n+\tstruct rte_mempool *zip_mp;\n+\t/* pointer to pools */\n+} __rte_cache_aligned;\n+\n+int\n+zipvf_create(struct rte_compressdev *compressdev);\n+\n+int\n+zipvf_destroy(struct rte_compressdev *compressdev);\n+\n+uint64_t\n+zip_reg_read64(uint8_t *hw_addr, uint64_t offset);\n+\n+void\n+zip_reg_write64(uint8_t *hw_addr, uint64_t offset, uint64_t val);\n+\n+#endif /* _RTE_ZIP_VF_H_ */\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 87a0c80ff..4ef8cd90e 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -211,6 +211,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += -lrte_pmd_virtio_crypto\n endif # CONFIG_RTE_LIBRTE_CRYPTODEV\n \n ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y)\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF) += -lrte_pmd_octeontx_zip\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lrte_pmd_isal_comp\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ISAL) += -lisal\n endif # CONFIG_RTE_LIBRTE_COMPRESSDEV\n", "prefixes": [ "v2", "1/6" ] }