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GET /api/patches/41988/?format=api
{ "id": 41988, "url": "http://patches.dpdk.org/api/patches/41988/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/ed3b702573e5f562600f6a446e1bbcdadd90246c.1530295732.git.rahul.lakkireddy@chelsio.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<ed3b702573e5f562600f6a446e1bbcdadd90246c.1530295732.git.rahul.lakkireddy@chelsio.com>", "list_archive_url": "https://inbox.dpdk.org/dev/ed3b702573e5f562600f6a446e1bbcdadd90246c.1530295732.git.rahul.lakkireddy@chelsio.com", "date": "2018-06-29T18:12:16", "name": "[1/9] net/cxgbe: query firmware for HASH filter resources", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6976676dfb62bbaac495c1b5ad7dda3725e4d906", "submitter": { "id": 241, "url": "http://patches.dpdk.org/api/people/241/?format=api", "name": "Rahul Lakkireddy", "email": "rahul.lakkireddy@chelsio.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/ed3b702573e5f562600f6a446e1bbcdadd90246c.1530295732.git.rahul.lakkireddy@chelsio.com/mbox/", "series": [ { "id": 331, "url": "http://patches.dpdk.org/api/series/331/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=331", "date": "2018-06-29T18:12:15", "name": "net/cxgbe: add support for offloading flows to HASH region", "version": 1, "mbox": "http://patches.dpdk.org/series/331/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/41988/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/41988/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1A8761B910;\n\tFri, 29 Jun 2018 20:13:37 +0200 (CEST)", "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n\tby dpdk.org (Postfix) with ESMTP id 2F8071B903\n\tfor <dev@dpdk.org>; Fri, 29 Jun 2018 20:13:35 +0200 (CEST)", "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n\tby stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w5TIDT11028614; \n\tFri, 29 Jun 2018 11:13:30 -0700" ], "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>", "To": "dev@dpdk.org", "Cc": "shaguna@chelsio.com, indranil@chelsio.com, nirranjan@chelsio.com", "Date": "Fri, 29 Jun 2018 23:42:16 +0530", "Message-Id": "<ed3b702573e5f562600f6a446e1bbcdadd90246c.1530295732.git.rahul.lakkireddy@chelsio.com>", "X-Mailer": "git-send-email 2.5.3", "In-Reply-To": [ "<cover.1530295732.git.rahul.lakkireddy@chelsio.com>", "<cover.1530295732.git.rahul.lakkireddy@chelsio.com>" ], "References": [ "<cover.1530295732.git.rahul.lakkireddy@chelsio.com>", "<cover.1530295732.git.rahul.lakkireddy@chelsio.com>" ], "Subject": "[dpdk-dev] [PATCH 1/9] net/cxgbe: query firmware for HASH filter\n\tresources", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shagun Agrawal <shaguna@chelsio.com>\n\nFetch available HASH filter resources and allocate table for managing\nthem. Currently only supported on Chelsio T6 family of NICs.\n\nSigned-off-by: Shagun Agrawal <shaguna@chelsio.com>\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\n---\n drivers/net/cxgbe/base/common.h | 7 ++++++\n drivers/net/cxgbe/base/t4_regs.h | 9 ++++++++\n drivers/net/cxgbe/cxgbe_compat.h | 12 ++++++++++\n drivers/net/cxgbe/cxgbe_filter.c | 38 ++++++++++++++++++++++++++++++++\n drivers/net/cxgbe/cxgbe_filter.h | 1 +\n drivers/net/cxgbe/cxgbe_main.c | 47 ++++++++++++++++++++++++++++++++++++----\n drivers/net/cxgbe/cxgbe_ofld.h | 26 ++++++++++++++++++++--\n 7 files changed, 134 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h\nindex e524f7931..a276a1ef5 100644\n--- a/drivers/net/cxgbe/base/common.h\n+++ b/drivers/net/cxgbe/base/common.h\n@@ -251,6 +251,8 @@ struct adapter_params {\n \tunsigned char nports; /* # of ethernet ports */\n \tunsigned char portvec;\n \n+\tunsigned char hash_filter;\n+\n \tenum chip_type chip; /* chip code */\n \tstruct arch_specific_params arch; /* chip specific params */\n \n@@ -314,6 +316,11 @@ static inline int is_pf4(struct adapter *adap)\n #define for_each_port(adapter, iter) \\\n \tfor (iter = 0; iter < (adapter)->params.nports; ++iter)\n \n+static inline int is_hashfilter(const struct adapter *adap)\n+{\n+\treturn adap->params.hash_filter;\n+}\n+\n void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);\n void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,\n \t\t\t unsigned int mask, unsigned int val);\ndiff --git a/drivers/net/cxgbe/base/t4_regs.h b/drivers/net/cxgbe/base/t4_regs.h\nindex fd8f9cf27..a1f6208ea 100644\n--- a/drivers/net/cxgbe/base/t4_regs.h\n+++ b/drivers/net/cxgbe/base/t4_regs.h\n@@ -937,3 +937,12 @@\n #define M_REV 0xfU\n #define V_REV(x) ((x) << S_REV)\n #define G_REV(x) (((x) >> S_REV) & M_REV)\n+\n+/* registers for module LE */\n+#define A_LE_DB_CONFIG 0x19c04\n+\n+#define S_HASHEN 20\n+#define V_HASHEN(x) ((x) << S_HASHEN)\n+#define F_HASHEN V_HASHEN(1U)\n+\n+#define A_LE_DB_TID_HASHBASE 0x19df8\ndiff --git a/drivers/net/cxgbe/cxgbe_compat.h b/drivers/net/cxgbe/cxgbe_compat.h\nindex 779bcf165..609156499 100644\n--- a/drivers/net/cxgbe/cxgbe_compat.h\n+++ b/drivers/net/cxgbe/cxgbe_compat.h\n@@ -250,4 +250,16 @@ static inline void writel_relaxed(unsigned int val, volatile void __iomem *addr)\n \trte_write32_relaxed(val, addr);\n }\n \n+/*\n+ * Multiplies an integer by a fraction, while avoiding unnecessary\n+ * overflow or loss of precision.\n+ */\n+#define mult_frac(x, numer, denom)( \\\n+{ \\\n+\ttypeof(x) quot = (x) / (denom); \\\n+\ttypeof(x) rem = (x) % (denom); \\\n+\t(quot * (numer)) + ((rem * (numer)) / (denom)); \\\n+} \\\n+)\n+\n #endif /* _CXGBE_COMPAT_H_ */\ndiff --git a/drivers/net/cxgbe/cxgbe_filter.c b/drivers/net/cxgbe/cxgbe_filter.c\nindex d098b9308..a5d20d164 100644\n--- a/drivers/net/cxgbe/cxgbe_filter.c\n+++ b/drivers/net/cxgbe/cxgbe_filter.c\n@@ -7,6 +7,44 @@\n #include \"t4_regs.h\"\n #include \"cxgbe_filter.h\"\n \n+/**\n+ * Initialize Hash Filters\n+ */\n+int init_hash_filter(struct adapter *adap)\n+{\n+\tunsigned int n_user_filters;\n+\tunsigned int user_filter_perc;\n+\tint ret;\n+\tu32 params[7], val[7];\n+\n+#define FW_PARAM_DEV(param) \\\n+\t(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \\\n+\tV_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))\n+\n+#define FW_PARAM_PFVF(param) \\\n+\t(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \\\n+\tV_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \\\n+\tV_FW_PARAMS_PARAM_Y(0) | \\\n+\tV_FW_PARAMS_PARAM_Z(0))\n+\n+\tparams[0] = FW_PARAM_DEV(NTID);\n+\tret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,\n+\t\t\t params, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tadap->tids.ntids = val[0];\n+\tadap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);\n+\n+\tuser_filter_perc = 100;\n+\tn_user_filters = mult_frac(adap->tids.nftids,\n+\t\t\t\t user_filter_perc,\n+\t\t\t\t 100);\n+\n+\tadap->tids.nftids = n_user_filters;\n+\tadap->params.hash_filter = 1;\n+\treturn 0;\n+}\n+\n /**\n * Validate if the requested filter specification can be set by checking\n * if the requested features have been enabled\ndiff --git a/drivers/net/cxgbe/cxgbe_filter.h b/drivers/net/cxgbe/cxgbe_filter.h\nindex 4df37b9cd..6758a1879 100644\n--- a/drivers/net/cxgbe/cxgbe_filter.h\n+++ b/drivers/net/cxgbe/cxgbe_filter.h\n@@ -220,6 +220,7 @@ int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,\n \t\t struct ch_filter_specification *fs,\n \t\t struct filter_ctx *ctx);\n int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family);\n+int init_hash_filter(struct adapter *adap);\n int validate_filter(struct adapter *adap, struct ch_filter_specification *fs);\n int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,\n \t\t\t u64 *c, bool get_byte);\ndiff --git a/drivers/net/cxgbe/cxgbe_main.c b/drivers/net/cxgbe/cxgbe_main.c\nindex 21ad380ae..c692939db 100644\n--- a/drivers/net/cxgbe/cxgbe_main.c\n+++ b/drivers/net/cxgbe/cxgbe_main.c\n@@ -287,24 +287,43 @@ static int tid_init(struct tid_info *t)\n {\n \tsize_t size;\n \tunsigned int ftid_bmap_size;\n+\tunsigned int natids = t->natids;\n \tunsigned int max_ftids = t->nftids;\n \n \tftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);\n \tsize = t->ntids * sizeof(*t->tid_tab) +\n-\t\tmax_ftids * sizeof(*t->ftid_tab);\n+\t\tmax_ftids * sizeof(*t->ftid_tab) +\n+\t\tnatids * sizeof(*t->atid_tab);\n \n \tt->tid_tab = t4_os_alloc(size);\n \tif (!t->tid_tab)\n \t\treturn -ENOMEM;\n \n-\tt->ftid_tab = (struct filter_entry *)&t->tid_tab[t->ntids];\n+\tt->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];\n+\tt->ftid_tab = (struct filter_entry *)&t->tid_tab[t->natids];\n \tt->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);\n \tif (!t->ftid_bmap_array) {\n \t\ttid_free(t);\n \t\treturn -ENOMEM;\n \t}\n \n+\tt4_os_lock_init(&t->atid_lock);\n \tt4_os_lock_init(&t->ftid_lock);\n+\n+\tt->afree = NULL;\n+\tt->atids_in_use = 0;\n+\trte_atomic32_init(&t->tids_in_use);\n+\trte_atomic32_set(&t->tids_in_use, 0);\n+\trte_atomic32_init(&t->conns_in_use);\n+\trte_atomic32_set(&t->conns_in_use, 0);\n+\n+\t/* Setup the free list for atid_tab and clear the stid bitmap. */\n+\tif (natids) {\n+\t\twhile (--natids)\n+\t\t\tt->atid_tab[natids - 1].next = &t->atid_tab[natids];\n+\t\tt->afree = t->atid_tab;\n+\t}\n+\n \tt->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,\n \t\t\t\t ftid_bmap_size);\n \tif (!t->ftid_bmap) {\n@@ -784,8 +803,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)\n \t * This will allow the firmware to optimize aspects of the hardware\n \t * configuration which will result in improved performance.\n \t */\n-\tcaps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |\n-\t\t\t\t\t FW_CAPS_CONFIG_NIC_ETHOFLD));\n+\tcaps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);\n \tcaps_cmd.toecaps = 0;\n \tcaps_cmd.iscsicaps = 0;\n \tcaps_cmd.rdmacaps = 0;\n@@ -990,6 +1008,12 @@ static int adap_init0(struct adapter *adap)\n \tif (ret < 0)\n \t\tgoto bye;\n \n+\tif ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&\n+\t is_t6(adap->params.chip)) {\n+\t\tif (init_hash_filter(adap) < 0)\n+\t\t\tgoto bye;\n+\t}\n+\n \t/* query tid-related parameters */\n \tparams[0] = FW_PARAM_DEV(NTID);\n \tret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,\n@@ -997,6 +1021,7 @@ static int adap_init0(struct adapter *adap)\n \tif (ret < 0)\n \t\tgoto bye;\n \tadap->tids.ntids = val[0];\n+\tadap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);\n \n \t/* If we're running on newer firmware, let it know that we're\n \t * prepared to deal with encapsulated CPL messages. Older\n@@ -1653,6 +1678,20 @@ int cxgbe_probe(struct adapter *adapter)\n \t\t\t \"filter support disabled. Continuing\\n\");\n \t}\n \n+\tif (is_hashfilter(adapter)) {\n+\t\tif (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {\n+\t\t\tu32 hash_base, hash_reg;\n+\n+\t\t\thash_reg = A_LE_DB_TID_HASHBASE;\n+\t\t\thash_base = t4_read_reg(adapter, hash_reg);\n+\t\t\tadapter->tids.hash_base = hash_base / 4;\n+\t\t}\n+\t} else {\n+\t\t/* Disable hash filtering support */\n+\t\tdev_warn(adapter,\n+\t\t\t \"Maskless filter support disabled. Continuing\\n\");\n+\t}\n+\n \terr = init_rss(adapter);\n \tif (err)\n \t\tgoto out_free;\ndiff --git a/drivers/net/cxgbe/cxgbe_ofld.h b/drivers/net/cxgbe/cxgbe_ofld.h\nindex 9f382f659..e97c42469 100644\n--- a/drivers/net/cxgbe/cxgbe_ofld.h\n+++ b/drivers/net/cxgbe/cxgbe_ofld.h\n@@ -10,6 +10,16 @@\n \n #include \"cxgbe_filter.h\"\n \n+/*\n+ * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.\n+ */\n+#define MAX_ATIDS 8192U\n+\n+union aopen_entry {\n+\tvoid *data;\n+\tunion aopen_entry *next;\n+};\n+\n /*\n * Holds the size, base address, free list start, etc of filter TID.\n * The tables themselves are allocated dynamically.\n@@ -18,10 +28,22 @@ struct tid_info {\n \tvoid **tid_tab;\n \tunsigned int ntids;\n \tstruct filter_entry *ftid_tab;\t/* Normal filters */\n+\tunion aopen_entry *atid_tab;\n \tstruct rte_bitmap *ftid_bmap;\n \tuint8_t *ftid_bmap_array;\n-\tunsigned int nftids;\n-\tunsigned int ftid_base;\n+\tunsigned int nftids, natids;\n+\tunsigned int ftid_base, hash_base;\n+\n+\tunion aopen_entry *afree;\n+\tunsigned int atids_in_use;\n+\n+\t/* TIDs in the TCAM */\n+\trte_atomic32_t tids_in_use;\n+\t/* TIDs in the HASH */\n+\trte_atomic32_t hash_tids_in_use;\n+\trte_atomic32_t conns_in_use;\n+\n+\trte_spinlock_t atid_lock __rte_cache_aligned;\n \trte_spinlock_t ftid_lock;\n };\n #endif /* _CXGBE_OFLD_H_ */\n", "prefixes": [ "1/9" ] }