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GET /api/patches/41820/?format=api
{ "id": 41820, "url": "http://patches.dpdk.org/api/patches/41820/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1530190137-17848-1-git-send-email-motih@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1530190137-17848-1-git-send-email-motih@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1530190137-17848-1-git-send-email-motih@mellanox.com", "date": "2018-06-28T12:48:57", "name": "[v3] net/mlx4: support hardware TSO", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "889ea552939e0d5cb02d9c9ae98dac5ae83ff34b", "submitter": { "id": 748, "url": "http://patches.dpdk.org/api/people/748/?format=api", "name": "Moti Haimovsky", "email": "motih@mellanox.com" }, "delegate": { "id": 6624, "url": "http://patches.dpdk.org/api/users/6624/?format=api", "username": "shahafs", "first_name": "Shahaf", "last_name": "Shuler", "email": "shahafs@mellanox.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1530190137-17848-1-git-send-email-motih@mellanox.com/mbox/", "series": [ { "id": 291, "url": "http://patches.dpdk.org/api/series/291/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=291", "date": "2018-06-28T12:48:57", "name": "[v3] net/mlx4: support hardware TSO", "version": 3, "mbox": "http://patches.dpdk.org/series/291/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/41820/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/41820/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5283C5B3A;\n\tThu, 28 Jun 2018 14:50:06 +0200 (CEST)", "from EUR03-VE1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr50070.outbound.protection.outlook.com [40.107.5.70])\n\tby dpdk.org (Postfix) with ESMTP id AC2BC378B\n\tfor <dev@dpdk.org>; Thu, 28 Jun 2018 14:50:04 +0200 (CEST)", "from localhost.localdomain (37.142.13.130) by\n\tDB7PR05MB4443.eurprd05.prod.outlook.com (2603:10a6:5:1b::20) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.884.23; Thu, 28 Jun 2018 12:50:00 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; 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PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(3002001)(3231254)(944501410)(52105095)(93006095)(93001095)(10201501046)(6055026)(149027)(150027)(6041310)(20161123558120)(20161123562045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(20161123560045)(6072148)(201708071742011)(7699016);\n\tSRVR:DB7PR05MB4443; BCL:0; PCL:0; RULEID:; SRVR:DB7PR05MB4443; ", "X-Forefront-PRVS": "0717E25089", "X-Forefront-Antispam-Report": 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"QDbZJ9GsSuKYE0FXl75wMSqI+BnH8qiA8P618U0UFaktmRyv8w5hoHNju6x2dMYYgR9oh4Tonlnj89nTmN+9/vocBr8bedTMvrEeuZhGH/oi69mS5jrYC6VfFRGZy5Wej6U9k3uP7L1MG517DbzimF3hTlB/SrGyYDDOn9xKr4nvdzk7TR/ewrb+SSBFMfMYyhH/JVnZMLbYUL30CN67nJ+NhmVMA2qgY9wRkvnIWXTscLXV+O4X1lVAIQPrMW2qi9sSQL5gsx/tbgzsIp1FRev4uBJyMZp0gsZnjHmcsM+9fbnGZZlUgPIARKgmsAwwasfD8UponpjkNB9AApjewyb44gcAMNkLvvoDOMch/ZA=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Jun 2018 12:50:00.8911\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "247bcc58-3407-4337-f56f-08d5dcf5aa06", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "a652971c-7d2e-4d9b-a6a4-d149256f461b", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB7PR05MB4443", "Subject": "[dpdk-dev] [PATCH v3] net/mlx4: support hardware TSO", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Implement support for hardware TSO.\n\nSigned-off-by: Moti Haimovsky <motih@mellanox.com>\n---\nv3:\n* Fixed compilation errors in compilers without GNU C extensions\n caused by a declaration of zero-length array in the code.\nin reply to\n1530187032-6489-1-git-send-email-motih@mellanox.com\n\nv2:\n* Fixed coding style warning.\nin reply to\n1530184583-30166-1-git-send-email-motih@mellanox.com\n\nv1:\n* Fixed coding style warnings.\nin reply to\n1530181779-19716-1-git-send-email-motih@mellanox.com\n---\n doc/guides/nics/features/mlx4.ini | 1 +\n doc/guides/nics/mlx4.rst | 3 +\n drivers/net/mlx4/mlx4.c | 16 ++\n drivers/net/mlx4/mlx4.h | 5 +\n drivers/net/mlx4/mlx4_prm.h | 12 ++\n drivers/net/mlx4/mlx4_rxtx.c | 372 +++++++++++++++++++++++++++++++++++++-\n drivers/net/mlx4/mlx4_rxtx.h | 2 +-\n drivers/net/mlx4/mlx4_txq.c | 8 +-\n 8 files changed, 415 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/mlx4.ini b/doc/guides/nics/features/mlx4.ini\nindex f6efd21..98a3f61 100644\n--- a/doc/guides/nics/features/mlx4.ini\n+++ b/doc/guides/nics/features/mlx4.ini\n@@ -13,6 +13,7 @@ Queue start/stop = Y\n MTU update = Y\n Jumbo frame = Y\n Scattered Rx = Y\n+TSO = Y\n Promiscuous mode = Y\n Allmulticast mode = Y\n Unicast MAC filter = Y\ndiff --git a/doc/guides/nics/mlx4.rst b/doc/guides/nics/mlx4.rst\nindex 491106a..12adaeb 100644\n--- a/doc/guides/nics/mlx4.rst\n+++ b/doc/guides/nics/mlx4.rst\n@@ -142,6 +142,9 @@ Limitations\n The ability to enable/disable CRC stripping requires OFED version\n 4.3-1.5.0.0 and above or rdma-core version v18 and above.\n \n+- TSO (Transmit Segmentation Offload) is supported in OFED version\n+ 4.4 and above or in rdma-core version v18 and above.\n+\n Prerequisites\n -------------\n \ndiff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c\nindex d151a90..61b7844 100644\n--- a/drivers/net/mlx4/mlx4.c\n+++ b/drivers/net/mlx4/mlx4.c\n@@ -519,6 +519,8 @@ struct mlx4_conf {\n \t\t.ports.present = 0,\n \t};\n \tunsigned int vf;\n+\tstruct rte_mbuf mbuf;\n+\tuint64_t size_test = UINT_MAX;\n \tint i;\n \n \t(void)pci_drv;\n@@ -677,6 +679,20 @@ struct mlx4_conf {\n \t\t\t\t\tIBV_RAW_PACKET_CAP_SCATTER_FCS);\n \t\tDEBUG(\"FCS stripping toggling is %ssupported\",\n \t\t priv->hw_fcs_strip ? \"\" : \"not \");\n+\t\t/*\n+\t\t * No TSO SIZE is defined in DPDK, need to figure it out\n+\t\t * in order to see if we can support it.\n+\t\t */\n+\t\tmbuf.tso_segsz = size_test;\n+\t\tpriv->tso =\n+\t\t\t((device_attr_ex.tso_caps.max_tso >= mbuf.tso_segsz) &&\n+\t\t\t (device_attr_ex.tso_caps.supported_qpts &\n+\t\t\t (1 << IBV_QPT_RAW_PACKET)));\n+\t\tif (priv->tso)\n+\t\t\tpriv->tso_max_payload_sz =\n+\t\t\t\t\tdevice_attr_ex.tso_caps.max_tso;\n+\t\tDEBUG(\"TSO is %ssupported\",\n+\t\t priv->tso ? \"\" : \"not \");\n \t\t/* Configure the first MAC address by default. */\n \t\terr = mlx4_get_mac(priv, &mac.addr_bytes);\n \t\tif (err) {\ndiff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h\nindex 300cb4d..742d741 100644\n--- a/drivers/net/mlx4/mlx4.h\n+++ b/drivers/net/mlx4/mlx4.h\n@@ -47,6 +47,9 @@\n /** Interrupt alarm timeout value in microseconds. */\n #define MLX4_INTR_ALARM_TIMEOUT 100000\n \n+/* Maximum Packet headers size (L2+L3+L4) for TSO. */\n+#define MLX4_MAX_TSO_HEADER 192 // TODO: find the real value\n+\n /** Port parameter. */\n #define MLX4_PMD_PORT_KVARG \"port\"\n \n@@ -90,6 +93,8 @@ struct priv {\n \tuint32_t hw_csum:1; /**< Checksum offload is supported. */\n \tuint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */\n \tuint32_t hw_fcs_strip:1; /**< FCS stripping toggling is supported. */\n+\tuint32_t tso:1; /**< Transmit segmentation offload is supported */\n+\tuint32_t tso_max_payload_sz; /* Max TSO payload size being supported */\n \tuint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */\n \tstruct rte_intr_handle intr_handle; /**< Port interrupt handle. */\n \tstruct mlx4_drop *drop; /**< Shared resources for drop flow rules. */\ndiff --git a/drivers/net/mlx4/mlx4_prm.h b/drivers/net/mlx4/mlx4_prm.h\nindex e15a3c1..0484878 100644\n--- a/drivers/net/mlx4/mlx4_prm.h\n+++ b/drivers/net/mlx4/mlx4_prm.h\n@@ -40,6 +40,7 @@\n /* Work queue element (WQE) flags. */\n #define MLX4_WQE_CTRL_IIP_HDR_CSUM (1 << 28)\n #define MLX4_WQE_CTRL_IL4_HDR_CSUM (1 << 27)\n+#define MLX4_WQE_CTRL_RR (1 << 6)\n \n /* CQE checksum flags. */\n enum {\n@@ -97,6 +98,17 @@ struct mlx4_cq {\n \tint arm_sn; /**< Rx event counter. */\n };\n \n+/*\n+ * WQE LSO segment structure.\n+ * Defined here as backward compatibility for rdma-core v17 and below.\n+ * Similar definition is found in infiniband/mlx4dv.h in rdma-core v18\n+ * and above.\n+ */\n+struct mlx4_wqe_lso_seg_ {\n+\t__be32 mss_hdr_size;\n+\t__be32 header[];\n+};\n+\n /**\n * Retrieve a CQE entry from a CQ.\n *\ndiff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c\nindex a92da66..992d193 100644\n--- a/drivers/net/mlx4/mlx4_rxtx.c\n+++ b/drivers/net/mlx4/mlx4_rxtx.c\n@@ -38,10 +38,25 @@\n * DWORD (32 byte) of a TXBB.\n */\n struct pv {\n-\tvolatile struct mlx4_wqe_data_seg *dseg;\n+\tunion {\n+\t\tvolatile struct mlx4_wqe_data_seg *dseg;\n+\t\tvolatile uint32_t *dst;\n+\t};\n \tuint32_t val;\n };\n \n+/** A helper struct for TSO packet handling. */\n+struct tso_info {\n+\t/* Total size of the WQE including padding */\n+\tuint32_t wqe_size;\n+\t/* size of TSO header to prepend to each packet to send */\n+\tuint16_t tso_header_sz;\n+\t/* Total size of the TSO entry in the WQE. */\n+\tuint16_t wqe_tso_seg_size;\n+\t/* Raw WQE size in units of 16 Bytes and without padding. */\n+\tuint8_t fence_size;\n+};\n+\n /** A table to translate Rx completion flags to packet type. */\n uint32_t mlx4_ptype_table[0x100] __rte_cache_aligned = {\n \t/*\n@@ -377,6 +392,349 @@ struct pv {\n }\n \n /**\n+ * Obtain and calculate TSO information needed for assembling a TSO WQE.\n+ *\n+ * @param buf\n+ * Pointer to the first packet mbuf.\n+ * @param txq\n+ * Pointer to Tx queue structure.\n+ * @param tinfo\n+ * Pointer to a structure to fill the info with.\n+ *\n+ * @return\n+ * 0 on success, negative value upon error.\n+ */\n+static inline int\n+mlx4_tx_burst_tso_get_params(struct rte_mbuf *buf,\n+\t\t\t struct txq *txq,\n+\t\t\t struct tso_info *tinfo)\n+{\n+\tstruct mlx4_sq *sq = &txq->msq;\n+\tconst uint8_t tunneled = txq->priv->hw_csum_l2tun &&\n+\t\t\t\t (buf->ol_flags & PKT_TX_TUNNEL_MASK);\n+\n+\ttinfo->tso_header_sz = buf->l2_len + buf->l3_len + buf->l4_len;\n+\tif (tunneled)\n+\t\ttinfo->tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;\n+\tif (unlikely(buf->tso_segsz == 0 || tinfo->tso_header_sz == 0)) {\n+\t\tDEBUG(\"%p: Invalid TSO parameters\", (void *)txq);\n+\t\treturn -EINVAL;\n+\t}\n+\t/* First segment must contain all TSO headers. */\n+\tif (unlikely(tinfo->tso_header_sz > MLX4_MAX_TSO_HEADER) ||\n+\t\t tinfo->tso_header_sz > buf->data_len) {\n+\t\tDEBUG(\"%p: Invalid TSO header length\", (void *)txq);\n+\t\treturn -EINVAL;\n+\t}\n+\t/*\n+\t * Calculate the WQE TSO segment size\n+\t * Note:\n+\t * 1. An LSO segment must be padded such that the subsequent data\n+\t * segment is 16-byte aligned.\n+\t * 2. The start address of the TSO segment is always 16 Bytes aligned.\n+\t */\n+\ttinfo->wqe_tso_seg_size = RTE_ALIGN(sizeof(struct mlx4_wqe_lso_seg_) +\n+\t\t\t\t\t tinfo->tso_header_sz,\n+\t\t\t\t\t sizeof(struct mlx4_wqe_data_seg));\n+\ttinfo->fence_size = ((sizeof(struct mlx4_wqe_ctrl_seg) +\n+\t\t\t tinfo->wqe_tso_seg_size) >> MLX4_SEG_SHIFT) +\n+\t\t\t buf->nb_segs;\n+\ttinfo->wqe_size =\n+\t\tRTE_ALIGN((uint32_t)(tinfo->fence_size << MLX4_SEG_SHIFT),\n+\t\t\t MLX4_TXBB_SIZE);\n+\t/* Validate WQE size and WQE space in the send queue. */\n+\tif (sq->remain_size < tinfo->wqe_size ||\n+\t tinfo->wqe_size > MLX4_MAX_WQE_SIZE)\n+\t\treturn -ENOMEM;\n+\treturn 0;\n+}\n+\n+/**\n+ * Fill the TSO WQE data segments with info on buffers to transmit .\n+ *\n+ * @param buf\n+ * Pointer to the first packet mbuf.\n+ * @param txq\n+ * Pointer to Tx queue structure.\n+ * @param tinfo\n+ * Pointer to TSO info to use.\n+ * @param dseg\n+ * Pointer to the first data segment in the TSO WQE.\n+ * @param pv\n+ * Pointer to a stash area for saving the first 32bit word of each TXBB\n+ * used for the TSO WQE.\n+ * @param pv_counter\n+ * Current location in the stash.\n+ *\n+ * @return\n+ * 0 on success, negative value upon error.\n+ */\n+static inline int\n+mlx4_tx_burst_fill_tso_segs(struct rte_mbuf *buf,\n+\t\t\t struct txq *txq,\n+\t\t\t const struct tso_info *tinfo,\n+\t\t\t volatile struct mlx4_wqe_data_seg *dseg,\n+\t\t\t struct pv *pv, int *pv_counter)\n+{\n+\tuint32_t lkey;\n+\tint nb_segs = buf->nb_segs;\n+\tint nb_segs_txbb;\n+\tstruct mlx4_sq *sq = &txq->msq;\n+\tstruct rte_mbuf *sbuf = buf;\n+\tuint16_t sb_of = tinfo->tso_header_sz;\n+\tuint16_t data_len;\n+\n+\twhile (nb_segs > 0) {\n+\t\t/* Wrap dseg if it points at the end of the queue. */\n+\t\tif ((volatile uint8_t *)dseg >= sq->eob)\n+\t\t\tdseg = (volatile struct mlx4_wqe_data_seg *)\n+\t\t\t\t\t(volatile uint8_t *)dseg - sq->size;\n+\t\t/* how many dseg entries do we have in the current TXBB ? */\n+\t\tnb_segs_txbb =\n+\t\t\t(MLX4_TXBB_SIZE / sizeof(struct mlx4_wqe_data_seg)) -\n+\t\t\t((uintptr_t)dseg & (MLX4_TXBB_SIZE - 1)) /\n+\t\t\tsizeof(struct mlx4_wqe_data_seg);\n+\t\tswitch (nb_segs_txbb) {\n+\t\tcase 4:\n+\t\t\t/* Memory region key for this memory pool. */\n+\t\t\tlkey = mlx4_tx_mb2mr(txq, sbuf);\n+\t\t\tif (unlikely(lkey == (uint32_t)-1))\n+\t\t\t\tgoto lkey_err;\n+\t\t\tdseg->addr =\n+\t\t\t rte_cpu_to_be_64(rte_pktmbuf_mtod_offset(sbuf,\n+\t\t\t\t\t\t\t\t uintptr_t,\n+\t\t\t\t\t\t\t\t sb_of));\n+\t\t\tdseg->lkey = lkey;\n+\t\t\t/*\n+\t\t\t * This data segment starts at the beginning of a new\n+\t\t\t * TXBB, so we need to postpone its byte_count writing\n+\t\t\t * for later.\n+\t\t\t */\n+\t\t\tpv[*pv_counter].dseg = dseg;\n+\t\t\t/*\n+\t\t\t * Zero length segment is treated as inline segment\n+\t\t\t * with zero data.\n+\t\t\t */\n+\t\t\tdata_len = sbuf->data_len - sb_of;\n+\t\t\tpv[(*pv_counter)++].val =\n+\t\t\t\trte_cpu_to_be_32(data_len ?\n+\t\t\t\t\t\t data_len :\n+\t\t\t\t\t\t 0x80000000);\n+\t\t\tsb_of = 0;\n+\t\t\tsbuf = sbuf->next;\n+\t\t\tdseg++;\n+\t\t\tif (--nb_segs == 0)\n+\t\t\t\tbreak;\n+\t\t\t/* fallthrough */\n+\t\tcase 3:\n+\t\t\tlkey = mlx4_tx_mb2mr(txq, sbuf);\n+\t\t\tif (unlikely(lkey == (uint32_t)-1))\n+\t\t\t\tgoto lkey_err;\n+\t\t\tdata_len = sbuf->data_len - sb_of;\n+\t\t\tmlx4_fill_tx_data_seg(dseg,\n+\t\t\t\t\tlkey,\n+\t\t\t\t\trte_pktmbuf_mtod_offset(sbuf,\n+\t\t\t\t\t\t\t\tuintptr_t,\n+\t\t\t\t\t\t\t\tsb_of),\n+\t\t\t\t\trte_cpu_to_be_32(data_len ?\n+\t\t\t\t\t\t\t data_len :\n+\t\t\t\t\t\t\t 0x80000000));\n+\t\t\tsb_of = 0;\n+\t\t\tsbuf = sbuf->next;\n+\t\t\tdseg++;\n+\t\t\tif (--nb_segs == 0)\n+\t\t\t\tbreak;\n+\t\t\t/* fallthrough */\n+\t\tcase 2:\n+\t\t\tlkey = mlx4_tx_mb2mr(txq, sbuf);\n+\t\t\tif (unlikely(lkey == (uint32_t)-1))\n+\t\t\t\tgoto lkey_err;\n+\t\t\tdata_len = sbuf->data_len - sb_of;\n+\t\t\tmlx4_fill_tx_data_seg(dseg,\n+\t\t\t\t\tlkey,\n+\t\t\t\t\trte_pktmbuf_mtod_offset(sbuf,\n+\t\t\t\t\t\t\t\tuintptr_t,\n+\t\t\t\t\t\t\t\tsb_of),\n+\t\t\t\t\trte_cpu_to_be_32(data_len ?\n+\t\t\t\t\t\t\t data_len :\n+\t\t\t\t\t\t\t 0x80000000));\n+\t\t\tsb_of = 0;\n+\t\t\tsbuf = sbuf->next;\n+\t\t\tdseg++;\n+\t\t\tif (--nb_segs == 0)\n+\t\t\t\tbreak;\n+\t\t\t/* fallthrough */\n+\t\tcase 1:\n+\t\t\tlkey = mlx4_tx_mb2mr(txq, sbuf);\n+\t\t\tif (unlikely(lkey == (uint32_t)-1))\n+\t\t\t\tgoto lkey_err;\n+\t\t\tdata_len = sbuf->data_len - sb_of;\n+\t\t\tmlx4_fill_tx_data_seg(dseg,\n+\t\t\t\t\tlkey,\n+\t\t\t\t\trte_pktmbuf_mtod_offset(sbuf,\n+\t\t\t\t\t\t\t\tuintptr_t,\n+\t\t\t\t\t\t\t\tsb_of),\n+\t\t\t\t\trte_cpu_to_be_32(data_len ?\n+\t\t\t\t\t\t\t data_len :\n+\t\t\t\t\t\t\t 0x80000000));\n+\t\t\tsb_of = 0;\n+\t\t\tsbuf = sbuf->next;\n+\t\t\tdseg++;\n+\t\t\t--nb_segs;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Should never happen */\n+\t\t\tERROR(\"%p: invalid number of txbb data segments %d\",\n+\t\t\t (void *)txq, nb_segs_txbb);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\treturn 0;\n+lkey_err:\n+\tDEBUG(\"%p: unable to get MP <-> MR association\",\n+\t (void *)txq);\n+\treturn -EFAULT;\n+}\n+\n+/**\n+ * Fill the packet's l2, l3 and l4 headers to the WQE.\n+ * This will be used as the header for each TSO segment that is transmitted.\n+ *\n+ * @param buf\n+ * Pointer to the first packet mbuf.\n+ * @param txq\n+ * Pointer to Tx queue structure.\n+ * @param tinfo\n+ * Pointer to TSO info to use.\n+ * @param tseg\n+ * Pointer to the TSO header field in the TSO WQE.\n+ * @param pv\n+ * Pointer to a stash area for saving the first 32bit word of each TXBB\n+ * used for the TSO WQE.\n+ * @param pv_counter\n+ * Current location in the stash.\n+ *\n+ * @return\n+ * 0 on success, negative value upon error.\n+ */\n+static inline int\n+mlx4_tx_burst_fill_tso_hdr(struct rte_mbuf *buf,\n+\t\t\t struct txq *txq,\n+\t\t\t const struct tso_info *tinfo,\n+\t\t\t volatile struct mlx4_wqe_lso_seg_ *tseg,\n+\t\t\t struct pv *pv, int *pv_counter)\n+{\n+\tstruct mlx4_sq *sq = &txq->msq;\n+\tint remain_sz = tinfo->tso_header_sz;\n+\tchar *from = rte_pktmbuf_mtod(buf, char *);\n+\tuint16_t txbb_avail_space;\n+\tint copy_sz;\n+\t/* Union to overcome volatile constraints when copying TSO header. */\n+\tunion {\n+\t\tvolatile uint8_t *vto;\n+\t\tuint8_t *to;\n+\t} thdr = { .vto = (volatile uint8_t *)tseg->header, };\n+\n+\t/*\n+\t * TSO data always starts at offset 20 from the beginning of the TXBB\n+\t * (16 byte ctrl + 4byte TSO desc). Since each TXBB is 64Byte aligned\n+\t * we can write the first 44 TSO header bytes without worry for TxQ\n+\t * wrapping or overwriting the first TXBB 32bit word.\n+\t */\n+\ttxbb_avail_space = MLX4_TXBB_SIZE -\n+\t\t\t (sizeof(struct mlx4_wqe_ctrl_seg) +\n+\t\t\t sizeof(struct mlx4_wqe_lso_seg_));\n+\tcopy_sz = RTE_MIN(txbb_avail_space, remain_sz);\n+\trte_memcpy(thdr.to, from, copy_sz);\n+\tremain_sz -= copy_sz;\n+\twhile (remain_sz > 0) {\n+\t\tfrom += copy_sz;\n+\t\tthdr.to += copy_sz;\n+\t\t/* Start of TXBB need to check for TxQ wrap. */\n+\t\tif (thdr.to >= sq->eob)\n+\t\t\tthdr.vto = sq->buf;\n+\t\t/* New TXBB, stash the first 32bits for later use. */\n+\t\tpv[*pv_counter].dst = (volatile uint32_t *)thdr.vto;\n+\t\tpv[(*pv_counter)++].val = *((uint32_t *)from);\n+\t\tfrom += sizeof(uint32_t);\n+\t\tthdr.to += sizeof(uint32_t);\n+\t\tremain_sz -= sizeof(uint32_t);\n+\t\tif (remain_sz <= 0)\n+\t\t\tbreak;\n+\t\t/* Now copy the rest */\n+\t\ttxbb_avail_space = MLX4_TXBB_SIZE - sizeof(uint32_t);\n+\t\tcopy_sz = RTE_MIN(txbb_avail_space, remain_sz);\n+\t\trte_memcpy(thdr.to, from, copy_sz);\n+\t\tremain_sz -= copy_sz;\n+\t}\n+\t/* TODO: handle PID and IPID ? */\n+\ttseg->mss_hdr_size = rte_cpu_to_be_32((buf->tso_segsz << 16) |\n+\t\t\t\t\t tinfo->tso_header_sz);\n+\treturn 0;\n+}\n+\n+/**\n+ * Write data segments and header for TSO uni/multi segment packet.\n+ *\n+ * @param buf\n+ * Pointer to the first packet mbuf.\n+ * @param txq\n+ * Pointer to Tx queue structure.\n+ * @param ctrl\n+ * Pointer to the WQE control segment.\n+ *\n+ * @return\n+ * Pointer to the next WQE control segment on success, NULL otherwise.\n+ */\n+static volatile struct mlx4_wqe_ctrl_seg *\n+mlx4_tx_burst_tso(struct rte_mbuf *buf, struct txq *txq,\n+\t\t volatile struct mlx4_wqe_ctrl_seg *ctrl)\n+{\n+\tvolatile struct mlx4_wqe_data_seg *dseg;\n+\tvolatile struct mlx4_wqe_lso_seg_ *tseg =\n+\t\t(volatile struct mlx4_wqe_lso_seg_ *)(ctrl + 1);\n+\tstruct mlx4_sq *sq = &txq->msq;\n+\tstruct tso_info tinfo;\n+\tstruct pv *pv = (struct pv *)txq->bounce_buf;\n+\tint pv_counter = 0;\n+\tint ret;\n+\n+\tret = mlx4_tx_burst_tso_get_params(buf, txq, &tinfo);\n+\tif (ret)\n+\t\tgoto error;\n+\tret = mlx4_tx_burst_fill_tso_hdr(buf, txq, &tinfo,\n+\t\t\t\t\t tseg, pv, &pv_counter);\n+\tif (ret)\n+\t\tgoto error;\n+\t/* Calculate data segment location */\n+\tdseg = (volatile struct mlx4_wqe_data_seg *)\n+\t\t\t\t((uintptr_t)tseg + tinfo.wqe_tso_seg_size);\n+\tif ((uintptr_t)dseg >= (uintptr_t)sq->eob)\n+\t\tdseg = (volatile struct mlx4_wqe_data_seg *)\n+\t\t\t\t\t((uintptr_t)dseg - sq->size);\n+\tret = mlx4_tx_burst_fill_tso_segs(buf, txq, &tinfo,\n+\t\t\t\t\t dseg, pv, &pv_counter);\n+\tif (ret)\n+\t\tgoto error;\n+\t/* Write the first DWORD of each TXBB save earlier. */\n+\tif (pv_counter) {\n+\t\t/* Need a barrier here before writing the first TXBB word. */\n+\t\trte_io_wmb();\n+\t\tfor (--pv_counter; pv_counter >= 0; pv_counter--)\n+\t\t\t*pv[pv_counter].dst = pv[pv_counter].val;\n+\t}\n+\tctrl->fence_size = tinfo.fence_size;\n+\tsq->remain_size -= tinfo.wqe_size;\n+\t/* Align next WQE address to the next TXBB. */\n+\treturn (volatile struct mlx4_wqe_ctrl_seg *)\n+\t\t((volatile uint8_t *)ctrl + tinfo.wqe_size);\n+error:\n+\ttxq->stats.odropped++;\n+\trte_errno = ret;\n+\treturn NULL;\n+}\n+\n+/**\n * Write data segments of multi-segment packet.\n *\n * @param buf\n@@ -569,6 +927,7 @@ struct pv {\n \t\t\tuint16_t flags16[2];\n \t\t} srcrb;\n \t\tuint32_t lkey;\n+\t\tbool tso = txq->priv->tso && (buf->ol_flags & PKT_TX_TCP_SEG);\n \n \t\t/* Clean up old buffer. */\n \t\tif (likely(elt->buf != NULL)) {\n@@ -587,7 +946,16 @@ struct pv {\n \t\t\t} while (tmp != NULL);\n \t\t}\n \t\tRTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);\n-\t\tif (buf->nb_segs == 1) {\n+\t\tif (tso) {\n+\t\t\t/* Change opcode to TSO */\n+\t\t\towner_opcode &= ~MLX4_OPCODE_CONFIG_CMD;\n+\t\t\towner_opcode |= MLX4_OPCODE_LSO | MLX4_WQE_CTRL_RR;\n+\t\t\tctrl_next = mlx4_tx_burst_tso(buf, txq, ctrl);\n+\t\t\tif (!ctrl_next) {\n+\t\t\t\telt->buf = NULL;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t} else if (buf->nb_segs == 1) {\n \t\t\t/* Validate WQE space in the send queue. */\n \t\t\tif (sq->remain_size < MLX4_TXBB_SIZE) {\n \t\t\t\telt->buf = NULL;\ndiff --git a/drivers/net/mlx4/mlx4_rxtx.h b/drivers/net/mlx4/mlx4_rxtx.h\nindex 4c025e3..ffa8abf 100644\n--- a/drivers/net/mlx4/mlx4_rxtx.h\n+++ b/drivers/net/mlx4/mlx4_rxtx.h\n@@ -90,7 +90,7 @@ struct mlx4_txq_stats {\n \tunsigned int idx; /**< Mapping index. */\n \tuint64_t opackets; /**< Total of successfully sent packets. */\n \tuint64_t obytes; /**< Total of successfully sent bytes. */\n-\tuint64_t odropped; /**< Total of packets not sent when Tx ring full. */\n+\tuint64_t odropped; /**< Total number of packets failed to transmit. */\n };\n \n /** Tx queue descriptor. */\ndiff --git a/drivers/net/mlx4/mlx4_txq.c b/drivers/net/mlx4/mlx4_txq.c\nindex 6edaadb..9aa7440 100644\n--- a/drivers/net/mlx4/mlx4_txq.c\n+++ b/drivers/net/mlx4/mlx4_txq.c\n@@ -116,8 +116,14 @@\n \t\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n \t\t\t DEV_TX_OFFLOAD_TCP_CKSUM);\n \t}\n-\tif (priv->hw_csum_l2tun)\n+\tif (priv->tso)\n+\t\toffloads |= DEV_TX_OFFLOAD_TCP_TSO;\n+\tif (priv->hw_csum_l2tun) {\n \t\toffloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;\n+\t\tif (priv->tso)\n+\t\t\toffloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |\n+\t\t\t\t DEV_TX_OFFLOAD_GRE_TNL_TSO);\n+\t}\n \treturn offloads;\n }\n \n", "prefixes": [ "v3" ] }