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GET /api/patches/41147/?format=api
{ "id": 41147, "url": "http://patches.dpdk.org/api/patches/41147/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1529032259-9718-1-git-send-email-wei.zhao1@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1529032259-9718-1-git-send-email-wei.zhao1@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1529032259-9718-1-git-send-email-wei.zhao1@intel.com", "date": "2018-06-15T03:10:59", "name": "[v4] net/ixgbe: fix mask bits register set error for FDIR", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "010b07f59fa712ffd20cd04413785654ec68710c", "submitter": { "id": 495, "url": "http://patches.dpdk.org/api/people/495/?format=api", "name": "Zhao1, Wei", "email": "wei.zhao1@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1529032259-9718-1-git-send-email-wei.zhao1@intel.com/mbox/", "series": [ { "id": 132, "url": "http://patches.dpdk.org/api/series/132/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=132", "date": "2018-06-15T03:10:59", "name": "[v4] net/ixgbe: fix mask bits register set error for FDIR", "version": 4, "mbox": "http://patches.dpdk.org/series/132/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/41147/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/41147/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 765591D689;\n\tFri, 15 Jun 2018 05:31:50 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id 91B051D682;\n\tFri, 15 Jun 2018 05:31:45 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t14 Jun 2018 20:31:43 -0700", "from dpdk6.bj.intel.com ([172.16.182.94])\n\tby fmsmga001.fm.intel.com with ESMTP; 14 Jun 2018 20:31:42 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,225,1526367600\"; d=\"scan'208\";a=\"64276529\"", "From": "Wei Zhao <wei.zhao1@intel.com>", "To": "dev@dpdk.org", "Cc": "wenzhuo.lu@intel.com,\n\tstable@dpdk.org,\n\tWei Zhao <wei.zhao1@intel.com>", "Date": "Fri, 15 Jun 2018 11:10:59 +0800", "Message-Id": "<1529032259-9718-1-git-send-email-wei.zhao1@intel.com>", "X-Mailer": "git-send-email 2.7.5", "In-Reply-To": "<1529029850-56080-1-git-send-email-wei.zhao1@intel.com>", "References": "<1529029850-56080-1-git-send-email-wei.zhao1@intel.com>", "Subject": "[dpdk-dev] [PATCH v4] net/ixgbe: fix mask bits register set error\n\tfor FDIR", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "MAC address bits in mask registers should be set to zero\nwhen the is mac mask is 0xFF, otherwise if it is 0x0\nthese bits should be to 0x3F.\n\nFixes: 82fb702077f6 (\"ixgbe: support new flow director modes for X550\")\n\nSigned-off-by: Wei Zhao <wei.zhao1@intel.com>\n\n---\n\nv2:\n-change mask bits set method to support more mac mask.\n\nv3:\n-change mask and with 0x3F to macro definition.\n\nv4:\n-fix mask bits bug in v3.\n---\n drivers/net/ixgbe/ixgbe_fdir.c | 10 ++++++----\n 1 file changed, 6 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdir.c\nindex 6baf825..6ac806c 100644\n--- a/drivers/net/ixgbe/ixgbe_fdir.c\n+++ b/drivers/net/ixgbe/ixgbe_fdir.c\n@@ -388,15 +388,17 @@ fdir_set_input_mask_x550(struct rte_eth_dev *dev)\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);\n \n \tfdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);\n-\tfdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;\n+\tfdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK | IXGBE_FDIRIP6M_INNER_MAC;\n \tif (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)\n \t\tfdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |\n \t\t\t\tIXGBE_FDIRIP6M_TNI_VNI;\n \n \tif (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {\n-\t\tmac_mask = info->mask.mac_addr_byte_mask;\n-\t\tfdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)\n-\t\t\t\t& IXGBE_FDIRIP6M_INNER_MAC;\n+\t\tmac_mask = info->mask.mac_addr_byte_mask &\n+\t\t\t(IXGBE_FDIRIP6M_INNER_MAC >>\n+\t\t\tIXGBE_FDIRIP6M_INNER_MAC_SHIFT);\n+\t\tfdiripv6m &= ~((mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT) &\n+\t\t\t\tIXGBE_FDIRIP6M_INNER_MAC);\n \n \t\tswitch (info->mask.tunnel_type_mask) {\n \t\tcase 0:\n", "prefixes": [ "v4" ] }