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{
    "id": 41068,
    "url": "http://patches.dpdk.org/api/patches/41068/",
    "web_url": "http://patches.dpdk.org/patch/41068/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1528892062-4997-36-git-send-email-tomaszx.jozwiak@intel.com>",
    "date": "2018-06-13T12:14:19",
    "name": "[v3,35/38] crypto/qat: make response process function inline",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "44b427c6e95d52174e91bfd87af6318f7fc1ddd5",
    "submitter": {
        "id": 949,
        "url": "http://patches.dpdk.org/api/people/949/",
        "name": "Tomasz Jozwiak",
        "email": "tomaszx.jozwiak@intel.com"
    },
    "delegate": {
        "id": 22,
        "url": "http://patches.dpdk.org/api/users/22/",
        "username": "pdelarag",
        "first_name": "Pablo",
        "last_name": "de Lara Guarch",
        "email": "pablo.de.lara.guarch@intel.com"
    },
    "mbox": "http://patches.dpdk.org/patch/41068/mbox/",
    "series": [
        {
            "id": 111,
            "url": "http://patches.dpdk.org/api/series/111/",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=111",
            "date": "2018-06-13T12:13:44",
            "name": "crypto/qat: refactor to support multiple services",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/111/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/41068/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/41068/checks/",
    "tags": {},
    "headers": {
        "X-Mailman-Version": "2.1.15",
        "X-ExtLoop1": "1",
        "Errors-To": "dev-bounces@dpdk.org",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Mailer": "git-send-email 2.7.4",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 711451F02B;\n\tWed, 13 Jun 2018 14:16:00 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id E37D91EF9B\n\tfor <dev@dpdk.org>; Wed, 13 Jun 2018 14:15:12 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Jun 2018 05:15:12 -0700",
            "from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 13 Jun 2018 05:15:11 -0700"
        ],
        "References": "<1523040732-3290-1-git-send-email-fiona.trahe@intel.com>\n\t<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "X-BeenThere": "dev@dpdk.org",
        "Message-Id": "<1528892062-4997-36-git-send-email-tomaszx.jozwiak@intel.com>",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,218,1526367600\"; d=\"scan'208\";a=\"63727866\"",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Precedence": "list",
        "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>",
        "X-Original-To": "patchwork@dpdk.org",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "In-Reply-To": "<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "To": "fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com,\n\tdev@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Date": "Wed, 13 Jun 2018 14:14:19 +0200",
        "X-Amp-File-Uploaded": "False",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "Subject": "[dpdk-dev] [PATCH v3 35/38] crypto/qat: make response process\n\tfunction inline"
    },
    "content": "From: Fiona Trahe <fiona.trahe@intel.com>\n\nOptimize the dequeue function by inlining the response\nprocessing function, assuming only symmetric\noperations are supported.\n\nSigned-off-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n drivers/crypto/qat/qat_qp.c      |   4 +-\n drivers/crypto/qat/qat_qp.h      |   5 --\n drivers/crypto/qat/qat_sym.c     | 127 ------------------------------\n drivers/crypto/qat/qat_sym.h     | 131 ++++++++++++++++++++++++++++++-\n drivers/crypto/qat/qat_sym_pmd.c |   1 -\n 5 files changed, 131 insertions(+), 137 deletions(-)",
    "diff": "diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c\nindex 0fdec0da0..b190f2cee 100644\n--- a/drivers/crypto/qat/qat_qp.c\n+++ b/drivers/crypto/qat/qat_qp.c\n@@ -14,6 +14,7 @@\n #include \"qat_logs.h\"\n #include \"qat_device.h\"\n #include \"qat_qp.h\"\n+#include \"qat_sym.h\"\n #include \"adf_transport_access_macros.h\"\n \n \n@@ -238,7 +239,6 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \n \tqp->qat_dev_gen = qat_dev->qat_dev_gen;\n \tqp->build_request = qat_qp_conf->build_request;\n-\tqp->process_response = qat_qp_conf->process_response;\n \tqp->qat_dev = qat_dev;\n \n \tPMD_DRV_LOG(DEBUG, \"QP setup complete: id: %d, cookiepool: %s\",\n@@ -612,7 +612,7 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n \twhile (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&\n \t\t\tresp_counter != nb_ops) {\n \n-\t\ttmp_qp->process_response(ops, resp_msg);\n+\t\tqat_sym_process_response(ops, resp_msg);\n \n \t\thead = adf_modulo(head + rx_queue->msg_size,\n \t\t\t\t  rx_queue->modulo_mask);\ndiff --git a/drivers/crypto/qat/qat_qp.h b/drivers/crypto/qat/qat_qp.h\nindex eb9188410..0b3d6d3aa 100644\n--- a/drivers/crypto/qat/qat_qp.h\n+++ b/drivers/crypto/qat/qat_qp.h\n@@ -21,9 +21,6 @@ typedef int (*build_request_t)(void *op,\n \t\tenum qat_device_gen qat_dev_gen);\n /**< Build a request from an op. */\n \n-typedef int (*process_response_t)(void **ops, uint8_t *resp);\n-/**< Process a response descriptor and return the associated op. */\n-\n /**\n  * Structure with data needed for creation of queue pair.\n  */\n@@ -44,7 +41,6 @@ struct qat_qp_config {\n \tuint32_t cookie_size;\n \tint socket_id;\n \tbuild_request_t build_request;\n-\tprocess_response_t process_response;\n \tconst char *service_str;\n };\n \n@@ -83,7 +79,6 @@ struct qat_qp {\n \tuint32_t nb_descriptors;\n \tenum qat_device_gen qat_dev_gen;\n \tbuild_request_t build_request;\n-\tprocess_response_t process_response;\n \tstruct qat_pci_device *qat_dev;\n \t/**< qat device this qp is on */\n } __rte_cache_aligned;\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex f613adce6..887d4ebcd 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -12,44 +12,7 @@\n #include <rte_byteorder.h>\n \n #include \"qat_logs.h\"\n-#include \"qat_sym_session.h\"\n #include \"qat_sym.h\"\n-#include \"qat_sym_pmd.h\"\n-\n-#define BYTE_LENGTH    8\n-/* bpi is only used for partial blocks of DES and AES\n- * so AES block len can be assumed as max len for iv, src and dst\n- */\n-#define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ\n-\n-/** Encrypt a single partial block\n- *  Depends on openssl libcrypto\n- *  Uses ECB+XOR to do CFB encryption, same result, more performant\n- */\n-static inline int\n-bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,\n-\t\tuint8_t *iv, int ivlen, int srclen,\n-\t\tvoid *bpi_ctx)\n-{\n-\tEVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;\n-\tint encrypted_ivlen;\n-\tuint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];\n-\tuint8_t *encr = encrypted_iv;\n-\n-\t/* ECB method: encrypt the IV, then XOR this with plaintext */\n-\tif (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)\n-\t\t\t\t\t\t\t\t<= 0)\n-\t\tgoto cipher_encrypt_err;\n-\n-\tfor (; srclen != 0; --srclen, ++dst, ++src, ++encr)\n-\t\t*dst = *src ^ *encr;\n-\n-\treturn 0;\n-\n-cipher_encrypt_err:\n-\tPMD_DRV_LOG(ERR, \"libcrypto ECB cipher encrypt failed\");\n-\treturn -EINVAL;\n-}\n \n /** Decrypt a single partial block\n  *  Depends on openssl libcrypto\n@@ -136,62 +99,6 @@ qat_bpicipher_preprocess(struct qat_sym_session *ctx,\n \treturn sym_op->cipher.data.length - last_block_len;\n }\n \n-static inline uint32_t\n-qat_bpicipher_postprocess(struct qat_sym_session *ctx,\n-\t\t\t\tstruct rte_crypto_op *op)\n-{\n-\tint block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);\n-\tstruct rte_crypto_sym_op *sym_op = op->sym;\n-\tuint8_t last_block_len = block_len > 0 ?\n-\t\t\tsym_op->cipher.data.length % block_len : 0;\n-\n-\tif (last_block_len > 0 &&\n-\t\t\tctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {\n-\n-\t\t/* Encrypt last block */\n-\t\tuint8_t *last_block, *dst, *iv;\n-\t\tuint32_t last_block_offset;\n-\n-\t\tlast_block_offset = sym_op->cipher.data.offset +\n-\t\t\t\tsym_op->cipher.data.length - last_block_len;\n-\t\tlast_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,\n-\t\t\t\tuint8_t *, last_block_offset);\n-\n-\t\tif (unlikely(sym_op->m_dst != NULL))\n-\t\t\t/* out-of-place operation (OOP) */\n-\t\t\tdst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,\n-\t\t\t\t\t\tuint8_t *, last_block_offset);\n-\t\telse\n-\t\t\tdst = last_block;\n-\n-\t\tif (last_block_len < sym_op->cipher.data.length)\n-\t\t\t/* use previous block ciphertext as IV */\n-\t\t\tiv = dst - block_len;\n-\t\telse\n-\t\t\t/* runt block, i.e. less than one full block */\n-\t\t\tiv = rte_crypto_op_ctod_offset(op, uint8_t *,\n-\t\t\t\t\tctx->cipher_iv.offset);\n-\n-#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX\n-\t\trte_hexdump(stdout, \"BPI: src before post-process:\", last_block,\n-\t\t\tlast_block_len);\n-\t\tif (sym_op->m_dst != NULL)\n-\t\t\trte_hexdump(stdout, \"BPI: dst before post-process:\",\n-\t\t\t\t\tdst, last_block_len);\n-#endif\n-\t\tbpi_cipher_encrypt(last_block, dst, iv, block_len,\n-\t\t\t\tlast_block_len, ctx->bpi_ctx);\n-#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX\n-\t\trte_hexdump(stdout, \"BPI: src after post-process:\", last_block,\n-\t\t\tlast_block_len);\n-\t\tif (sym_op->m_dst != NULL)\n-\t\t\trte_hexdump(stdout, \"BPI: dst after post-process:\", dst,\n-\t\t\t\tlast_block_len);\n-#endif\n-\t}\n-\treturn sym_op->cipher.data.length - last_block_len;\n-}\n-\n static inline void\n set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,\n \t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param,\n@@ -659,37 +566,3 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n #endif\n \treturn 0;\n }\n-\n-int\n-qat_sym_process_response(void **op, uint8_t *resp)\n-{\n-\n-\tstruct icp_qat_fw_comn_resp *resp_msg =\n-\t\t\t(struct icp_qat_fw_comn_resp *)resp;\n-\tstruct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)\n-\t\t\t(resp_msg->opaque_data);\n-\n-#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX\n-\trte_hexdump(stdout, \"qat_response:\", (uint8_t *)resp_msg,\n-\t\t\tsizeof(struct icp_qat_fw_comn_resp));\n-#endif\n-\n-\tif (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=\n-\t\t\tICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(\n-\t\t\tresp_msg->comn_hdr.comn_status)) {\n-\n-\t\trx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n-\t} else {\n-\t\tstruct qat_sym_session *sess = (struct qat_sym_session *)\n-\t\t\t\t\t\tget_session_private_data(\n-\t\t\t\t\t\trx_op->sym->session,\n-\t\t\t\t\t\tcryptodev_qat_driver_id);\n-\n-\t\tif (sess->bpi_ctx)\n-\t\t\tqat_bpicipher_postprocess(sess, rx_op);\n-\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-\t}\n-\t*op = (void *)rx_op;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex dffd5f369..ddd0f473f 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -6,8 +6,19 @@\n #define _QAT_SYM_H_\n \n #include <rte_cryptodev_pmd.h>\n+#include <rte_hexdump.h>\n+\n+#include <openssl/evp.h>\n \n #include \"qat_common.h\"\n+#include \"qat_sym_session.h\"\n+#include \"qat_sym_pmd.h\"\n+\n+#define BYTE_LENGTH    8\n+/* bpi is only used for partial blocks of DES and AES\n+ * so AES block len can be assumed as max len for iv, src and dst\n+ */\n+#define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ\n \n struct qat_sym_session;\n \n@@ -21,7 +32,123 @@ struct qat_sym_op_cookie {\n int\n qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen);\n-int\n-qat_sym_process_response(void **op, uint8_t *resp);\n \n+\n+/** Encrypt a single partial block\n+ *  Depends on openssl libcrypto\n+ *  Uses ECB+XOR to do CFB encryption, same result, more performant\n+ */\n+static inline int\n+bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,\n+\t\tuint8_t *iv, int ivlen, int srclen,\n+\t\tvoid *bpi_ctx)\n+{\n+\tEVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;\n+\tint encrypted_ivlen;\n+\tuint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];\n+\tuint8_t *encr = encrypted_iv;\n+\n+\t/* ECB method: encrypt the IV, then XOR this with plaintext */\n+\tif (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)\n+\t\t\t\t\t\t\t\t<= 0)\n+\t\tgoto cipher_encrypt_err;\n+\n+\tfor (; srclen != 0; --srclen, ++dst, ++src, ++encr)\n+\t\t*dst = *src ^ *encr;\n+\n+\treturn 0;\n+\n+cipher_encrypt_err:\n+\tPMD_DRV_LOG(ERR, \"libcrypto ECB cipher encrypt failed\");\n+\treturn -EINVAL;\n+}\n+\n+static inline uint32_t\n+qat_bpicipher_postprocess(struct qat_sym_session *ctx,\n+\t\t\t\tstruct rte_crypto_op *op)\n+{\n+\tint block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tuint8_t last_block_len = block_len > 0 ?\n+\t\t\tsym_op->cipher.data.length % block_len : 0;\n+\n+\tif (last_block_len > 0 &&\n+\t\t\tctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {\n+\n+\t\t/* Encrypt last block */\n+\t\tuint8_t *last_block, *dst, *iv;\n+\t\tuint32_t last_block_offset;\n+\n+\t\tlast_block_offset = sym_op->cipher.data.offset +\n+\t\t\t\tsym_op->cipher.data.length - last_block_len;\n+\t\tlast_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,\n+\t\t\t\tuint8_t *, last_block_offset);\n+\n+\t\tif (unlikely(sym_op->m_dst != NULL))\n+\t\t\t/* out-of-place operation (OOP) */\n+\t\t\tdst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,\n+\t\t\t\t\t\tuint8_t *, last_block_offset);\n+\t\telse\n+\t\t\tdst = last_block;\n+\n+\t\tif (last_block_len < sym_op->cipher.data.length)\n+\t\t\t/* use previous block ciphertext as IV */\n+\t\t\tiv = dst - block_len;\n+\t\telse\n+\t\t\t/* runt block, i.e. less than one full block */\n+\t\t\tiv = rte_crypto_op_ctod_offset(op, uint8_t *,\n+\t\t\t\t\tctx->cipher_iv.offset);\n+\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX\n+\t\trte_hexdump(stdout, \"BPI: src before post-process:\", last_block,\n+\t\t\tlast_block_len);\n+\t\tif (sym_op->m_dst != NULL)\n+\t\t\trte_hexdump(stdout, \"BPI: dst before post-process:\",\n+\t\t\t\t\tdst, last_block_len);\n+#endif\n+\t\tbpi_cipher_encrypt(last_block, dst, iv, block_len,\n+\t\t\t\tlast_block_len, ctx->bpi_ctx);\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX\n+\t\trte_hexdump(stdout, \"BPI: src after post-process:\", last_block,\n+\t\t\tlast_block_len);\n+\t\tif (sym_op->m_dst != NULL)\n+\t\t\trte_hexdump(stdout, \"BPI: dst after post-process:\", dst,\n+\t\t\t\tlast_block_len);\n+#endif\n+\t}\n+\treturn sym_op->cipher.data.length - last_block_len;\n+}\n+\n+static inline void\n+qat_sym_process_response(void **op, uint8_t *resp)\n+{\n+\n+\tstruct icp_qat_fw_comn_resp *resp_msg =\n+\t\t\t(struct icp_qat_fw_comn_resp *)resp;\n+\tstruct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)\n+\t\t\t(resp_msg->opaque_data);\n+\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX\n+\trte_hexdump(stdout, \"qat_response:\", (uint8_t *)resp_msg,\n+\t\t\tsizeof(struct icp_qat_fw_comn_resp));\n+#endif\n+\n+\tif (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=\n+\t\t\tICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(\n+\t\t\tresp_msg->comn_hdr.comn_status)) {\n+\n+\t\trx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t} else {\n+\t\tstruct qat_sym_session *sess = (struct qat_sym_session *)\n+\t\t\t\t\t\tget_session_private_data(\n+\t\t\t\t\t\trx_op->sym->session,\n+\t\t\t\t\t\tcryptodev_qat_driver_id);\n+\n+\n+\t\tif (sess->bpi_ctx)\n+\t\t\tqat_bpicipher_postprocess(sess, rx_op);\n+\t\trx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t}\n+\t*op = (void *)rx_op;\n+}\n #endif /* _QAT_SYM_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex 28e579b77..6b39b32f8 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -160,7 +160,6 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \n \tqat_qp_conf.hw = qp_hw_data;\n \tqat_qp_conf.build_request = qat_sym_build_request;\n-\tqat_qp_conf.process_response = qat_sym_process_response;\n \tqat_qp_conf.cookie_size = sizeof(struct qat_sym_op_cookie);\n \tqat_qp_conf.nb_descriptors = qp_conf->nb_descriptors;\n \tqat_qp_conf.socket_id = socket_id;\n",
    "prefixes": [
        "v3",
        "35/38"
    ]
}