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{
    "id": 41056,
    "url": "http://patches.dpdk.org/api/patches/41056/",
    "web_url": "http://patches.dpdk.org/patch/41056/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1528892062-4997-25-git-send-email-tomaszx.jozwiak@intel.com>",
    "date": "2018-06-13T12:14:08",
    "name": "[v3,24/38] crypto/qat: add lock around csr access and change logic",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "d58c489cc4f41eb1220f23603423a2a6b906bfa2",
    "submitter": {
        "id": 949,
        "url": "http://patches.dpdk.org/api/people/949/",
        "name": "Tomasz Jozwiak",
        "email": "tomaszx.jozwiak@intel.com"
    },
    "delegate": {
        "id": 22,
        "url": "http://patches.dpdk.org/api/users/22/",
        "username": "pdelarag",
        "first_name": "Pablo",
        "last_name": "de Lara Guarch",
        "email": "pablo.de.lara.guarch@intel.com"
    },
    "mbox": "http://patches.dpdk.org/patch/41056/mbox/",
    "series": [
        {
            "id": 111,
            "url": "http://patches.dpdk.org/api/series/111/",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=111",
            "date": "2018-06-13T12:13:44",
            "name": "crypto/qat: refactor to support multiple services",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/111/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/41056/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/41056/checks/",
    "tags": {},
    "headers": {
        "X-Mailer": "git-send-email 2.7.4",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Precedence": "list",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Date": "Wed, 13 Jun 2018 14:14:08 +0200",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "To": "fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com,\n\tdev@dpdk.org",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<1523040732-3290-1-git-send-email-fiona.trahe@intel.com>\n\t<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,218,1526367600\"; d=\"scan'208\";a=\"63727765\"",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5C7B41EF7A;\n\tWed, 13 Jun 2018 14:15:28 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id C28111EF8C\n\tfor <dev@dpdk.org>; Wed, 13 Jun 2018 14:15:02 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Jun 2018 05:14:59 -0700",
            "from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 13 Jun 2018 05:14:57 -0700"
        ],
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "X-Amp-File-Uploaded": "False",
        "Subject": "[dpdk-dev] [PATCH v3 24/38] crypto/qat: add lock around csr access\n\tand change logic",
        "In-Reply-To": "<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "Message-Id": "<1528892062-4997-25-git-send-email-tomaszx.jozwiak@intel.com>",
        "X-ExtLoop1": "1",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-Original-To": "patchwork@dpdk.org"
    },
    "content": "From: Fiona Trahe <fiona.trahe@intel.com>\n\nAdd lock around accesses to the arbiter CSR\nand use & instead of ^ as ^ not safe if\narb_disable called when already disabled.\n\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n drivers/crypto/qat/qat_qp.c | 26 +++++++++++++++++++-------\n 1 file changed, 19 insertions(+), 7 deletions(-)",
    "diff": "diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c\nindex 7b2dc3f90..f26fd0900 100644\n--- a/drivers/crypto/qat/qat_qp.c\n+++ b/drivers/crypto/qat/qat_qp.c\n@@ -107,8 +107,10 @@ static int qat_queue_create(struct qat_pci_device *qat_dev,\n static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,\n \tuint32_t *queue_size_for_csr);\n static void adf_configure_queues(struct qat_qp *queue);\n-static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr);\n-static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr);\n+static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,\n+\trte_spinlock_t *lock);\n+static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,\n+\trte_spinlock_t *lock);\n \n \n int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,\n@@ -216,7 +218,8 @@ int qat_qp_setup(struct qat_pci_device *qat_dev,\n \t}\n \n \tadf_configure_queues(qp);\n-\tadf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr);\n+\tadf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr,\n+\t\t\t\t\t&qat_dev->arb_csr_lock);\n \n \tsnprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,\n \t\t\t\t\t\"%s%d_cookies_%s_qp%hu\",\n@@ -282,7 +285,8 @@ int qat_qp_release(struct qat_qp **qp_addr)\n \t\treturn -EAGAIN;\n \t}\n \n-\tadf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr);\n+\tadf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr,\n+\t\t\t\t\t&qp->qat_dev->arb_csr_lock);\n \n \tfor (i = 0; i < qp->nb_descriptors; i++)\n \t\trte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);\n@@ -443,7 +447,8 @@ static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,\n \treturn -EINVAL;\n }\n \n-static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr)\n+static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,\n+\t\t\t\t\trte_spinlock_t *lock)\n {\n \tuint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +\n \t\t\t\t\t(ADF_ARB_REG_SLOT *\n@@ -451,12 +456,16 @@ static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr)\n \tuint32_t value;\n \n \tPMD_INIT_FUNC_TRACE();\n+\n+\trte_spinlock_lock(lock);\n \tvalue = ADF_CSR_RD(base_addr, arb_csr_offset);\n \tvalue |= (0x01 << txq->hw_queue_number);\n \tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n }\n \n-static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr)\n+static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,\n+\t\t\t\t\trte_spinlock_t *lock)\n {\n \tuint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +\n \t\t\t\t\t(ADF_ARB_REG_SLOT *\n@@ -464,9 +473,12 @@ static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr)\n \tuint32_t value;\n \n \tPMD_INIT_FUNC_TRACE();\n+\n+\trte_spinlock_lock(lock);\n \tvalue = ADF_CSR_RD(base_addr, arb_csr_offset);\n-\tvalue ^= (0x01 << txq->hw_queue_number);\n+\tvalue &= ~(0x01 << txq->hw_queue_number);\n \tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n }\n \n static void adf_configure_queues(struct qat_qp *qp)\n",
    "prefixes": [
        "v3",
        "24/38"
    ]
}