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{
    "id": 41051,
    "url": "http://patches.dpdk.org/api/patches/41051/",
    "web_url": "http://patches.dpdk.org/patch/41051/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1528892062-4997-18-git-send-email-tomaszx.jozwiak@intel.com>",
    "date": "2018-06-13T12:14:01",
    "name": "[v3,17/38] crypto/qat: move sgl related element to appropriate files",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "74958e17df61810d392ac58b44e4b34854e64c99",
    "submitter": {
        "id": 949,
        "url": "http://patches.dpdk.org/api/people/949/",
        "name": "Tomasz Jozwiak",
        "email": "tomaszx.jozwiak@intel.com"
    },
    "delegate": {
        "id": 22,
        "url": "http://patches.dpdk.org/api/users/22/",
        "username": "pdelarag",
        "first_name": "Pablo",
        "last_name": "de Lara Guarch",
        "email": "pablo.de.lara.guarch@intel.com"
    },
    "mbox": "http://patches.dpdk.org/patch/41051/mbox/",
    "series": [
        {
            "id": 111,
            "url": "http://patches.dpdk.org/api/series/111/",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=111",
            "date": "2018-06-13T12:13:44",
            "name": "crypto/qat: refactor to support multiple services",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/111/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/41051/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/41051/checks/",
    "tags": {},
    "headers": {
        "X-Mailer": "git-send-email 2.7.4",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Precedence": "list",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Date": "Wed, 13 Jun 2018 14:14:01 +0200",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "To": "fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com,\n\tdev@dpdk.org",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<1523040732-3290-1-git-send-email-fiona.trahe@intel.com>\n\t<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,218,1526367600\"; d=\"scan'208\";a=\"63727722\"",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2C5811EFA3;\n\tWed, 13 Jun 2018 14:15:14 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 8B43E1EF8C\n\tfor <dev@dpdk.org>; Wed, 13 Jun 2018 14:15:01 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Jun 2018 05:14:58 -0700",
            "from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 13 Jun 2018 05:14:48 -0700"
        ],
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "X-Amp-File-Uploaded": "False",
        "Subject": "[dpdk-dev] [PATCH v3 17/38] crypto/qat: move sgl related element to\n\tappropriate files",
        "In-Reply-To": "<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "Message-Id": "<1528892062-4997-18-git-send-email-tomaszx.jozwiak@intel.com>",
        "X-ExtLoop1": "1",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-Original-To": "patchwork@dpdk.org"
    },
    "content": "From: Fiona Trahe <fiona.trahe@intel.com>\n\nMove SGL (Scatter-Gather List) related functions to common file\nMove qat_sym_op_cookie struct to sym header file\n\nSigned-off-by: ArkadiuszX Kusztal <arkadiuszx.kusztal@intel.com>\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n drivers/crypto/qat/Makefile     |  1 +\n drivers/crypto/qat/meson.build  |  1 +\n drivers/crypto/qat/qat_common.c | 53 +++++++++++++++++++++++++++++++++\n drivers/crypto/qat/qat_common.h | 11 ++++---\n drivers/crypto/qat/qat_sym.c    | 47 -----------------------------\n drivers/crypto/qat/qat_sym.h    |  7 +++++\n 6 files changed, 67 insertions(+), 53 deletions(-)\n create mode 100644 drivers/crypto/qat/qat_common.c",
    "diff": "diff --git a/drivers/crypto/qat/Makefile b/drivers/crypto/qat/Makefile\nindex 8cb802b9d..902c47ff4 100644\n--- a/drivers/crypto/qat/Makefile\n+++ b/drivers/crypto/qat/Makefile\n@@ -25,6 +25,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_sym.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_device.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_qp.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_sym_session.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_common.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += rte_qat_cryptodev.c\n \n # export include files\ndiff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build\nindex e596006da..12910c377 100644\n--- a/drivers/crypto/qat/meson.build\n+++ b/drivers/crypto/qat/meson.build\n@@ -7,6 +7,7 @@ if not dep.found()\n endif\n sources = files('qat_sym.c', 'qat_qp.c',\n \t\t'qat_sym_session.c',\n+\t\t'qat_common.c',\n \t\t'rte_qat_cryptodev.c',\n \t\t'qat_device.c')\n includes += include_directories('qat_adf')\ndiff --git a/drivers/crypto/qat/qat_common.c b/drivers/crypto/qat/qat_common.c\nnew file mode 100644\nindex 000000000..a8865904f\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_common.c\n@@ -0,0 +1,53 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#include \"qat_common.h\"\n+#include \"qat_logs.h\"\n+\n+int\n+qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,\n+\t\tstruct qat_sgl *list, uint32_t data_len)\n+{\n+\tint nr = 1;\n+\n+\tuint32_t buf_len = rte_pktmbuf_iova(buf) -\n+\t\t\tbuf_start + rte_pktmbuf_data_len(buf);\n+\n+\tlist->buffers[0].addr = buf_start;\n+\tlist->buffers[0].resrvd = 0;\n+\tlist->buffers[0].len = buf_len;\n+\n+\tif (data_len <= buf_len) {\n+\t\tlist->num_bufs = nr;\n+\t\tlist->buffers[0].len = data_len;\n+\t\treturn 0;\n+\t}\n+\n+\tbuf = buf->next;\n+\twhile (buf) {\n+\t\tif (unlikely(nr == QAT_SGL_MAX_NUMBER)) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"QAT PMD exceeded size of QAT SGL entry(%u)\",\n+\t\t\t\t\tQAT_SGL_MAX_NUMBER);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tlist->buffers[nr].len = rte_pktmbuf_data_len(buf);\n+\t\tlist->buffers[nr].resrvd = 0;\n+\t\tlist->buffers[nr].addr = rte_pktmbuf_iova(buf);\n+\n+\t\tbuf_len += list->buffers[nr].len;\n+\t\tbuf = buf->next;\n+\n+\t\tif (buf_len > data_len) {\n+\t\t\tlist->buffers[nr].len -=\n+\t\t\t\tbuf_len - data_len;\n+\t\t\tbuf = NULL;\n+\t\t}\n+\t\t++nr;\n+\t}\n+\tlist->num_bufs = nr;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/qat/qat_common.h b/drivers/crypto/qat/qat_common.h\nindex 193639550..77ffc8f72 100644\n--- a/drivers/crypto/qat/qat_common.h\n+++ b/drivers/crypto/qat/qat_common.h\n@@ -6,6 +6,8 @@\n \n #include <stdint.h>\n \n+#include <rte_mbuf.h>\n+\n /**< Intel(R) QAT Symmetric Crypto PMD device name */\n #define CRYPTODEV_NAME_QAT_SYM_PMD\tcrypto_qat\n \n@@ -45,11 +47,8 @@ struct qat_sgl {\n \tstruct qat_flat_buf buffers[QAT_SGL_MAX_NUMBER];\n } __rte_packed __rte_cache_aligned;\n \n-struct qat_sym_op_cookie {\n-\tstruct qat_sgl qat_sgl_src;\n-\tstruct qat_sgl qat_sgl_dst;\n-\tphys_addr_t qat_sgl_src_phys_addr;\n-\tphys_addr_t qat_sgl_dst_phys_addr;\n-};\n+int\n+qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buf_start,\n+\t\tstruct qat_sgl *list, uint32_t data_len);\n \n #endif /* _QAT_COMMON_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex a9beff064..b74dfa634 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -248,53 +248,6 @@ qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n \treturn qat_dequeue_op_burst(qp, (void **)ops, nb_ops);\n }\n \n-static inline int\n-qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,\n-\t\tstruct qat_sgl *list, uint32_t data_len)\n-{\n-\tint nr = 1;\n-\n-\tuint32_t buf_len = rte_pktmbuf_iova(buf) -\n-\t\t\tbuff_start + rte_pktmbuf_data_len(buf);\n-\n-\tlist->buffers[0].addr = buff_start;\n-\tlist->buffers[0].resrvd = 0;\n-\tlist->buffers[0].len = buf_len;\n-\n-\tif (data_len <= buf_len) {\n-\t\tlist->num_bufs = nr;\n-\t\tlist->buffers[0].len = data_len;\n-\t\treturn 0;\n-\t}\n-\n-\tbuf = buf->next;\n-\twhile (buf) {\n-\t\tif (unlikely(nr == QAT_SGL_MAX_NUMBER)) {\n-\t\t\tPMD_DRV_LOG(ERR, \"QAT PMD exceeded size of QAT SGL\"\n-\t\t\t\t\t\" entry(%u)\",\n-\t\t\t\t\tQAT_SGL_MAX_NUMBER);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tlist->buffers[nr].len = rte_pktmbuf_data_len(buf);\n-\t\tlist->buffers[nr].resrvd = 0;\n-\t\tlist->buffers[nr].addr = rte_pktmbuf_iova(buf);\n-\n-\t\tbuf_len += list->buffers[nr].len;\n-\t\tbuf = buf->next;\n-\n-\t\tif (buf_len > data_len) {\n-\t\t\tlist->buffers[nr].len -=\n-\t\t\t\tbuf_len - data_len;\n-\t\t\tbuf = NULL;\n-\t\t}\n-\t\t++nr;\n-\t}\n-\tlist->num_bufs = nr;\n-\n-\treturn 0;\n-}\n-\n static inline void\n set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,\n \t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param,\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex b92ec72de..37bec3ce3 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -22,6 +22,13 @@\n \n struct qat_sym_session;\n \n+struct qat_sym_op_cookie {\n+\tstruct qat_sgl qat_sgl_src;\n+\tstruct qat_sgl qat_sgl_dst;\n+\tphys_addr_t qat_sgl_src_phys_addr;\n+\tphys_addr_t qat_sgl_dst_phys_addr;\n+};\n+\n int\n qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen);\n",
    "prefixes": [
        "v3",
        "17/38"
    ]
}