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{
    "id": 41047,
    "url": "http://patches.dpdk.org/api/patches/41047/",
    "web_url": "http://patches.dpdk.org/patch/41047/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk"
    },
    "msgid": "<1528892062-4997-16-git-send-email-tomaszx.jozwiak@intel.com>",
    "date": "2018-06-13T12:13:59",
    "name": "[v3,15/38] crypto/qat: create structures to support various generations",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "912cfe62fc92f3312124b631e84e31fb2bd47a9e",
    "submitter": {
        "id": 949,
        "url": "http://patches.dpdk.org/api/people/949/",
        "name": "Tomasz Jozwiak",
        "email": "tomaszx.jozwiak@intel.com"
    },
    "delegate": {
        "id": 22,
        "url": "http://patches.dpdk.org/api/users/22/",
        "username": "pdelarag",
        "first_name": "Pablo",
        "last_name": "de Lara Guarch",
        "email": "pablo.de.lara.guarch@intel.com"
    },
    "mbox": "http://patches.dpdk.org/patch/41047/mbox/",
    "series": [
        {
            "id": 111,
            "url": "http://patches.dpdk.org/api/series/111/",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=111",
            "date": "2018-06-13T12:13:44",
            "name": "crypto/qat: refactor to support multiple services",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/111/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/41047/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/41047/checks/",
    "tags": {},
    "headers": {
        "X-Mailer": "git-send-email 2.7.4",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "Precedence": "list",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Date": "Wed, 13 Jun 2018 14:13:59 +0200",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Delivered-To": "patchwork@dpdk.org",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "To": "fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com,\n\tdev@dpdk.org",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<1523040732-3290-1-git-send-email-fiona.trahe@intel.com>\n\t<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-IronPort-AV": "E=Sophos;i=\"5.51,218,1526367600\"; d=\"scan'208\";a=\"63727711\"",
        "List-Post": "<mailto:dev@dpdk.org>",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 301F91EF4A;\n\tWed, 13 Jun 2018 14:15:05 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 608D51EF36\n\tfor <dev@dpdk.org>; Wed, 13 Jun 2018 14:15:00 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Jun 2018 05:14:58 -0700",
            "from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 13 Jun 2018 05:14:45 -0700"
        ],
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "X-Amp-File-Uploaded": "False",
        "Subject": "[dpdk-dev] [PATCH v3 15/38] crypto/qat: create structures to\n\tsupport various generations",
        "In-Reply-To": "<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>",
        "Message-Id": "<1528892062-4997-16-git-send-email-tomaszx.jozwiak@intel.com>",
        "X-ExtLoop1": "1",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "X-Original-To": "patchwork@dpdk.org"
    },
    "content": "From: Fiona Trahe <fiona.trahe@intel.com>\n\nCreate data structures to support different generations\nof qat hardware supplying services through different queue pairs.\n - Add two new structs qat_gen_hw_data and qat_qp_hw_dat\n - Add a qat_service_type enum\nAn array of qat_qp_hw_data elements is\ninitialised with constants, these are arranged so that the qp_id used\non the API can be used as an index to pick up the qp data to use.\nThe constants are common to current generations,\nnew arrays will be added for future generations.\n\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n .../qat/qat_adf/adf_transport_access_macros.h |  6 +-\n drivers/crypto/qat/qat_common.h               |  8 ++\n drivers/crypto/qat/qat_device.c               | 21 ++++-\n drivers/crypto/qat/qat_device.h               |  9 ++\n drivers/crypto/qat/qat_qp.c                   | 94 ++++++++++++++++++-\n drivers/crypto/qat/qat_qp.h                   | 18 +++-\n drivers/crypto/qat/qat_sym.c                  | 27 ++----\n 7 files changed, 154 insertions(+), 29 deletions(-)",
    "diff": "diff --git a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h\nindex 8b88b69de..2136d54ab 100644\n--- a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h\n+++ b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h\n@@ -51,7 +51,8 @@\n #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K\n \n #define ADF_NUM_BUNDLES_PER_DEV         1\n-#define ADF_NUM_SYM_QPS_PER_BUNDLE      2\n+/* Maximum number of qps for any service type */\n+#define ADF_MAX_QPS_PER_BUNDLE\t\t4\n #define ADF_RING_DIR_TX\t\t\t0\n #define ADF_RING_DIR_RX\t\t\t1\n \n@@ -132,4 +133,5 @@ do { \\\n #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \\\n \tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n \t\t\tADF_RING_CSR_INT_FLAG_AND_COL, value)\n-#endif\n+\n+#endif /*ADF_TRANSPORT_ACCESS_MACROS_H */\ndiff --git a/drivers/crypto/qat/qat_common.h b/drivers/crypto/qat/qat_common.h\nindex 7802e96f9..c3e7bd9a7 100644\n--- a/drivers/crypto/qat/qat_common.h\n+++ b/drivers/crypto/qat/qat_common.h\n@@ -23,6 +23,14 @@ enum qat_device_gen {\n \tQAT_GEN2,\n };\n \n+enum qat_service_type {\n+\tQAT_SERVICE_ASYMMETRIC = 0,\n+\tQAT_SERVICE_SYMMETRIC,\n+\tQAT_SERVICE_COMPRESSION,\n+\tQAT_SERVICE_INVALID\n+};\n+#define QAT_MAX_SERVICES\t\t(QAT_SERVICE_INVALID)\n+\n /**< Common struct for scatter-gather list operations */\n struct qat_alg_buf {\n \tuint32_t len;\ndiff --git a/drivers/crypto/qat/qat_device.c b/drivers/crypto/qat/qat_device.c\nindex ac6bd1af6..cdf4f7058 100644\n--- a/drivers/crypto/qat/qat_device.c\n+++ b/drivers/crypto/qat/qat_device.c\n@@ -4,6 +4,21 @@\n \n #include \"qat_device.h\"\n #include \"adf_transport_access_macros.h\"\n+#include \"qat_qp.h\"\n+\n+/* Hardware device information per generation */\n+__extension__\n+struct qat_gen_hw_data qp_gen_config[] =  {\n+\t[QAT_GEN1] = {\n+\t\t.dev_gen = QAT_GEN1,\n+\t\t.qp_hw_data = qat_gen1_qps,\n+\t},\n+\t[QAT_GEN2] = {\n+\t\t.dev_gen = QAT_GEN2,\n+\t\t.qp_hw_data = qat_gen1_qps,\n+\t\t/* gen2 has same ring layout as gen1 */\n+\t},\n+};\n \n int qat_dev_config(__rte_unused struct rte_cryptodev *dev,\n \t\t__rte_unused struct rte_cryptodev_config *config)\n@@ -42,12 +57,14 @@ void qat_dev_info_get(struct rte_cryptodev *dev,\n \t\t\tstruct rte_cryptodev_info *info)\n {\n \tstruct qat_pmd_private *internals = dev->data->dev_private;\n+\tconst struct qat_qp_hw_data *sym_hw_qps =\n+\t\tqp_gen_config[internals->qat_dev_gen]\n+\t\t\t      .qp_hw_data[QAT_SERVICE_SYMMETRIC];\n \n \tPMD_INIT_FUNC_TRACE();\n \tif (info != NULL) {\n \t\tinfo->max_nb_queue_pairs =\n-\t\t\t\tADF_NUM_SYM_QPS_PER_BUNDLE *\n-\t\t\t\tADF_NUM_BUNDLES_PER_DEV;\n+\t\t\tqat_qps_per_service(sym_hw_qps, QAT_SERVICE_SYMMETRIC);\n \t\tinfo->feature_flags = dev->feature_flags;\n \t\tinfo->capabilities = internals->qat_dev_capabilities;\n \t\tinfo->sym.max_nb_sessions = internals->max_nb_sessions;\ndiff --git a/drivers/crypto/qat/qat_device.h b/drivers/crypto/qat/qat_device.h\nindex 64706abae..0983e3c2e 100644\n--- a/drivers/crypto/qat/qat_device.h\n+++ b/drivers/crypto/qat/qat_device.h\n@@ -8,6 +8,8 @@\n #include <rte_bus_pci.h>\n #include \"qat_common.h\"\n #include \"qat_logs.h\"\n+#include \"adf_transport_access_macros.h\"\n+#include \"qat_qp.h\"\n \n extern uint8_t cryptodev_qat_driver_id;\n \n@@ -34,6 +36,13 @@ struct qat_pmd_private {\n \t/**< Device ID for this instance */\n };\n \n+struct qat_gen_hw_data {\n+\tenum qat_device_gen dev_gen;\n+\tconst struct qat_qp_hw_data (*qp_hw_data)[ADF_MAX_QPS_PER_BUNDLE];\n+};\n+\n+extern struct qat_gen_hw_data qp_gen_config[];\n+\n int qat_dev_config(struct rte_cryptodev *dev,\n \t\tstruct rte_cryptodev_config *config);\n int qat_dev_start(struct rte_cryptodev *dev);\ndiff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c\nindex b831ab420..656645e4c 100644\n--- a/drivers/crypto/qat/qat_qp.c\n+++ b/drivers/crypto/qat/qat_qp.c\n@@ -13,10 +13,10 @@\n \n #include \"qat_logs.h\"\n #include \"qat_qp.h\"\n-#include \"qat_sym.h\"\n-\n+#include \"qat_device.h\"\n #include \"adf_transport_access_macros.h\"\n \n+\n #define ADF_MAX_DESC\t\t\t\t4096\n #define ADF_MIN_DESC\t\t\t\t128\n \n@@ -27,6 +27,78 @@\n \tADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \\\n \t(ADF_ARB_REG_SLOT * index), value)\n \n+__extension__\n+const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]\n+\t\t\t\t\t [ADF_MAX_QPS_PER_BUNDLE] = {\n+\t/* queue pairs which provide an asymmetric crypto service */\n+\t[QAT_SERVICE_ASYMMETRIC] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 0,\n+\t\t\t.rx_ring_num = 8,\n+\t\t\t.tx_msg_size = 64,\n+\t\t\t.rx_msg_size = 32,\n+\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_ASYMMETRIC,\n+\t\t\t.tx_ring_num = 1,\n+\t\t\t.rx_ring_num = 9,\n+\t\t\t.tx_msg_size = 64,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_INVALID,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_INVALID,\n+\t\t}\n+\t},\n+\t/* queue pairs which provide a symmetric crypto service */\n+\t[QAT_SERVICE_SYMMETRIC] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 2,\n+\t\t\t.rx_ring_num = 10,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t},\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_SYMMETRIC,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 3,\n+\t\t\t.rx_ring_num = 11,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_INVALID,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_INVALID,\n+\t\t}\n+\t},\n+\t/* queue pairs which provide a compression service */\n+\t[QAT_SERVICE_COMPRESSION] = {\n+\t\t{\n+\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 6,\n+\t\t\t.rx_ring_num = 14,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_COMPRESSION,\n+\t\t\t.hw_bundle_num = 0,\n+\t\t\t.tx_ring_num = 7,\n+\t\t\t.rx_ring_num = 15,\n+\t\t\t.tx_msg_size = 128,\n+\t\t\t.rx_msg_size = 32,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_INVALID,\n+\t\t}, {\n+\t\t\t.service_type = QAT_SERVICE_INVALID,\n+\t\t}\n+\t}\n+};\n+\n static int qat_qp_check_queue_alignment(uint64_t phys_addr,\n \tuint32_t queue_size_bytes);\n static void qat_queue_delete(struct qat_queue *queue);\n@@ -38,6 +110,18 @@ static void adf_configure_queues(struct qat_qp *queue);\n static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr);\n static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr);\n \n+\n+int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,\n+\t\tenum qat_service_type service)\n+{\n+\tint i, count;\n+\n+\tfor (i = 0, count = 0; i < ADF_MAX_QPS_PER_BUNDLE; i++)\n+\t\tif (qp_hw_data[i].service_type == service)\n+\t\t\tcount++;\n+\treturn count * ADF_NUM_BUNDLES_PER_DEV;\n+}\n+\n static const struct rte_memzone *\n queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,\n \t\t\tint socket_id)\n@@ -247,12 +331,12 @@ qat_queue_create(struct qat_pmd_private *qat_dev, struct qat_queue *queue,\n \tstruct rte_pci_device *pci_dev = qat_dev->pci_dev;\n \tint ret = 0;\n \tuint16_t desc_size = (dir == ADF_RING_DIR_TX ?\n-\t\t\t\tqp_conf->tx_msg_size : qp_conf->rx_msg_size);\n+\t\t\tqp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);\n \tuint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);\n \n-\tqueue->hw_bundle_number = qp_conf->hw_bundle_num;\n+\tqueue->hw_bundle_number = qp_conf->hw->hw_bundle_num;\n \tqueue->hw_queue_number = (dir == ADF_RING_DIR_TX ?\n-\t\t\tqp_conf->tx_ring_num : qp_conf->rx_ring_num);\n+\t\t\tqp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);\n \n \tif (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {\n \t\tPMD_DRV_LOG(ERR, \"Invalid descriptor size %d\", desc_size);\ndiff --git a/drivers/crypto/qat/qat_qp.h b/drivers/crypto/qat/qat_qp.h\nindex 8cf072c55..f808e16a5 100644\n--- a/drivers/crypto/qat/qat_qp.h\n+++ b/drivers/crypto/qat/qat_qp.h\n@@ -5,7 +5,8 @@\n #define _QAT_QP_H_\n \n #include \"qat_common.h\"\n-#include \"qat_device.h\"\n+#include <rte_cryptodev_pmd.h>\n+#include \"adf_transport_access_macros.h\"\n \n #define QAT_CSR_HEAD_WRITE_THRESH 32U\n /* number of requests to accumulate before writing head CSR */\n@@ -27,12 +28,19 @@ typedef int (*process_response_t)(void **ops,\n /**\n  * Structure with data needed for creation of queue pair.\n  */\n-struct qat_qp_config {\n+struct qat_qp_hw_data {\n+\tenum qat_service_type service_type;\n \tuint8_t hw_bundle_num;\n \tuint8_t tx_ring_num;\n \tuint8_t rx_ring_num;\n \tuint16_t tx_msg_size;\n \tuint16_t rx_msg_size;\n+};\n+/**\n+ * Structure with data needed for creation of queue pair.\n+ */\n+struct qat_qp_config {\n+\tconst struct qat_qp_hw_data *hw;\n \tuint32_t nb_descriptors;\n \tuint32_t cookie_size;\n \tint socket_id;\n@@ -81,6 +89,8 @@ struct qat_qp {\n \t/**< qat device this qp is on */\n } __rte_cache_aligned;\n \n+extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_PER_BUNDLE];\n+\n uint16_t\n qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);\n \n@@ -94,4 +104,8 @@ int\n qat_qp_setup(struct qat_pmd_private *qat_dev,\n \t\tstruct qat_qp **qp_addr, uint16_t queue_pair_id,\n \t\tstruct qat_qp_config *qat_qp_conf);\n+\n+int\n+qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,\n+\t\t\tenum qat_service_type service);\n #endif /* _QAT_QP_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 8ab95ac43..e448dc859 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -16,6 +16,7 @@\n #include \"qat_sym.h\"\n #include \"qat_qp.h\"\n #include \"adf_transport_access_macros.h\"\n+#include \"qat_device.h\"\n \n #define BYTE_LENGTH    8\n /* bpi is only used for partial blocks of DES and AES\n@@ -23,12 +24,6 @@\n  */\n #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ\n \n-#define ADF_SYM_TX_RING_DESC_SIZE\t\t128\n-#define ADF_SYM_RX_RING_DESC_SIZE\t\t32\n-#define ADF_SYM_TX_QUEUE_STARTOFF\t\t2\n-/* Offset from bundle start to 1st Sym Tx queue */\n-#define ADF_SYM_RX_QUEUE_STARTOFF\t\t10\n-\n /** Encrypt a single partial block\n  *  Depends on openssl libcrypto\n  *  Uses ECB+XOR to do CFB encryption, same result, more performant\n@@ -805,12 +800,11 @@ void qat_sym_stats_reset(struct rte_cryptodev *dev)\n \tPMD_DRV_LOG(DEBUG, \"QAT crypto: stats cleared\");\n }\n \n-\n-\n int qat_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)\n {\n \tPMD_DRV_LOG(DEBUG, \"Release sym qp %u on device %d\",\n \t\t\t\tqueue_pair_id, dev->data->dev_id);\n+\n \treturn qat_qp_release((struct qat_qp **)\n \t\t\t&(dev->data->queue_pairs[queue_pair_id]));\n }\n@@ -823,9 +817,14 @@ int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tint ret = 0;\n \tuint32_t i;\n \tstruct qat_qp_config qat_qp_conf;\n+\n \tstruct qat_qp **qp_addr =\n \t\t\t(struct qat_qp **)&(dev->data->queue_pairs[qp_id]);\n \tstruct qat_pmd_private *qat_private = dev->data->dev_private;\n+\tconst struct qat_qp_hw_data *sym_hw_qps =\n+\t\t\tqp_gen_config[qat_private->qat_dev_gen]\n+\t\t\t\t      .qp_hw_data[QAT_SERVICE_SYMMETRIC];\n+\tconst struct qat_qp_hw_data *qp_hw_data = sym_hw_qps + qp_id;\n \n \t/* If qp is already in use free ring memory and qp metadata. */\n \tif (*qp_addr != NULL) {\n@@ -833,19 +832,12 @@ int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tif (ret < 0)\n \t\t\treturn ret;\n \t}\n-\tif (qp_id >= (ADF_NUM_SYM_QPS_PER_BUNDLE *\n-\t\t\t\t\tADF_NUM_BUNDLES_PER_DEV)) {\n+\tif (qp_id >= qat_qps_per_service(sym_hw_qps, QAT_SERVICE_SYMMETRIC)) {\n \t\tPMD_DRV_LOG(ERR, \"qp_id %u invalid for this device\", qp_id);\n \t\treturn -EINVAL;\n \t}\n \n-\tqat_qp_conf.hw_bundle_num = (qp_id/ADF_NUM_SYM_QPS_PER_BUNDLE);\n-\tqat_qp_conf.tx_ring_num = (qp_id%ADF_NUM_SYM_QPS_PER_BUNDLE) +\n-\t\t\tADF_SYM_TX_QUEUE_STARTOFF;\n-\tqat_qp_conf.rx_ring_num = (qp_id%ADF_NUM_SYM_QPS_PER_BUNDLE) +\n-\t\t\tADF_SYM_RX_QUEUE_STARTOFF;\n-\tqat_qp_conf.tx_msg_size = ADF_SYM_TX_RING_DESC_SIZE;\n-\tqat_qp_conf.rx_msg_size = ADF_SYM_RX_RING_DESC_SIZE;\n+\tqat_qp_conf.hw = qp_hw_data;\n \tqat_qp_conf.build_request = qat_sym_build_request;\n \tqat_qp_conf.process_response = qat_sym_process_response;\n \tqat_qp_conf.cookie_size = sizeof(struct qat_sym_op_cookie);\n@@ -876,5 +868,4 @@ int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t}\n \n \treturn ret;\n-\n }\n",
    "prefixes": [
        "v3",
        "15/38"
    ]
}