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GET /api/patches/41041/?format=api
{ "id": 41041, "url": "http://patches.dpdk.org/api/patches/41041/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1528892062-4997-9-git-send-email-tomaszx.jozwiak@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1528892062-4997-9-git-send-email-tomaszx.jozwiak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1528892062-4997-9-git-send-email-tomaszx.jozwiak@intel.com", "date": "2018-06-13T12:13:52", "name": "[v3,08/38] crypto/qat: make enqueue function generic", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f64e7fa00fe32b5db90303fd914fe8aa5dc3671f", "submitter": { "id": 949, "url": "http://patches.dpdk.org/api/people/949/?format=api", "name": "Tomasz Jozwiak", "email": "tomaszx.jozwiak@intel.com" }, "delegate": { "id": 22, "url": "http://patches.dpdk.org/api/users/22/?format=api", "username": "pdelarag", "first_name": "Pablo", "last_name": "de Lara Guarch", "email": "pablo.de.lara.guarch@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1528892062-4997-9-git-send-email-tomaszx.jozwiak@intel.com/mbox/", "series": [ { "id": 111, "url": "http://patches.dpdk.org/api/series/111/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=111", "date": "2018-06-13T12:13:44", "name": "crypto/qat: refactor to support multiple services", "version": 3, "mbox": "http://patches.dpdk.org/series/111/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/41041/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/41041/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 26E271EF50;\n\tWed, 13 Jun 2018 14:14:44 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id ADABF1D9C1\n\tfor <dev@dpdk.org>; Wed, 13 Jun 2018 14:14:38 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t13 Jun 2018 05:14:38 -0700", "from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain)\n\t([10.103.104.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 13 Jun 2018 05:14:37 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.51,218,1526367600\"; d=\"scan'208\";a=\"63727675\"", "From": "Tomasz Jozwiak <tomaszx.jozwiak@intel.com>", "To": "fiona.trahe@intel.com,\n\ttomaszx.jozwiak@intel.com,\n\tdev@dpdk.org", "Date": "Wed, 13 Jun 2018 14:13:52 +0200", "Message-Id": "<1528892062-4997-9-git-send-email-tomaszx.jozwiak@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>", "References": "<1523040732-3290-1-git-send-email-fiona.trahe@intel.com>\n\t<1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 08/38] crypto/qat: make enqueue function\n\tgeneric", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Fiona Trahe <fiona.trahe@intel.com>\n\nQueue-handling code in enqueue is made generic, so it can\nbe used by other services in future. This is done by\n - Removing all sym-specific refs in input params - replace with void ptrs.\n - Wrapping this generic enqueue with the sym-specific enqueue\n called through the API.\n - Setting a fn ptr for build_request in qp on qp creation\n - Passing void * params to this, in the service-specific implementation\n qat_sym_build_request cast back to sym structs.\n\nSigned-off-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n drivers/crypto/qat/qat_qp.c | 1 +\n drivers/crypto/qat/qat_sym.c | 46 ++++++++++++++++++++----------------\n drivers/crypto/qat/qat_sym.h | 11 +++++++++\n 3 files changed, 38 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c\nindex fb9c2a7ef..d7d79f1af 100644\n--- a/drivers/crypto/qat/qat_qp.c\n+++ b/drivers/crypto/qat/qat_qp.c\n@@ -197,6 +197,7 @@ int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,\n \tstruct qat_pmd_private *internals\n \t\t= dev->data->dev_private;\n \tqp->qat_dev_gen = internals->qat_dev_gen;\n+\tqp->build_request = qat_sym_build_request;\n \n \tdev->data->queue_pairs[queue_pair_id] = qp;\n \treturn 0;\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex 2dfdc9cce..4e404749a 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -86,10 +86,6 @@ bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,\n static inline uint32_t\n adf_modulo(uint32_t data, uint32_t shift);\n \n-static inline int\n-qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,\n-\t\tstruct qat_sym_op_cookie *qat_op_cookie, struct qat_qp *qp);\n-\n static inline uint32_t\n qat_bpicipher_preprocess(struct qat_sym_session *ctx,\n \t\t\t\tstruct rte_crypto_op *op)\n@@ -209,14 +205,12 @@ txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {\n \tq->csr_tail = q->tail;\n }\n \n-uint16_t\n-qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n-\t\tuint16_t nb_ops)\n+static uint16_t\n+qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)\n {\n \tregister struct qat_queue *queue;\n \tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n \tregister uint32_t nb_ops_sent = 0;\n-\tregister struct rte_crypto_op **cur_op = ops;\n \tregister int ret;\n \tuint16_t nb_ops_possible = nb_ops;\n \tregister uint8_t *base_addr;\n@@ -242,8 +236,9 @@ qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t}\n \n \twhile (nb_ops_sent != nb_ops_possible) {\n-\t\tret = qat_sym_build_request(*cur_op, base_addr + tail,\n-\t\t\ttmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);\n+\t\tret = tmp_qp->build_request(*ops, base_addr + tail,\n+\t\t\t\ttmp_qp->op_cookies[tail / queue->msg_size],\n+\t\t\t\ttmp_qp->qat_dev_gen);\n \t\tif (ret != 0) {\n \t\t\ttmp_qp->stats.enqueue_err_count++;\n \t\t\t/*\n@@ -257,8 +252,8 @@ qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\t}\n \n \t\ttail = adf_modulo(tail + queue->msg_size, queue->modulo);\n+\t\tops++;\n \t\tnb_ops_sent++;\n-\t\tcur_op++;\n \t}\n kick_tail:\n \tqueue->tail = tail;\n@@ -298,6 +293,13 @@ void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)\n \t\t\t q->hw_queue_number, new_head);\n }\n \n+uint16_t\n+qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,\n+\t\tuint16_t nb_ops)\n+{\n+\treturn qat_enqueue_op_burst(qp, (void **)ops, nb_ops);\n+}\n+\n uint16_t\n qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,\n \t\tuint16_t nb_ops)\n@@ -456,9 +458,10 @@ set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,\n \t\t\tiv_length);\n }\n \n-static inline int\n-qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,\n-\t\tstruct qat_sym_op_cookie *qat_op_cookie, struct qat_qp *qp)\n+\n+int\n+qat_sym_build_request(void *in_op, uint8_t *out_msg,\n+\t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen)\n {\n \tint ret = 0;\n \tstruct qat_sym_session *ctx;\n@@ -471,6 +474,9 @@ qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,\n \tuint32_t min_ofs = 0;\n \tuint64_t src_buf_start = 0, dst_buf_start = 0;\n \tuint8_t do_sgl = 0;\n+\tstruct rte_crypto_op *op = (struct rte_crypto_op *)in_op;\n+\tstruct qat_sym_op_cookie *cookie =\n+\t\t\t\t(struct qat_sym_op_cookie *)op_cookie;\n \n #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX\n \tif (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {\n@@ -494,7 +500,7 @@ qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {\n+\tif (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {\n \t\tPMD_DRV_LOG(ERR, \"Session alg not supported on this device gen\");\n \t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n \t\treturn -EINVAL;\n@@ -807,7 +813,7 @@ qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,\n \t\tICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,\n \t\t\t\tQAT_COMN_PTR_TYPE_SGL);\n \t\tret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,\n-\t\t\t\t&qat_op_cookie->qat_sgl_list_src,\n+\t\t\t\t&cookie->qat_sgl_list_src,\n \t\t\t\tqat_req->comn_mid.src_length);\n \t\tif (ret) {\n \t\t\tPMD_DRV_LOG(ERR, \"QAT PMD Cannot fill sgl array\");\n@@ -817,11 +823,11 @@ qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,\n \t\tif (likely(op->sym->m_dst == NULL))\n \t\t\tqat_req->comn_mid.dest_data_addr =\n \t\t\t\tqat_req->comn_mid.src_data_addr =\n-\t\t\t\tqat_op_cookie->qat_sgl_src_phys_addr;\n+\t\t\t\tcookie->qat_sgl_src_phys_addr;\n \t\telse {\n \t\t\tret = qat_sgl_fill_array(op->sym->m_dst,\n \t\t\t\t\tdst_buf_start,\n-\t\t\t\t\t&qat_op_cookie->qat_sgl_list_dst,\n+\t\t\t\t\t&cookie->qat_sgl_list_dst,\n \t\t\t\t\t\tqat_req->comn_mid.dst_length);\n \n \t\t\tif (ret) {\n@@ -831,9 +837,9 @@ qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,\n \t\t\t}\n \n \t\t\tqat_req->comn_mid.src_data_addr =\n-\t\t\t\tqat_op_cookie->qat_sgl_src_phys_addr;\n+\t\t\t\tcookie->qat_sgl_src_phys_addr;\n \t\t\tqat_req->comn_mid.dest_data_addr =\n-\t\t\t\t\tqat_op_cookie->qat_sgl_dst_phys_addr;\n+\t\t\t\t\tcookie->qat_sgl_dst_phys_addr;\n \t\t}\n \t} else {\n \t\tqat_req->comn_mid.src_data_addr = src_buf_start;\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex 18c77ea11..b1ddb6e93 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -27,6 +27,11 @@\n #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U\n /* number of inflights below which no tail write coalescing should occur */\n \n+typedef int (*build_request_t)(void *op,\n+\t\tuint8_t *req, void *op_cookie,\n+\t\tenum qat_device_gen qat_dev_gen);\n+/**< Build a request from an op. */\n+\n struct qat_sym_session;\n \n /**\n@@ -63,8 +68,14 @@ struct qat_qp {\n \tvoid **op_cookies;\n \tuint32_t nb_descriptors;\n \tenum qat_device_gen qat_dev_gen;\n+\tbuild_request_t build_request;\n } __rte_cache_aligned;\n \n+\n+int\n+qat_sym_build_request(void *in_op, uint8_t *out_msg,\n+\t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen);\n+\n void qat_sym_stats_get(struct rte_cryptodev *dev,\n \tstruct rte_cryptodev_stats *stats);\n void qat_sym_stats_reset(struct rte_cryptodev *dev);\n", "prefixes": [ "v3", "08/38" ] }