get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/40976/
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40976,
    "url": "http://patches.dpdk.org/api/patches/40976/",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180611110123.9682-1-mk@semihalf.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20180611110123.9682-1-mk@semihalf.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20180611110123.9682-1-mk@semihalf.com",
    "date": "2018-06-11T11:01:23",
    "name": "[v5,02/27] net/ena: update ena_com to the newer version",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "fbeecd66e0ef40584f2e95588f5817a810005afc",
    "submitter": {
        "id": 786,
        "url": "http://patches.dpdk.org/api/people/786/",
        "name": "Michał Krawczyk",
        "email": "mk@semihalf.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180611110123.9682-1-mk@semihalf.com/mbox/",
    "series": [
        {
            "id": 79,
            "url": "http://patches.dpdk.org/api/series/79/",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=79",
            "date": "2018-06-11T11:00:08",
            "name": "net/ena: new features and fixes",
            "version": 5,
            "mbox": "http://patches.dpdk.org/series/79/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/40976/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/40976/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Subject": "[dpdk-dev] [PATCH v5 02/27] net/ena: update ena_com to the newer\n\tversion",
        "List-Post": "<mailto:dev@dpdk.org>",
        "X-Mailer": "git-send-email 2.14.1",
        "X-Original-To": "patchwork@dpdk.org",
        "Cc": "dev@dpdk.org,\n\tmatua@amazon.com,\n\tRafal Kozik <rk@semihalf.com>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "From": "Michal Krawczyk <mk@semihalf.com>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-BeenThere": "dev@dpdk.org",
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=5d7KeXFSMqFlwGxgF/9CyMAW/QjUJSZDiXzL9Ghj3No=;\n\tb=FcGpgsw6EvlKr+JLA8NlGfj5KGLRY8XVuRrWPW1RPfI98FfKZpsV21q22ujjxV2ESW\n\t+d1rGClfHw2IrpTL5PIPyGRGlIo5erPUK8rRxbYgu2sRIAKe8O09OXBWm98RF5eHjTi6\n\tUnxC7C2+L/KQqXS9G9lyhoEFVhe/NaQ1d940LQHN+Px8FmajJgqJLR2FGVUQ60SardtQ\n\taMlYaC5fcoe4rDcmdm02IcTGUQzBwGcCV4rWKlNFJ87TCptSKKfq7uPeiMm/Xsra0MzD\n\tdliSZL89kCDRkrzg0kDDGP60A+tjYX8IAVNVPAsOm/MrtuwnXaVWdAyla/4WedwKtK4f\n\tZalg==",
        "X-Gm-Message-State": "APt69E1F5nGeXmM0IxvviTpDYYpy/ngznkxKzZ4Em4hNsSPtH836AHH7\n\tZfB2z5OZYfPOzyGVe5KfL4JnduIvCI0=",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=semihalf-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=5d7KeXFSMqFlwGxgF/9CyMAW/QjUJSZDiXzL9Ghj3No=;\n\tb=XA4Uc3d7QYWSH4g9Lasm3upJW+qkZ1xr++CSCjc3J5WzTwBeyOTYRyzqTSfTpWDUjh\n\tbNep+JlJ4Sb+8koxqhiVNd51N0ne3qZ+jfjaUp2gTtVsFijkLiNXiocVtZDdAb7LbMHd\n\tiREDAWAdAhjKtoaVkz3U8K1VhdBa+3MOu3UkRtwybpY5UlgAt+wDydqej3CijmLJ1mYo\n\tO29EgKDXFDV+g2iUvi3lrpfZeM6sbIMbdz/7HB3HaXLNx+KuWEUgIhjmH99zoAocTawT\n\t9mGYtAfio1uTxRreG6ZnzXAod6oIYOKTXLFGzUBsfHdz8td3gq9kW+ueYd2D5fF2w//E\n\tZTVQ==",
        "Date": "Mon, 11 Jun 2018 13:01:23 +0200",
        "In-Reply-To": "<f9dfdb44-b197-8ed3-1607-2d0cc8aa364c@intel.com>",
        "Message-Id": "<20180611110123.9682-1-mk@semihalf.com>",
        "X-Mailman-Version": "2.1.15",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<f9dfdb44-b197-8ed3-1607-2d0cc8aa364c@intel.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "Precedence": "list",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 261FC1E324;\n\tMon, 11 Jun 2018 13:01:36 +0200 (CEST)",
            "from mail-lf0-f67.google.com (mail-lf0-f67.google.com\n\t[209.85.215.67]) by dpdk.org (Postfix) with ESMTP id B0EFE1E323\n\tfor <dev@dpdk.org>; Mon, 11 Jun 2018 13:01:34 +0200 (CEST)",
            "by mail-lf0-f67.google.com with SMTP id g21-v6so27889332lfb.4\n\tfor <dev@dpdk.org>; Mon, 11 Jun 2018 04:01:34 -0700 (PDT)",
            "from mkPC.semihalf.local (31-172-191-173.noc.fibertech.net.pl.\n\t[31.172.191.173]) by smtp.gmail.com with ESMTPSA id\n\ts14-v6sm3404912lfg.88.2018.06.11.04.01.31\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 11 Jun 2018 04:01:31 -0700 (PDT)"
        ],
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "X-Google-Smtp-Source": "ADUXVKKCUMmjM7gkwwrH6lY4LHlgxRUF1oAu4ox5Y6j1TFG91A9N0PoN/xpp8m1uC/NbIFPfgBfeiw==",
        "X-Received": "by 2002:a19:6550:: with SMTP id\n\tc16-v6mr2145588lfj.31.1528714892809; \n\tMon, 11 Jun 2018 04:01:32 -0700 (PDT)",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "To": "ferruh.yigit@intel.com, Marcin Wojtas <mw@semihalf.com>,\n\tMichal Krawczyk <mk@semihalf.com>, Guy Tzalik <gtzalik@amazon.com>,\n\tEvgeny Schemeilin <evgenys@amazon.com>"
    },
    "content": "ena_com is the HAL provided by the vendor and it shouldn't be modified\nby the driver developers.\n\nThe PMD and platform file was adjusted for the new version of the\nena_com:\n    * Do not use deprecated meta descriptor fields\n    * Add empty AENQ handler structure with unimplemented handlers\n    * Add memzone allocations count to ena_ethdev.c file - it was\n      removed from ena_com.c file\n    * Add new macros used in new ena_com files\n    * Use error code ENA_COM_UNSUPPORTED instead of ENA_COM_PERMISSION\n\nSigned-off-by: Michal Krawczyk <mk@semihalf.com>\nSigned-off-by: Rafal Kozik <rk@semihalf.com>\n---\n drivers/net/ena/base/ena_com.c                  |  711 +++++++-------\n drivers/net/ena/base/ena_com.h                  |  112 +--\n drivers/net/ena/base/ena_defs/ena_admin_defs.h  | 1164 +++++++----------------\n drivers/net/ena/base/ena_defs/ena_common_defs.h |    8 +-\n drivers/net/ena/base/ena_defs/ena_eth_io_defs.h |  758 +++++----------\n drivers/net/ena/base/ena_defs/ena_gen_info.h    |    4 +-\n drivers/net/ena/base/ena_defs/ena_includes.h    |    2 -\n drivers/net/ena/base/ena_defs/ena_regs_defs.h   |   36 +\n drivers/net/ena/base/ena_eth_com.c              |   78 +-\n drivers/net/ena/base/ena_eth_com.h              |   10 +-\n drivers/net/ena/base/ena_plat.h                 |    2 -\n drivers/net/ena/base/ena_plat_dpdk.h            |   39 +-\n drivers/net/ena/ena_ethdev.c                    |   54 +-\n 13 files changed, 1115 insertions(+), 1863 deletions(-)",
    "diff": "diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c\nindex 38a058775..4abf1a28a 100644\n--- a/drivers/net/ena/base/ena_com.c\n+++ b/drivers/net/ena/base/ena_com.c\n@@ -37,11 +37,19 @@\n /*****************************************************************************/\n \n /* Timeout in micro-sec */\n-#define ADMIN_CMD_TIMEOUT_US (1000000)\n+#define ADMIN_CMD_TIMEOUT_US (3000000)\n \n-#define ENA_ASYNC_QUEUE_DEPTH 4\n+#define ENA_ASYNC_QUEUE_DEPTH 16\n #define ENA_ADMIN_QUEUE_DEPTH 32\n \n+#ifdef ENA_EXTENDED_STATS\n+\n+#define ENA_HISTOGRAM_ACTIVE_MASK_OFFSET 0xF08\n+#define ENA_EXTENDED_STAT_GET_FUNCT(_funct_queue) (_funct_queue & 0xFFFF)\n+#define ENA_EXTENDED_STAT_GET_QUEUE(_funct_queue) (_funct_queue >> 16)\n+\n+#endif /* ENA_EXTENDED_STATS */\n+\n #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \\\n \t\tENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \\\n \t\t| (ENA_COMMON_SPEC_VERSION_MINOR))\n@@ -62,7 +70,9 @@\n \n #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF\n \n-static int ena_alloc_cnt;\n+#define ENA_REGS_ADMIN_INTR_MASK 1\n+\n+#define ENA_POLL_MS\t5\n \n /*****************************************************************************/\n /*****************************************************************************/\n@@ -86,6 +96,11 @@ struct ena_comp_ctx {\n \tbool occupied;\n };\n \n+struct ena_com_stats_ctx {\n+\tstruct ena_admin_aq_get_stats_cmd get_cmd;\n+\tstruct ena_admin_acq_get_stats_resp get_resp;\n+};\n+\n static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,\n \t\t\t\t       struct ena_common_mem_addr *ena_addr,\n \t\t\t\t       dma_addr_t addr)\n@@ -95,50 +110,49 @@ static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,\n \t\treturn ENA_COM_INVAL;\n \t}\n \n-\tena_addr->mem_addr_low = (u32)addr;\n-\tena_addr->mem_addr_high =\n-\t\t((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 32)) >> 32);\n+\tena_addr->mem_addr_low = lower_32_bits(addr);\n+\tena_addr->mem_addr_high = (u16)upper_32_bits(addr);\n \n \treturn 0;\n }\n \n static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)\n {\n-\tENA_MEM_ALLOC_COHERENT(queue->q_dmadev,\n-\t\t\t       ADMIN_SQ_SIZE(queue->q_depth),\n-\t\t\t       queue->sq.entries,\n-\t\t\t       queue->sq.dma_addr,\n-\t\t\t       queue->sq.mem_handle);\n+\tstruct ena_com_admin_sq *sq = &queue->sq;\n+\tu16 size = ADMIN_SQ_SIZE(queue->q_depth);\n \n-\tif (!queue->sq.entries) {\n+\tENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,\n+\t\t\t       sq->mem_handle);\n+\n+\tif (!sq->entries) {\n \t\tena_trc_err(\"memory allocation failed\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n \n-\tqueue->sq.head = 0;\n-\tqueue->sq.tail = 0;\n-\tqueue->sq.phase = 1;\n+\tsq->head = 0;\n+\tsq->tail = 0;\n+\tsq->phase = 1;\n \n-\tqueue->sq.db_addr = NULL;\n+\tsq->db_addr = NULL;\n \n \treturn 0;\n }\n \n static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)\n {\n-\tENA_MEM_ALLOC_COHERENT(queue->q_dmadev,\n-\t\t\t       ADMIN_CQ_SIZE(queue->q_depth),\n-\t\t\t       queue->cq.entries,\n-\t\t\t       queue->cq.dma_addr,\n-\t\t\t       queue->cq.mem_handle);\n+\tstruct ena_com_admin_cq *cq = &queue->cq;\n+\tu16 size = ADMIN_CQ_SIZE(queue->q_depth);\n+\n+\tENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,\n+\t\t\t       cq->mem_handle);\n \n-\tif (!queue->cq.entries)  {\n+\tif (!cq->entries)  {\n \t\tena_trc_err(\"memory allocation failed\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n \n-\tqueue->cq.head = 0;\n-\tqueue->cq.phase = 1;\n+\tcq->head = 0;\n+\tcq->phase = 1;\n \n \treturn 0;\n }\n@@ -146,44 +160,44 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)\n static int ena_com_admin_init_aenq(struct ena_com_dev *dev,\n \t\t\t\t   struct ena_aenq_handlers *aenq_handlers)\n {\n+\tstruct ena_com_aenq *aenq = &dev->aenq;\n \tu32 addr_low, addr_high, aenq_caps;\n+\tu16 size;\n \n \tdev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;\n-\tENA_MEM_ALLOC_COHERENT(dev->dmadev,\n-\t\t\t       ADMIN_AENQ_SIZE(dev->aenq.q_depth),\n-\t\t\t       dev->aenq.entries,\n-\t\t\t       dev->aenq.dma_addr,\n-\t\t\t       dev->aenq.mem_handle);\n+\tsize = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);\n+\tENA_MEM_ALLOC_COHERENT(dev->dmadev, size,\n+\t\t\taenq->entries,\n+\t\t\taenq->dma_addr,\n+\t\t\taenq->mem_handle);\n \n-\tif (!dev->aenq.entries) {\n+\tif (!aenq->entries) {\n \t\tena_trc_err(\"memory allocation failed\");\n \t\treturn ENA_COM_NO_MEM;\n \t}\n \n-\tdev->aenq.head = dev->aenq.q_depth;\n-\tdev->aenq.phase = 1;\n+\taenq->head = aenq->q_depth;\n+\taenq->phase = 1;\n \n-\taddr_low = ENA_DMA_ADDR_TO_UINT32_LOW(dev->aenq.dma_addr);\n-\taddr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(dev->aenq.dma_addr);\n+\taddr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);\n+\taddr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);\n \n-\tENA_REG_WRITE32(addr_low, (unsigned char *)dev->reg_bar\n-\t\t\t+ ENA_REGS_AENQ_BASE_LO_OFF);\n-\tENA_REG_WRITE32(addr_high, (unsigned char *)dev->reg_bar\n-\t\t\t+ ENA_REGS_AENQ_BASE_HI_OFF);\n+\tENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);\n+\tENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);\n \n \taenq_caps = 0;\n \taenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;\n \taenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<\n \t\tENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &\n \t\tENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;\n+\tENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);\n \n-\tENA_REG_WRITE32(aenq_caps, (unsigned char *)dev->reg_bar\n-\t\t\t+ ENA_REGS_AENQ_CAPS_OFF);\n-\n-\tif (unlikely(!aenq_handlers))\n+\tif (unlikely(!aenq_handlers)) {\n \t\tena_trc_err(\"aenq handlers pointer is NULL\\n\");\n+\t\treturn ENA_COM_INVAL;\n+\t}\n \n-\tdev->aenq.aenq_handlers = aenq_handlers;\n+\taenq->aenq_handlers = aenq_handlers;\n \n \treturn 0;\n }\n@@ -217,12 +231,11 @@ static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,\n \treturn &queue->comp_ctx[command_id];\n }\n \n-static struct ena_comp_ctx *\n-__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n-\t\t\t   struct ena_admin_aq_entry *cmd,\n-\t\t\t   size_t cmd_size_in_bytes,\n-\t\t\t   struct ena_admin_acq_entry *comp,\n-\t\t\t   size_t comp_size_in_bytes)\n+static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n+\t\t\t\t\t\t       struct ena_admin_aq_entry *cmd,\n+\t\t\t\t\t\t       size_t cmd_size_in_bytes,\n+\t\t\t\t\t\t       struct ena_admin_acq_entry *comp,\n+\t\t\t\t\t\t       size_t comp_size_in_bytes)\n {\n \tstruct ena_comp_ctx *comp_ctx;\n \tu16 tail_masked, cmd_id;\n@@ -234,12 +247,9 @@ __ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n \ttail_masked = admin_queue->sq.tail & queue_size_mask;\n \n \t/* In case of queue FULL */\n-\tcnt = admin_queue->sq.tail - admin_queue->sq.head;\n+\tcnt = ATOMIC32_READ(&admin_queue->outstanding_cmds);\n \tif (cnt >= admin_queue->q_depth) {\n-\t\tena_trc_dbg(\"admin queue is FULL (tail %d head %d depth: %d)\\n\",\n-\t\t\t    admin_queue->sq.tail,\n-\t\t\t    admin_queue->sq.head,\n-\t\t\t    admin_queue->q_depth);\n+\t\tena_trc_dbg(\"admin queue is full.\\n\");\n \t\tadmin_queue->stats.out_of_space++;\n \t\treturn ERR_PTR(ENA_COM_NO_SPACE);\n \t}\n@@ -253,6 +263,8 @@ __ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n \t\tENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;\n \n \tcomp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);\n+\tif (unlikely(!comp_ctx))\n+\t\treturn ERR_PTR(ENA_COM_INVAL);\n \n \tcomp_ctx->status = ENA_CMD_SUBMITTED;\n \tcomp_ctx->comp_size = (u32)comp_size_in_bytes;\n@@ -272,7 +284,8 @@ __ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n \tif (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))\n \t\tadmin_queue->sq.phase = !admin_queue->sq.phase;\n \n-\tENA_REG_WRITE32(admin_queue->sq.tail, admin_queue->sq.db_addr);\n+\tENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,\n+\t\t\tadmin_queue->sq.db_addr);\n \n \treturn comp_ctx;\n }\n@@ -298,12 +311,11 @@ static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)\n \treturn 0;\n }\n \n-static struct ena_comp_ctx *\n-ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n-\t\t\t struct ena_admin_aq_entry *cmd,\n-\t\t\t size_t cmd_size_in_bytes,\n-\t\t\t struct ena_admin_acq_entry *comp,\n-\t\t\t size_t comp_size_in_bytes)\n+static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n+\t\t\t\t\t\t     struct ena_admin_aq_entry *cmd,\n+\t\t\t\t\t\t     size_t cmd_size_in_bytes,\n+\t\t\t\t\t\t     struct ena_admin_acq_entry *comp,\n+\t\t\t\t\t\t     size_t comp_size_in_bytes)\n {\n \tunsigned long flags = 0;\n \tstruct ena_comp_ctx *comp_ctx;\n@@ -317,7 +329,7 @@ ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,\n \t\t\t\t\t      cmd_size_in_bytes,\n \t\t\t\t\t      comp,\n \t\t\t\t\t      comp_size_in_bytes);\n-\tif (unlikely(IS_ERR(comp_ctx)))\n+\tif (IS_ERR(comp_ctx))\n \t\tadmin_queue->running_state = false;\n \tENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);\n \n@@ -331,9 +343,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,\n \tsize_t size;\n \tint dev_node = 0;\n \n-\tENA_TOUCH(ctx);\n-\n-\tmemset(&io_sq->desc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));\n+\tmemset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));\n \n \tio_sq->desc_entry_size =\n \t\t(io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?\n@@ -347,23 +357,26 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,\n \t\t\t\t\t    size,\n \t\t\t\t\t    io_sq->desc_addr.virt_addr,\n \t\t\t\t\t    io_sq->desc_addr.phys_addr,\n+\t\t\t\t\t    io_sq->desc_addr.mem_handle,\n \t\t\t\t\t    ctx->numa_node,\n \t\t\t\t\t    dev_node);\n-\t\tif (!io_sq->desc_addr.virt_addr)\n+\t\tif (!io_sq->desc_addr.virt_addr) {\n \t\t\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,\n \t\t\t\t\t       size,\n \t\t\t\t\t       io_sq->desc_addr.virt_addr,\n \t\t\t\t\t       io_sq->desc_addr.phys_addr,\n \t\t\t\t\t       io_sq->desc_addr.mem_handle);\n+\t\t}\n \t} else {\n \t\tENA_MEM_ALLOC_NODE(ena_dev->dmadev,\n \t\t\t\t   size,\n \t\t\t\t   io_sq->desc_addr.virt_addr,\n \t\t\t\t   ctx->numa_node,\n \t\t\t\t   dev_node);\n-\t\tif (!io_sq->desc_addr.virt_addr)\n+\t\tif (!io_sq->desc_addr.virt_addr) {\n \t\t\tio_sq->desc_addr.virt_addr =\n \t\t\t\tENA_MEM_ALLOC(ena_dev->dmadev, size);\n+\t\t}\n \t}\n \n \tif (!io_sq->desc_addr.virt_addr) {\n@@ -385,8 +398,7 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,\n \tsize_t size;\n \tint prev_node = 0;\n \n-\tENA_TOUCH(ctx);\n-\tmemset(&io_cq->cdesc_addr, 0x0, sizeof(struct ena_com_io_desc_addr));\n+\tmemset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));\n \n \t/* Use the basic completion descriptor for Rx */\n \tio_cq->cdesc_entry_size_in_bytes =\n@@ -397,17 +409,19 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,\n \tsize = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;\n \n \tENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,\n-\t\t\t\t    size,\n-\t\t\t\t    io_cq->cdesc_addr.virt_addr,\n-\t\t\t\t    io_cq->cdesc_addr.phys_addr,\n-\t\t\t\t    ctx->numa_node,\n-\t\t\t\t    prev_node);\n-\tif (!io_cq->cdesc_addr.virt_addr)\n+\t\t\tsize,\n+\t\t\tio_cq->cdesc_addr.virt_addr,\n+\t\t\tio_cq->cdesc_addr.phys_addr,\n+\t\t\tio_cq->cdesc_addr.mem_handle,\n+\t\t\tctx->numa_node,\n+\t\t\tprev_node);\n+\tif (!io_cq->cdesc_addr.virt_addr) {\n \t\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,\n \t\t\t\t       size,\n \t\t\t\t       io_cq->cdesc_addr.virt_addr,\n \t\t\t\t       io_cq->cdesc_addr.phys_addr,\n \t\t\t\t       io_cq->cdesc_addr.mem_handle);\n+\t}\n \n \tif (!io_cq->cdesc_addr.virt_addr) {\n \t\tena_trc_err(\"memory allocation failed\");\n@@ -420,9 +434,8 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,\n \treturn 0;\n }\n \n-static void\n-ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,\n-\t\t\t\t       struct ena_admin_acq_entry *cqe)\n+static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,\n+\t\t\t\t\t\t   struct ena_admin_acq_entry *cqe)\n {\n \tstruct ena_comp_ctx *comp_ctx;\n \tu16 cmd_id;\n@@ -447,8 +460,7 @@ ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,\n \t\tENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);\n }\n \n-static void\n-ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)\n+static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)\n {\n \tstruct ena_admin_acq_entry *cqe = NULL;\n \tu16 comp_num = 0;\n@@ -499,7 +511,7 @@ static int ena_com_comp_status_to_errno(u8 comp_status)\n \tcase ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:\n \t\treturn ENA_COM_NO_MEM;\n \tcase ENA_ADMIN_UNSUPPORTED_OPCODE:\n-\t\treturn ENA_COM_PERMISSION;\n+\t\treturn ENA_COM_UNSUPPORTED;\n \tcase ENA_ADMIN_BAD_OPCODE:\n \tcase ENA_ADMIN_MALFORMED_REQUEST:\n \tcase ENA_ADMIN_ILLEGAL_PARAMETER:\n@@ -510,20 +522,24 @@ static int ena_com_comp_status_to_errno(u8 comp_status)\n \treturn 0;\n }\n \n-static int\n-ena_com_wait_and_process_admin_cq_polling(\n-\t\tstruct ena_comp_ctx *comp_ctx,\n-\t\tstruct ena_com_admin_queue *admin_queue)\n+static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,\n+\t\t\t\t\t\t     struct ena_com_admin_queue *admin_queue)\n {\n \tunsigned long flags = 0;\n-\tu64 start_time;\n+\tunsigned long timeout;\n \tint ret;\n \n-\tstart_time = ENA_GET_SYSTEM_USECS();\n+\ttimeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);\n+\n+\twhile (1) {\n+                ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);\n+                ena_com_handle_admin_completion(admin_queue);\n+                ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);\n+\n+                if (comp_ctx->status != ENA_CMD_SUBMITTED)\n+\t\t\tbreak;\n \n-\twhile (comp_ctx->status == ENA_CMD_SUBMITTED) {\n-\t\tif ((ENA_GET_SYSTEM_USECS() - start_time) >\n-\t\t    ADMIN_CMD_TIMEOUT_US) {\n+\t\tif (ENA_TIME_EXPIRE(timeout)) {\n \t\t\tena_trc_err(\"Wait for completion (polling) timeout\\n\");\n \t\t\t/* ENA didn't have any completion */\n \t\t\tENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);\n@@ -535,9 +551,7 @@ ena_com_wait_and_process_admin_cq_polling(\n \t\t\tgoto err;\n \t\t}\n \n-\t\tENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);\n-\t\tena_com_handle_admin_completion(admin_queue);\n-\t\tENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);\n+\t\tENA_MSLEEP(ENA_POLL_MS);\n \t}\n \n \tif (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {\n@@ -549,8 +563,8 @@ ena_com_wait_and_process_admin_cq_polling(\n \t\tgoto err;\n \t}\n \n-\tENA_ASSERT(comp_ctx->status == ENA_CMD_COMPLETED,\n-\t\t   \"Invalid comp status %d\\n\", comp_ctx->status);\n+\tENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,\n+\t\t \"Invalid comp status %d\\n\", comp_ctx->status);\n \n \tret = ena_com_comp_status_to_errno(comp_ctx->comp_status);\n err:\n@@ -558,16 +572,14 @@ ena_com_wait_and_process_admin_cq_polling(\n \treturn ret;\n }\n \n-static int\n-ena_com_wait_and_process_admin_cq_interrupts(\n-\t\tstruct ena_comp_ctx *comp_ctx,\n-\t\tstruct ena_com_admin_queue *admin_queue)\n+static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,\n+\t\t\t\t\t\t\tstruct ena_com_admin_queue *admin_queue)\n {\n \tunsigned long flags = 0;\n-\tint ret = 0;\n+\tint ret;\n \n \tENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,\n-\t\t\t    ADMIN_CMD_TIMEOUT_US);\n+\t\t\t    admin_queue->completion_timeout);\n \n \t/* In case the command wasn't completed find out the root cause.\n \t * There might be 2 kinds of errors\n@@ -607,16 +619,18 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)\n \tstruct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;\n \tvolatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =\n \t\tmmio_read->read_resp;\n-\tu32 mmio_read_reg, ret;\n+\tu32 mmio_read_reg, ret, i;\n \tunsigned long flags = 0;\n-\tint i;\n+\tu32 timeout = mmio_read->reg_read_to;\n \n \tENA_MIGHT_SLEEP();\n \n+\tif (timeout == 0)\n+\t\ttimeout = ENA_REG_READ_TIMEOUT;\n+\n \t/* If readless is disabled, perform regular read */\n \tif (!mmio_read->readless_supported)\n-\t\treturn ENA_REG_READ32((unsigned char *)ena_dev->reg_bar +\n-\t\t\t\t      offset);\n+\t\treturn ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);\n \n \tENA_SPINLOCK_LOCK(mmio_read->lock, flags);\n \tmmio_read->seq_num++;\n@@ -632,17 +646,16 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)\n \t */\n \twmb();\n \n-\tENA_REG_WRITE32(mmio_read_reg, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_MMIO_REG_READ_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);\n \n-\tfor (i = 0; i < ENA_REG_READ_TIMEOUT; i++) {\n+\tfor (i = 0; i < timeout; i++) {\n \t\tif (read_resp->req_id == mmio_read->seq_num)\n \t\t\tbreak;\n \n \t\tENA_UDELAY(1);\n \t}\n \n-\tif (unlikely(i == ENA_REG_READ_TIMEOUT)) {\n+\tif (unlikely(i == timeout)) {\n \t\tena_trc_err(\"reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\\n\",\n \t\t\t    mmio_read->seq_num,\n \t\t\t    offset,\n@@ -653,7 +666,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)\n \t}\n \n \tif (read_resp->reg_off != offset) {\n-\t\tena_trc_err(\"reading failed for wrong offset value\");\n+\t\tena_trc_err(\"Read failure: wrong offset provided\");\n \t\tret = ENA_MMIO_READ_TIMEOUT;\n \t} else {\n \t\tret = read_resp->reg_val;\n@@ -671,9 +684,8 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)\n  * It is expected that the IRQ called ena_com_handle_admin_completion\n  * to mark the completions.\n  */\n-static int\n-ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,\n-\t\t\t\t  struct ena_com_admin_queue *admin_queue)\n+static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,\n+\t\t\t\t\t     struct ena_com_admin_queue *admin_queue)\n {\n \tif (admin_queue->polling)\n \t\treturn ena_com_wait_and_process_admin_cq_polling(comp_ctx,\n@@ -692,7 +704,7 @@ static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,\n \tu8 direction;\n \tint ret;\n \n-\tmemset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));\n+\tmemset(&destroy_cmd, 0x0, sizeof(destroy_cmd));\n \n \tif (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)\n \t\tdirection = ENA_ADMIN_SQ_DIRECTION_TX;\n@@ -706,12 +718,11 @@ static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,\n \tdestroy_cmd.sq.sq_idx = io_sq->idx;\n \tdestroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;\n \n-\tret = ena_com_execute_admin_command(\n-\t\t\tadmin_queue,\n-\t\t\t(struct ena_admin_aq_entry *)&destroy_cmd,\n-\t\t\tsizeof(destroy_cmd),\n-\t\t\t(struct ena_admin_acq_entry *)&destroy_resp,\n-\t\t\tsizeof(destroy_resp));\n+\tret = ena_com_execute_admin_command(admin_queue,\n+\t\t\t\t\t    (struct ena_admin_aq_entry *)&destroy_cmd,\n+\t\t\t\t\t    sizeof(destroy_cmd),\n+\t\t\t\t\t    (struct ena_admin_acq_entry *)&destroy_resp,\n+\t\t\t\t\t    sizeof(destroy_resp));\n \n \tif (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))\n \t\tena_trc_err(\"failed to destroy io sq error: %d\\n\", ret);\n@@ -747,18 +758,20 @@ static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,\n \t\t\t\t\t      io_sq->desc_addr.phys_addr,\n \t\t\t\t\t      io_sq->desc_addr.mem_handle);\n \t\telse\n-\t\t\tENA_MEM_FREE(ena_dev->dmadev,\n-\t\t\t\t     io_sq->desc_addr.virt_addr);\n+\t\t\tENA_MEM_FREE(ena_dev->dmadev, io_sq->desc_addr.virt_addr);\n \n \t\tio_sq->desc_addr.virt_addr = NULL;\n \t}\n }\n \n-static int wait_for_reset_state(struct ena_com_dev *ena_dev,\n-\t\t\t\tu32 timeout, u16 exp_state)\n+static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,\n+\t\t\t\tu16 exp_state)\n {\n \tu32 val, i;\n \n+\t/* Convert timeout from resolution of 100ms to ENA_POLL_MS */\n+\ttimeout = (timeout * 100) / ENA_POLL_MS;\n+\n \tfor (i = 0; i < timeout; i++) {\n \t\tval = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);\n \n@@ -771,16 +784,14 @@ static int wait_for_reset_state(struct ena_com_dev *ena_dev,\n \t\t\texp_state)\n \t\t\treturn 0;\n \n-\t\t/* The resolution of the timeout is 100ms */\n-\t\tENA_MSLEEP(100);\n+\t\tENA_MSLEEP(ENA_POLL_MS);\n \t}\n \n \treturn ENA_COM_TIMER_EXPIRED;\n }\n \n-static bool\n-ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,\n-\t\t\t\t   enum ena_admin_aq_feature_id feature_id)\n+static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t       enum ena_admin_aq_feature_id feature_id)\n {\n \tu32 feature_mask = 1 << feature_id;\n \n@@ -802,14 +813,9 @@ static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,\n \tstruct ena_admin_get_feat_cmd get_cmd;\n \tint ret;\n \n-\tif (!ena_dev) {\n-\t\tena_trc_err(\"%s : ena_dev is NULL\\n\", __func__);\n-\t\treturn ENA_COM_NO_DEVICE;\n-\t}\n-\n \tif (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {\n-\t\tena_trc_info(\"Feature %d isn't supported\\n\", feature_id);\n-\t\treturn ENA_COM_PERMISSION;\n+\t\tena_trc_dbg(\"Feature %d isn't supported\\n\", feature_id);\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n \tmemset(&get_cmd, 0x0, sizeof(get_cmd));\n@@ -945,10 +951,10 @@ static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,\n \t\tsizeof(struct ena_admin_rss_ind_table_entry);\n \n \tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,\n-\t\t\t       tbl_size,\n-\t\t\t       rss->rss_ind_tbl,\n-\t\t\t       rss->rss_ind_tbl_dma_addr,\n-\t\t\t       rss->rss_ind_tbl_mem_handle);\n+\t\t\t     tbl_size,\n+\t\t\t     rss->rss_ind_tbl,\n+\t\t\t     rss->rss_ind_tbl_dma_addr,\n+\t\t\t     rss->rss_ind_tbl_mem_handle);\n \tif (unlikely(!rss->rss_ind_tbl))\n \t\tgoto mem_err1;\n \n@@ -1005,7 +1011,7 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,\n \tu8 direction;\n \tint ret;\n \n-\tmemset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_sq_cmd));\n+\tmemset(&create_cmd, 0x0, sizeof(create_cmd));\n \n \tcreate_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;\n \n@@ -1041,12 +1047,11 @@ static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,\n \t\t}\n \t}\n \n-\tret = ena_com_execute_admin_command(\n-\t\t\tadmin_queue,\n-\t\t\t(struct ena_admin_aq_entry *)&create_cmd,\n-\t\t\tsizeof(create_cmd),\n-\t\t\t(struct ena_admin_acq_entry *)&cmd_completion,\n-\t\t\tsizeof(cmd_completion));\n+\tret = ena_com_execute_admin_command(admin_queue,\n+\t\t\t\t\t    (struct ena_admin_aq_entry *)&create_cmd,\n+\t\t\t\t\t    sizeof(create_cmd),\n+\t\t\t\t\t    (struct ena_admin_acq_entry *)&cmd_completion,\n+\t\t\t\t\t    sizeof(cmd_completion));\n \tif (unlikely(ret)) {\n \t\tena_trc_err(\"Failed to create IO SQ. error: %d\\n\", ret);\n \t\treturn ret;\n@@ -1133,9 +1138,8 @@ static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)\n \treturn 0;\n }\n \n-static void\n-ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,\n-\t\t\t\t     u16 intr_delay_resolution)\n+static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t\t u16 intr_delay_resolution)\n {\n \tstruct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;\n \tunsigned int i;\n@@ -1165,13 +1169,18 @@ int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,\n \t\t\t\t  size_t comp_size)\n {\n \tstruct ena_comp_ctx *comp_ctx;\n-\tint ret = 0;\n+\tint ret;\n \n \tcomp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,\n \t\t\t\t\t    comp, comp_size);\n-\tif (unlikely(IS_ERR(comp_ctx))) {\n-\t\tena_trc_err(\"Failed to submit command [%ld]\\n\",\n-\t\t\t    PTR_ERR(comp_ctx));\n+\tif (IS_ERR(comp_ctx)) {\n+\t\tif (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))\n+\t\t\tena_trc_dbg(\"Failed to submit command [%ld]\\n\",\n+\t\t\t\t    PTR_ERR(comp_ctx));\n+\t\telse\n+\t\t\tena_trc_err(\"Failed to submit command [%ld]\\n\",\n+\t\t\t\t    PTR_ERR(comp_ctx));\n+\n \t\treturn PTR_ERR(comp_ctx);\n \t}\n \n@@ -1195,7 +1204,7 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev,\n \tstruct ena_admin_acq_create_cq_resp_desc cmd_completion;\n \tint ret;\n \n-\tmemset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_cq_cmd));\n+\tmemset(&create_cmd, 0x0, sizeof(create_cmd));\n \n \tcreate_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;\n \n@@ -1215,12 +1224,11 @@ int ena_com_create_io_cq(struct ena_com_dev *ena_dev,\n \t\treturn ret;\n \t}\n \n-\tret = ena_com_execute_admin_command(\n-\t\t\tadmin_queue,\n-\t\t\t(struct ena_admin_aq_entry *)&create_cmd,\n-\t\t\tsizeof(create_cmd),\n-\t\t\t(struct ena_admin_acq_entry *)&cmd_completion,\n-\t\t\tsizeof(cmd_completion));\n+\tret = ena_com_execute_admin_command(admin_queue,\n+\t\t\t\t\t    (struct ena_admin_aq_entry *)&create_cmd,\n+\t\t\t\t\t    sizeof(create_cmd),\n+\t\t\t\t\t    (struct ena_admin_acq_entry *)&cmd_completion,\n+\t\t\t\t\t    sizeof(cmd_completion));\n \tif (unlikely(ret)) {\n \t\tena_trc_err(\"Failed to create IO CQ. error: %d\\n\", ret);\n \t\treturn ret;\n@@ -1290,7 +1298,7 @@ void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)\n \tENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);\n \twhile (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {\n \t\tENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);\n-\t\tENA_MSLEEP(20);\n+\t\tENA_MSLEEP(ENA_POLL_MS);\n \t\tENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);\n \t}\n \tENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);\n@@ -1304,17 +1312,16 @@ int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,\n \tstruct ena_admin_acq_destroy_cq_resp_desc destroy_resp;\n \tint ret;\n \n-\tmemset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd));\n+\tmemset(&destroy_cmd, 0x0, sizeof(destroy_cmd));\n \n \tdestroy_cmd.cq_idx = io_cq->idx;\n \tdestroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;\n \n-\tret = ena_com_execute_admin_command(\n-\t\t\tadmin_queue,\n-\t\t\t(struct ena_admin_aq_entry *)&destroy_cmd,\n-\t\t\tsizeof(destroy_cmd),\n-\t\t\t(struct ena_admin_acq_entry *)&destroy_resp,\n-\t\t\tsizeof(destroy_resp));\n+\tret = ena_com_execute_admin_command(admin_queue,\n+\t\t\t\t\t    (struct ena_admin_aq_entry *)&destroy_cmd,\n+\t\t\t\t\t    sizeof(destroy_cmd),\n+\t\t\t\t\t    (struct ena_admin_acq_entry *)&destroy_resp,\n+\t\t\t\t\t    sizeof(destroy_resp));\n \n \tif (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))\n \t\tena_trc_err(\"Failed to destroy IO CQ. error: %d\\n\", ret);\n@@ -1341,13 +1348,12 @@ void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)\n {\n \tu16 depth = ena_dev->aenq.q_depth;\n \n-\tENA_ASSERT(ena_dev->aenq.head == depth, \"Invalid AENQ state\\n\");\n+\tENA_WARN(ena_dev->aenq.head != depth, \"Invalid AENQ state\\n\");\n \n \t/* Init head_db to mark that all entries in the queue\n \t * are initially available\n \t */\n-\tENA_REG_WRITE32(depth, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_AENQ_HEAD_DB_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);\n }\n \n int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)\n@@ -1356,12 +1362,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)\n \tstruct ena_admin_set_feat_cmd cmd;\n \tstruct ena_admin_set_feat_resp resp;\n \tstruct ena_admin_get_feat_resp get_resp;\n-\tint ret = 0;\n-\n-\tif (unlikely(!ena_dev)) {\n-\t\tena_trc_err(\"%s : ena_dev is NULL\\n\", __func__);\n-\t\treturn ENA_COM_NO_DEVICE;\n-\t}\n+\tint ret;\n \n \tret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);\n \tif (ret) {\n@@ -1373,7 +1374,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)\n \t\tena_trc_warn(\"Trying to set unsupported aenq events. supported flag: %x asked flag: %x\\n\",\n \t\t\t     get_resp.u.aenq.supported_groups,\n \t\t\t     groups_flag);\n-\t\treturn ENA_COM_PERMISSION;\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n \tmemset(&cmd, 0x0, sizeof(cmd));\n@@ -1476,41 +1477,42 @@ int ena_com_validate_version(struct ena_com_dev *ena_dev)\n void ena_com_admin_destroy(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;\n+\tstruct ena_com_admin_cq *cq = &admin_queue->cq;\n+\tstruct ena_com_admin_sq *sq = &admin_queue->sq;\n+\tstruct ena_com_aenq *aenq = &ena_dev->aenq;\n+\tu16 size;\n \n-\tif (!admin_queue)\n-\t\treturn;\n-\n+\tENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);\n \tif (admin_queue->comp_ctx)\n \t\tENA_MEM_FREE(ena_dev->dmadev, admin_queue->comp_ctx);\n \tadmin_queue->comp_ctx = NULL;\n-\n-\tif (admin_queue->sq.entries)\n-\t\tENA_MEM_FREE_COHERENT(ena_dev->dmadev,\n-\t\t\t\t      ADMIN_SQ_SIZE(admin_queue->q_depth),\n-\t\t\t\t      admin_queue->sq.entries,\n-\t\t\t\t      admin_queue->sq.dma_addr,\n-\t\t\t\t      admin_queue->sq.mem_handle);\n-\tadmin_queue->sq.entries = NULL;\n-\n-\tif (admin_queue->cq.entries)\n-\t\tENA_MEM_FREE_COHERENT(ena_dev->dmadev,\n-\t\t\t\t      ADMIN_CQ_SIZE(admin_queue->q_depth),\n-\t\t\t\t      admin_queue->cq.entries,\n-\t\t\t\t      admin_queue->cq.dma_addr,\n-\t\t\t\t      admin_queue->cq.mem_handle);\n-\tadmin_queue->cq.entries = NULL;\n-\n+\tsize = ADMIN_SQ_SIZE(admin_queue->q_depth);\n+\tif (sq->entries)\n+\t\tENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,\n+\t\t\t\t      sq->dma_addr, sq->mem_handle);\n+\tsq->entries = NULL;\n+\n+\tsize = ADMIN_CQ_SIZE(admin_queue->q_depth);\n+\tif (cq->entries)\n+\t\tENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,\n+\t\t\t\t      cq->dma_addr, cq->mem_handle);\n+\tcq->entries = NULL;\n+\n+\tsize = ADMIN_AENQ_SIZE(aenq->q_depth);\n \tif (ena_dev->aenq.entries)\n-\t\tENA_MEM_FREE_COHERENT(ena_dev->dmadev,\n-\t\t\t\t      ADMIN_AENQ_SIZE(ena_dev->aenq.q_depth),\n-\t\t\t\t      ena_dev->aenq.entries,\n-\t\t\t\t      ena_dev->aenq.dma_addr,\n-\t\t\t\t      ena_dev->aenq.mem_handle);\n-\tena_dev->aenq.entries = NULL;\n+\t\tENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,\n+\t\t\t\t      aenq->dma_addr, aenq->mem_handle);\n+\taenq->entries = NULL;\n }\n \n void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)\n {\n+\tu32 mask_value = 0;\n+\n+\tif (polling)\n+\t\tmask_value = ENA_REGS_ADMIN_INTR_MASK;\n+\n+\tENA_REG_WRITE32(ena_dev->bus, mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);\n \tena_dev->admin_queue.polling = polling;\n }\n \n@@ -1536,8 +1538,7 @@ int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)\n \treturn 0;\n }\n \n-void\n-ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)\n+void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)\n {\n \tstruct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;\n \n@@ -1548,10 +1549,8 @@ void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;\n \n-\tENA_REG_WRITE32(0x0, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_MMIO_RESP_LO_OFF);\n-\tENA_REG_WRITE32(0x0, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_MMIO_RESP_HI_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);\n \n \tENA_MEM_FREE_COHERENT(ena_dev->dmadev,\n \t\t\t      sizeof(*mmio_read->read_resp),\n@@ -1570,10 +1569,8 @@ void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)\n \taddr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);\n \taddr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);\n \n-\tENA_REG_WRITE32(addr_low, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_MMIO_RESP_LO_OFF);\n-\tENA_REG_WRITE32(addr_high, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_MMIO_RESP_HI_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);\n }\n \n int ena_com_admin_init(struct ena_com_dev *ena_dev,\n@@ -1619,24 +1616,20 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,\n \tif (ret)\n \t\tgoto error;\n \n-\tadmin_queue->sq.db_addr = (u32 __iomem *)\n-\t\t((unsigned char *)ena_dev->reg_bar + ENA_REGS_AQ_DB_OFF);\n+\tadmin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +\n+\t\tENA_REGS_AQ_DB_OFF);\n \n \taddr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);\n \taddr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);\n \n-\tENA_REG_WRITE32(addr_low, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_AQ_BASE_LO_OFF);\n-\tENA_REG_WRITE32(addr_high, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_AQ_BASE_HI_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);\n \n \taddr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);\n \taddr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);\n \n-\tENA_REG_WRITE32(addr_low, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_ACQ_BASE_LO_OFF);\n-\tENA_REG_WRITE32(addr_high, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_ACQ_BASE_HI_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);\n \n \taq_caps = 0;\n \taq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;\n@@ -1650,10 +1643,8 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,\n \t\tENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &\n \t\tENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;\n \n-\tENA_REG_WRITE32(aq_caps, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_AQ_CAPS_OFF);\n-\tENA_REG_WRITE32(acq_caps, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_ACQ_CAPS_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);\n \tret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);\n \tif (ret)\n \t\tgoto error;\n@@ -1672,7 +1663,7 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev,\n {\n \tstruct ena_com_io_sq *io_sq;\n \tstruct ena_com_io_cq *io_cq;\n-\tint ret = 0;\n+\tint ret;\n \n \tif (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {\n \t\tena_trc_err(\"Qid (%d) is bigger than max num of queues (%d)\\n\",\n@@ -1683,8 +1674,8 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev,\n \tio_sq = &ena_dev->io_sq_queues[ctx->qid];\n \tio_cq = &ena_dev->io_cq_queues[ctx->qid];\n \n-\tmemset(io_sq, 0x0, sizeof(struct ena_com_io_sq));\n-\tmemset(io_cq, 0x0, sizeof(struct ena_com_io_cq));\n+\tmemset(io_sq, 0x0, sizeof(*io_sq));\n+\tmemset(io_cq, 0x0, sizeof(*io_cq));\n \n \t/* Init CQ */\n \tio_cq->q_depth = ctx->queue_size;\n@@ -1794,6 +1785,19 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n \tmemcpy(&get_feat_ctx->offload, &get_resp.u.offload,\n \t       sizeof(get_resp.u.offload));\n \n+\t/* Driver hints isn't mandatory admin command. So in case the\n+\t * command isn't supported set driver hints to 0\n+\t */\n+\trc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS);\n+\n+\tif (!rc)\n+\t\tmemcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,\n+\t\t       sizeof(get_resp.u.hw_hints));\n+\telse if (rc == ENA_COM_UNSUPPORTED)\n+\t\tmemset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));\n+\telse\n+\t\treturn rc;\n+\n \treturn 0;\n }\n \n@@ -1826,6 +1830,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)\n \tstruct ena_admin_aenq_common_desc *aenq_common;\n \tstruct ena_com_aenq *aenq  = &dev->aenq;\n \tena_aenq_handler handler_cb;\n+\tunsigned long long timestamp;\n \tu16 masked_head, processed = 0;\n \tu8 phase;\n \n@@ -1837,11 +1842,13 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)\n \t/* Go over all the events */\n \twhile ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) ==\n \t\tphase) {\n+\t\ttimestamp = (unsigned long long)aenq_common->timestamp_low |\n+\t\t\t((unsigned long long)aenq_common->timestamp_high << 32);\n+\t\tENA_TOUCH(timestamp); /* In case debug is disabled */\n \t\tena_trc_dbg(\"AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\\n\",\n \t\t\t    aenq_common->group,\n \t\t\t    aenq_common->syndrom,\n-\t\t\t    (unsigned long long)aenq_common->timestamp_low +\n-\t\t\t    ((u64)aenq_common->timestamp_high << 32));\n+\t\t\t    timestamp);\n \n \t\t/* Handle specific event*/\n \t\thandler_cb = ena_com_get_specific_aenq_cb(dev,\n@@ -1869,11 +1876,11 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)\n \n \t/* write the aenq doorbell after all AENQ descriptors were read */\n \tmb();\n-\tENA_REG_WRITE32((u32)aenq->head, (unsigned char *)dev->reg_bar\n-\t\t\t+ ENA_REGS_AENQ_HEAD_DB_OFF);\n+\tENA_REG_WRITE32(dev->bus, (u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);\n }\n \n-int ena_com_dev_reset(struct ena_com_dev *ena_dev)\n+int ena_com_dev_reset(struct ena_com_dev *ena_dev,\n+\t\t      enum ena_regs_reset_reason_types reset_reason)\n {\n \tu32 stat, timeout, cap, reset_val;\n \tint rc;\n@@ -1901,8 +1908,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev)\n \n \t/* start reset */\n \treset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;\n-\tENA_REG_WRITE32(reset_val, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_DEV_CTL_OFF);\n+\treset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &\n+\t\t\tENA_REGS_DEV_CTL_RESET_REASON_MASK;\n+\tENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);\n \n \t/* Write again the MMIO read request address */\n \tena_com_mmio_reg_read_request_write_dev_addr(ena_dev);\n@@ -1915,29 +1923,32 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev)\n \t}\n \n \t/* reset done */\n-\tENA_REG_WRITE32(0, (unsigned char *)ena_dev->reg_bar\n-\t\t\t+ ENA_REGS_DEV_CTL_OFF);\n+\tENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);\n \trc = wait_for_reset_state(ena_dev, timeout, 0);\n \tif (rc != 0) {\n \t\tena_trc_err(\"Reset indication didn't turn off\\n\");\n \t\treturn rc;\n \t}\n \n+\ttimeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>\n+\t\tENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;\n+\tif (timeout)\n+\t\t/* the resolution of timeout reg is 100ms */\n+\t\tena_dev->admin_queue.completion_timeout = timeout * 100000;\n+\telse\n+\t\tena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;\n+\n \treturn 0;\n }\n \n static int ena_get_dev_stats(struct ena_com_dev *ena_dev,\n-\t\t\t     struct ena_admin_aq_get_stats_cmd *get_cmd,\n-\t\t\t     struct ena_admin_acq_get_stats_resp *get_resp,\n+\t\t\t     struct ena_com_stats_ctx *ctx,\n \t\t\t     enum ena_admin_get_stats_type type)\n {\n+\tstruct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;\n+\tstruct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;\n \tstruct ena_com_admin_queue *admin_queue;\n-\tint ret = 0;\n-\n-\tif (!ena_dev) {\n-\t\tena_trc_err(\"%s : ena_dev is NULL\\n\", __func__);\n-\t\treturn ENA_COM_NO_DEVICE;\n-\t}\n+\tint ret;\n \n \tadmin_queue = &ena_dev->admin_queue;\n \n@@ -1945,12 +1956,11 @@ static int ena_get_dev_stats(struct ena_com_dev *ena_dev,\n \tget_cmd->aq_common_descriptor.flags = 0;\n \tget_cmd->type = type;\n \n-\tret =  ena_com_execute_admin_command(\n-\t\t\tadmin_queue,\n-\t\t\t(struct ena_admin_aq_entry *)get_cmd,\n-\t\t\tsizeof(*get_cmd),\n-\t\t\t(struct ena_admin_acq_entry *)get_resp,\n-\t\t\tsizeof(*get_resp));\n+\tret =  ena_com_execute_admin_command(admin_queue,\n+\t\t\t\t\t     (struct ena_admin_aq_entry *)get_cmd,\n+\t\t\t\t\t     sizeof(*get_cmd),\n+\t\t\t\t\t     (struct ena_admin_acq_entry *)get_resp,\n+\t\t\t\t\t     sizeof(*get_resp));\n \n \tif (unlikely(ret))\n \t\tena_trc_err(\"Failed to get stats. error: %d\\n\", ret);\n@@ -1961,78 +1971,28 @@ static int ena_get_dev_stats(struct ena_com_dev *ena_dev,\n int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,\n \t\t\t\tstruct ena_admin_basic_stats *stats)\n {\n-\tint ret = 0;\n-\tstruct ena_admin_aq_get_stats_cmd get_cmd;\n-\tstruct ena_admin_acq_get_stats_resp get_resp;\n+\tstruct ena_com_stats_ctx ctx;\n+\tint ret;\n \n-\tmemset(&get_cmd, 0x0, sizeof(get_cmd));\n-\tret = ena_get_dev_stats(ena_dev, &get_cmd, &get_resp,\n-\t\t\t\tENA_ADMIN_GET_STATS_TYPE_BASIC);\n+\tmemset(&ctx, 0x0, sizeof(ctx));\n+\tret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);\n \tif (likely(ret == 0))\n-\t\tmemcpy(stats, &get_resp.basic_stats,\n-\t\t       sizeof(get_resp.basic_stats));\n+\t\tmemcpy(stats, &ctx.get_resp.basic_stats,\n+\t\t       sizeof(ctx.get_resp.basic_stats));\n \n \treturn ret;\n }\n \n-int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,\n-\t\t\t\t   u32 len)\n-{\n-\tint ret = 0;\n-\tstruct ena_admin_aq_get_stats_cmd get_cmd;\n-\tstruct ena_admin_acq_get_stats_resp get_resp;\n-\tena_mem_handle_t mem_handle = 0;\n-\tvoid *virt_addr;\n-\tdma_addr_t phys_addr;\n-\n-\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, len,\n-\t\t\t       virt_addr, phys_addr, mem_handle);\n-\tif (!virt_addr) {\n-\t\tret = ENA_COM_NO_MEM;\n-\t\tgoto done;\n-\t}\n-\tmemset(&get_cmd, 0x0, sizeof(get_cmd));\n-\tret = ena_com_mem_addr_set(ena_dev,\n-\t\t\t\t   &get_cmd.u.control_buffer.address,\n-\t\t\t\t   phys_addr);\n-\tif (unlikely(ret)) {\n-\t\tena_trc_err(\"memory address set failed\\n\");\n-\t\treturn ret;\n-\t}\n-\tget_cmd.u.control_buffer.length = len;\n-\n-\tget_cmd.device_id = ena_dev->stats_func;\n-\tget_cmd.queue_idx = ena_dev->stats_queue;\n-\n-\tret = ena_get_dev_stats(ena_dev, &get_cmd, &get_resp,\n-\t\t\t\tENA_ADMIN_GET_STATS_TYPE_EXTENDED);\n-\tif (ret < 0)\n-\t\tgoto free_ext_stats_mem;\n-\n-\tret = snprintf(buff, len, \"%s\", (char *)virt_addr);\n-\n-free_ext_stats_mem:\n-\tENA_MEM_FREE_COHERENT(ena_dev->dmadev, len, virt_addr, phys_addr,\n-\t\t\t      mem_handle);\n-done:\n-\treturn ret;\n-}\n-\n int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)\n {\n \tstruct ena_com_admin_queue *admin_queue;\n \tstruct ena_admin_set_feat_cmd cmd;\n \tstruct ena_admin_set_feat_resp resp;\n-\tint ret = 0;\n-\n-\tif (unlikely(!ena_dev)) {\n-\t\tena_trc_err(\"%s : ena_dev is NULL\\n\", __func__);\n-\t\treturn ENA_COM_NO_DEVICE;\n-\t}\n+\tint ret;\n \n \tif (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {\n-\t\tena_trc_info(\"Feature %d isn't supported\\n\", ENA_ADMIN_MTU);\n-\t\treturn ENA_COM_PERMISSION;\n+\t\tena_trc_dbg(\"Feature %d isn't supported\\n\", ENA_ADMIN_MTU);\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n \tmemset(&cmd, 0x0, sizeof(cmd));\n@@ -2049,11 +2009,10 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)\n \t\t\t\t\t    (struct ena_admin_acq_entry *)&resp,\n \t\t\t\t\t    sizeof(resp));\n \n-\tif (unlikely(ret)) {\n+\tif (unlikely(ret))\n \t\tena_trc_err(\"Failed to set mtu %d. error: %d\\n\", mtu, ret);\n-\t\treturn ENA_COM_INVAL;\n-\t}\n-\treturn 0;\n+\n+\treturn ret;\n }\n \n int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,\n@@ -2066,7 +2025,7 @@ int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,\n \t\t\t\t  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);\n \tif (unlikely(ret)) {\n \t\tena_trc_err(\"Failed to get offload capabilities %d\\n\", ret);\n-\t\treturn ENA_COM_INVAL;\n+\t\treturn ret;\n \t}\n \n \tmemcpy(offload, &resp.u.offload, sizeof(resp.u.offload));\n@@ -2085,9 +2044,9 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev)\n \n \tif (!ena_com_check_supported_feature_id(ena_dev,\n \t\t\t\t\t\tENA_ADMIN_RSS_HASH_FUNCTION)) {\n-\t\tena_trc_info(\"Feature %d isn't supported\\n\",\n-\t\t\t     ENA_ADMIN_RSS_HASH_FUNCTION);\n-\t\treturn ENA_COM_PERMISSION;\n+\t\tena_trc_dbg(\"Feature %d isn't supported\\n\",\n+\t\t\t    ENA_ADMIN_RSS_HASH_FUNCTION);\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n \t/* Validate hash function is supported */\n@@ -2099,7 +2058,7 @@ int ena_com_set_hash_function(struct ena_com_dev *ena_dev)\n \tif (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) {\n \t\tena_trc_err(\"Func hash %d isn't supported by device, abort\\n\",\n \t\t\t    rss->hash_func);\n-\t\treturn ENA_COM_PERMISSION;\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n \tmemset(&cmd, 0x0, sizeof(cmd));\n@@ -2158,7 +2117,7 @@ int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,\n \n \tif (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {\n \t\tena_trc_err(\"Flow hash function %d isn't supported\\n\", func);\n-\t\treturn ENA_COM_PERMISSION;\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n \tswitch (func) {\n@@ -2207,7 +2166,7 @@ int ena_com_get_hash_function(struct ena_com_dev *ena_dev,\n \tif (unlikely(rc))\n \t\treturn rc;\n \n-\trss->hash_func = (enum ena_admin_hash_functions)get_resp.u.flow_hash_func.selected_func;\n+\trss->hash_func = get_resp.u.flow_hash_func.selected_func;\n \tif (func)\n \t\t*func = rss->hash_func;\n \n@@ -2242,17 +2201,20 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;\n \tstruct ena_rss *rss = &ena_dev->rss;\n+\tstruct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;\n \tstruct ena_admin_set_feat_cmd cmd;\n \tstruct ena_admin_set_feat_resp resp;\n \tint ret;\n \n \tif (!ena_com_check_supported_feature_id(ena_dev,\n \t\t\t\t\t\tENA_ADMIN_RSS_HASH_INPUT)) {\n-\t\tena_trc_info(\"Feature %d isn't supported\\n\",\n-\t\t\t     ENA_ADMIN_RSS_HASH_INPUT);\n-\t\treturn ENA_COM_PERMISSION;\n+\t\tena_trc_dbg(\"Feature %d isn't supported\\n\",\n+\t\t\t    ENA_ADMIN_RSS_HASH_INPUT);\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n+\tmemset(&cmd, 0x0, sizeof(cmd));\n+\n \tcmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;\n \tcmd.aq_common_descriptor.flags =\n \t\tENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;\n@@ -2268,20 +2230,17 @@ int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)\n \t\tena_trc_err(\"memory address set failed\\n\");\n \t\treturn ret;\n \t}\n-\tcmd.control_buffer.length =\n-\t\tsizeof(struct ena_admin_feature_rss_hash_control);\n+\tcmd.control_buffer.length = sizeof(*hash_ctrl);\n \n \tret = ena_com_execute_admin_command(admin_queue,\n \t\t\t\t\t    (struct ena_admin_aq_entry *)&cmd,\n \t\t\t\t\t    sizeof(cmd),\n \t\t\t\t\t    (struct ena_admin_acq_entry *)&resp,\n \t\t\t\t\t    sizeof(resp));\n-\tif (unlikely(ret)) {\n+\tif (unlikely(ret))\n \t\tena_trc_err(\"Failed to set hash input. error: %d\\n\", ret);\n-\t\treturn ENA_COM_INVAL;\n-\t}\n \n-\treturn 0;\n+\treturn ret;\n }\n \n int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)\n@@ -2293,7 +2252,7 @@ int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)\n \tint rc, i;\n \n \t/* Get the supported hash input */\n-\trc = ena_com_get_hash_ctrl(ena_dev, (enum ena_admin_flow_hash_proto)0, NULL);\n+\trc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);\n \tif (unlikely(rc))\n \t\treturn rc;\n \n@@ -2322,7 +2281,7 @@ int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)\n \thash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =\n \t\tENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;\n \n-\thash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =\n+\thash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =\n \t\tENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;\n \n \tfor (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {\n@@ -2332,7 +2291,7 @@ int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)\n \t\t\tena_trc_err(\"hash control doesn't support all the desire configuration. proto %x supported %x selected %x\\n\",\n \t\t\t\t    i, hash_ctrl->supported_fields[i].fields,\n \t\t\t\t    hash_ctrl->selected_fields[i].fields);\n-\t\t\treturn ENA_COM_PERMISSION;\n+\t\t\treturn ENA_COM_UNSUPPORTED;\n \t\t}\n \t}\n \n@@ -2340,7 +2299,7 @@ int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)\n \n \t/* In case of failure, restore the old hash ctrl */\n \tif (unlikely(rc))\n-\t\tena_com_get_hash_ctrl(ena_dev, (enum ena_admin_flow_hash_proto)0, NULL);\n+\t\tena_com_get_hash_ctrl(ena_dev, 0, NULL);\n \n \treturn rc;\n }\n@@ -2377,7 +2336,7 @@ int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,\n \n \t/* In case of failure, restore the old hash ctrl */\n \tif (unlikely(rc))\n-\t\tena_com_get_hash_ctrl(ena_dev, (enum ena_admin_flow_hash_proto)0, NULL);\n+\t\tena_com_get_hash_ctrl(ena_dev, 0, NULL);\n \n \treturn 0;\n }\n@@ -2404,14 +2363,13 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)\n \tstruct ena_rss *rss = &ena_dev->rss;\n \tstruct ena_admin_set_feat_cmd cmd;\n \tstruct ena_admin_set_feat_resp resp;\n-\tint ret = 0;\n+\tint ret;\n \n-\tif (!ena_com_check_supported_feature_id(\n-\t\t\t\tena_dev,\n-\t\t\t\tENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {\n-\t\tena_trc_info(\"Feature %d isn't supported\\n\",\n-\t\t\t     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);\n-\t\treturn ENA_COM_PERMISSION;\n+\tif (!ena_com_check_supported_feature_id(ena_dev,\n+\t\t\t\t\t\tENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {\n+\t\tena_trc_dbg(\"Feature %d isn't supported\\n\",\n+\t\t\t    ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);\n+\t\treturn ENA_COM_UNSUPPORTED;\n \t}\n \n \tret = ena_com_ind_tbl_convert_to_device(ena_dev);\n@@ -2446,12 +2404,10 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)\n \t\t\t\t\t    (struct ena_admin_acq_entry *)&resp,\n \t\t\t\t\t    sizeof(resp));\n \n-\tif (unlikely(ret)) {\n+\tif (unlikely(ret))\n \t\tena_trc_err(\"Failed to set indirect table. error: %d\\n\", ret);\n-\t\treturn ENA_COM_INVAL;\n-\t}\n \n-\treturn 0;\n+\treturn ret;\n }\n \n int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)\n@@ -2538,17 +2494,18 @@ int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)\n }\n \n int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,\n-\t\t\t\tu32 debug_area_size) {\n+\t\t\t\tu32 debug_area_size)\n+{\n \tstruct ena_host_attribute *host_attr = &ena_dev->host_attr;\n \n-\t\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,\n-\t\t\t\t       debug_area_size,\n-\t\t\t\t       host_attr->debug_area_virt_addr,\n-\t\t\t\t       host_attr->debug_area_dma_addr,\n-\t\t\t\t       host_attr->debug_area_dma_handle);\n-\t\tif (unlikely(!host_attr->debug_area_virt_addr)) {\n-\t\t\thost_attr->debug_area_size = 0;\n-\t\t\treturn ENA_COM_NO_MEM;\n+\tENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,\n+\t\t\t       debug_area_size,\n+\t\t\t       host_attr->debug_area_virt_addr,\n+\t\t\t       host_attr->debug_area_dma_addr,\n+\t\t\t       host_attr->debug_area_dma_handle);\n+\tif (unlikely(!host_attr->debug_area_virt_addr)) {\n+\t\thost_attr->debug_area_size = 0;\n+\t\treturn ENA_COM_NO_MEM;\n \t}\n \n \thost_attr->debug_area_size = debug_area_size;\n@@ -2590,6 +2547,7 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)\n \tstruct ena_com_admin_queue *admin_queue;\n \tstruct ena_admin_set_feat_cmd cmd;\n \tstruct ena_admin_set_feat_resp resp;\n+\n \tint ret;\n \n \t/* Host attribute config is called before ena_com_get_dev_attr_feat\n@@ -2635,14 +2593,12 @@ int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)\n /* Interrupt moderation */\n bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)\n {\n-\treturn ena_com_check_supported_feature_id(\n-\t\t\tena_dev,\n-\t\t\tENA_ADMIN_INTERRUPT_MODERATION);\n+\treturn ena_com_check_supported_feature_id(ena_dev,\n+\t\t\t\t\t\t  ENA_ADMIN_INTERRUPT_MODERATION);\n }\n \n-int\n-ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,\n-\t\t\t\t\t\t  u32 tx_coalesce_usecs)\n+int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t\t      u32 tx_coalesce_usecs)\n {\n \tif (!ena_dev->intr_delay_resolution) {\n \t\tena_trc_err(\"Illegal interrupt delay granularity value\\n\");\n@@ -2655,9 +2611,8 @@ ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,\n \treturn 0;\n }\n \n-int\n-ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,\n-\t\t\t\t\t\t  u32 rx_coalesce_usecs)\n+int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t\t      u32 rx_coalesce_usecs)\n {\n \tif (!ena_dev->intr_delay_resolution) {\n \t\tena_trc_err(\"Illegal interrupt delay granularity value\\n\");\n@@ -2690,9 +2645,9 @@ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)\n \t\t\t\t ENA_ADMIN_INTERRUPT_MODERATION);\n \n \tif (rc) {\n-\t\tif (rc == ENA_COM_PERMISSION) {\n-\t\t\tena_trc_info(\"Feature %d isn't supported\\n\",\n-\t\t\t\t     ENA_ADMIN_INTERRUPT_MODERATION);\n+\t\tif (rc == ENA_COM_UNSUPPORTED) {\n+\t\t\tena_trc_dbg(\"Feature %d isn't supported\\n\",\n+\t\t\t\t    ENA_ADMIN_INTERRUPT_MODERATION);\n \t\t\trc = 0;\n \t\t} else {\n \t\t\tena_trc_err(\"Failed to get interrupt moderation admin cmd. rc: %d\\n\",\n@@ -2719,8 +2674,7 @@ int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)\n \treturn rc;\n }\n \n-void\n-ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)\n+void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;\n \n@@ -2763,14 +2717,12 @@ ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)\n \t\tENA_INTR_HIGHEST_BYTES;\n }\n \n-unsigned int\n-ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)\n+unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)\n {\n \treturn ena_dev->intr_moder_tx_interval;\n }\n \n-unsigned int\n-ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)\n+unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)\n {\n \tstruct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;\n \n@@ -2794,7 +2746,10 @@ void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,\n \t\tintr_moder_tbl[level].intr_moder_interval /=\n \t\t\tena_dev->intr_delay_resolution;\n \tintr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;\n-\tintr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;\n+\n+\t/* use hardcoded value until ethtool supports bytecount parameter */\n+\tif (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)\n+\t\tintr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;\n }\n \n void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,\ndiff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h\nindex e53459262..f58cd86a8 100644\n--- a/drivers/net/ena/base/ena_com.h\n+++ b/drivers/net/ena/base/ena_com.h\n@@ -35,15 +35,7 @@\n #define ENA_COM\n \n #include \"ena_plat.h\"\n-#include \"ena_common_defs.h\"\n-#include \"ena_admin_defs.h\"\n-#include \"ena_eth_io_defs.h\"\n-#include \"ena_regs_defs.h\"\n-#if defined(__linux__) && !defined(__KERNEL__)\n-#include <rte_lcore.h>\n-#include <rte_spinlock.h>\n-#define __iomem\n-#endif\n+#include \"ena_includes.h\"\n \n #define ENA_MAX_NUM_IO_QUEUES\t\t128U\n /* We need to queues for each IO (on for Tx and one for Rx) */\n@@ -89,6 +81,11 @@\n #define ENA_INTR_DELAY_OLD_VALUE_WEIGHT\t\t\t6\n #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT\t\t\t4\n \n+#define ENA_INTR_MODER_LEVEL_STRIDE\t\t\t1\n+#define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED\t\t0xFFFFFF\n+\n+#define ENA_HW_HINTS_NO_TIMEOUT\t\t\t\t0xFFFF\n+\n enum ena_intr_moder_level {\n \tENA_INTR_MODER_LOWEST = 0,\n \tENA_INTR_MODER_LOW,\n@@ -120,8 +117,8 @@ struct ena_com_rx_buf_info {\n };\n \n struct ena_com_io_desc_addr {\n-\tu8  __iomem *pbuf_dev_addr; /* LLQ address */\n-\tu8  *virt_addr;\n+\tu8 __iomem *pbuf_dev_addr; /* LLQ address */\n+\tu8 *virt_addr;\n \tdma_addr_t phys_addr;\n \tena_mem_handle_t mem_handle;\n };\n@@ -130,13 +127,12 @@ struct ena_com_tx_meta {\n \tu16 mss;\n \tu16 l3_hdr_len;\n \tu16 l3_hdr_offset;\n-\tu16 l3_outer_hdr_len; /* In words */\n-\tu16 l3_outer_hdr_offset;\n \tu16 l4_hdr_len; /* In words */\n };\n \n struct ena_com_io_cq {\n \tstruct ena_com_io_desc_addr cdesc_addr;\n+\tvoid *bus;\n \n \t/* Interrupt unmask register */\n \tu32 __iomem *unmask_reg;\n@@ -174,6 +170,7 @@ struct ena_com_io_cq {\n \n struct ena_com_io_sq {\n \tstruct ena_com_io_desc_addr desc_addr;\n+\tvoid *bus;\n \n \tu32 __iomem *db_addr;\n \tu8 __iomem *header_addr;\n@@ -228,8 +225,11 @@ struct ena_com_stats_admin {\n \n struct ena_com_admin_queue {\n \tvoid *q_dmadev;\n+\tvoid *bus;\n \tena_spinlock_t q_lock; /* spinlock for the admin queue */\n+\n \tstruct ena_comp_ctx *comp_ctx;\n+\tu32 completion_timeout;\n \tu16 q_depth;\n \tstruct ena_com_admin_cq cq;\n \tstruct ena_com_admin_sq sq;\n@@ -266,6 +266,7 @@ struct ena_com_mmio_read {\n \tstruct ena_admin_ena_mmio_req_read_less_resp *read_resp;\n \tdma_addr_t read_resp_dma_addr;\n \tena_mem_handle_t read_resp_mem_handle;\n+\tu32 reg_read_to; /* in us */\n \tu16 seq_num;\n \tbool readless_supported;\n \t/* spin lock to ensure a single outstanding read */\n@@ -316,6 +317,7 @@ struct ena_com_dev {\n \tu8 __iomem *reg_bar;\n \tvoid __iomem *mem_bar;\n \tvoid *dmadev;\n+\tvoid *bus;\n \n \tenum ena_admin_placement_policy_type tx_mem_queue_type;\n \tu32 tx_max_header_size;\n@@ -340,6 +342,7 @@ struct ena_com_dev_get_features_ctx {\n \tstruct ena_admin_device_attr_feature_desc dev_attr;\n \tstruct ena_admin_feature_aenq_desc aenq;\n \tstruct ena_admin_feature_offload_desc offload;\n+\tstruct ena_admin_ena_hw_hints hw_hints;\n };\n \n struct ena_com_create_io_ctx {\n@@ -379,7 +382,7 @@ int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);\n \n /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism\n  * @ena_dev: ENA communication layer struct\n- * @realess_supported: readless mode (enable/disable)\n+ * @readless_supported: readless mode (enable/disable)\n  */\n void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,\n \t\t\t\tbool readless_supported);\n@@ -421,14 +424,16 @@ void ena_com_admin_destroy(struct ena_com_dev *ena_dev);\n \n /* ena_com_dev_reset - Perform device FLR to the device.\n  * @ena_dev: ENA communication layer struct\n+ * @reset_reason: Specify what is the trigger for the reset in case of an error.\n  *\n  * @return - 0 on success, negative value on failure.\n  */\n-int ena_com_dev_reset(struct ena_com_dev *ena_dev);\n+int ena_com_dev_reset(struct ena_com_dev *ena_dev,\n+\t\t      enum ena_regs_reset_reason_types reset_reason);\n \n /* ena_com_create_io_queue - Create io queue.\n  * @ena_dev: ENA communication layer struct\n- * ena_com_create_io_ctx - create context structure\n+ * @ctx - create context structure\n  *\n  * Create the submission and the completion queues.\n  *\n@@ -437,8 +442,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev);\n int ena_com_create_io_queue(struct ena_com_dev *ena_dev,\n \t\t\t    struct ena_com_create_io_ctx *ctx);\n \n-/* ena_com_admin_destroy - Destroy IO queue with the queue id - qid.\n+/* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.\n  * @ena_dev: ENA communication layer struct\n+ * @qid - the caller virtual queue id.\n  */\n void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);\n \n@@ -581,9 +587,8 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);\n  *\n  * @return: 0 on Success and negative value otherwise.\n  */\n-int\n-ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n-\t\t\t  struct ena_com_dev_get_features_ctx *get_feat_ctx);\n+int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,\n+\t\t\t      struct ena_com_dev_get_features_ctx *get_feat_ctx);\n \n /* ena_com_get_dev_basic_stats - Get device basic statistics\n  * @ena_dev: ENA communication layer struct\n@@ -608,9 +613,8 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);\n  *\n  * @return: 0 on Success and negative value otherwise.\n  */\n-int\n-ena_com_get_offload_settings(struct ena_com_dev *ena_dev,\n-\t\t\t     struct ena_admin_feature_offload_desc *offload);\n+int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,\n+\t\t\t\t struct ena_admin_feature_offload_desc *offload);\n \n /* ena_com_rss_init - Init RSS\n  * @ena_dev: ENA communication layer struct\n@@ -765,8 +769,8 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);\n  *\n  * Retrieve the RSS indirection table from the device.\n  *\n- * @note: If the caller called ena_com_indirect_table_fill_entry but didn't\n- * flash it to the device, the new configuration will be lost.\n+ * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash\n+ * it to the device, the new configuration will be lost.\n  *\n  * @return: 0 on Success and negative value otherwise.\n  */\n@@ -874,8 +878,7 @@ bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);\n  * moderation table back to the default parameters.\n  * @ena_dev: ENA communication layer struct\n  */\n-void\n-ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);\n+void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);\n \n /* ena_com_update_nonadaptive_moderation_interval_tx - Update the\n  * non-adaptive interval in Tx direction.\n@@ -884,9 +887,8 @@ ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);\n  *\n  * @return - 0 on success, negative value on failure.\n  */\n-int\n-ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,\n-\t\t\t\t\t\t  u32 tx_coalesce_usecs);\n+int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t\t      u32 tx_coalesce_usecs);\n \n /* ena_com_update_nonadaptive_moderation_interval_rx - Update the\n  * non-adaptive interval in Rx direction.\n@@ -895,9 +897,8 @@ ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,\n  *\n  * @return - 0 on success, negative value on failure.\n  */\n-int\n-ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,\n-\t\t\t\t\t\t  u32 rx_coalesce_usecs);\n+int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t\t      u32 rx_coalesce_usecs);\n \n /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the\n  * non-adaptive interval in Tx direction.\n@@ -905,8 +906,7 @@ ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,\n  *\n  * @return - interval in usec\n  */\n-unsigned int\n-ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);\n+unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);\n \n /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the\n  * non-adaptive interval in Rx direction.\n@@ -914,8 +914,7 @@ ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);\n  *\n  * @return - interval in usec\n  */\n-unsigned int\n-ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);\n+unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);\n \n /* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt\n  * moderation table.\n@@ -940,20 +939,17 @@ void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,\n \t\t\t\t       enum ena_intr_moder_level level,\n \t\t\t\t       struct ena_intr_moder_entry *entry);\n \n-static inline bool\n-ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)\n+static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)\n {\n \treturn ena_dev->adaptive_coalescing;\n }\n \n-static inline void\n-ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)\n+static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)\n {\n \tena_dev->adaptive_coalescing = true;\n }\n \n-static inline void\n-ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)\n+static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)\n {\n \tena_dev->adaptive_coalescing = false;\n }\n@@ -966,12 +962,11 @@ ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)\n  * @moder_tbl_idx: Current table level as input update new level as return\n  * value.\n  */\n-static inline void\n-ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,\n-\t\t\t\t  unsigned int pkts,\n-\t\t\t\t  unsigned int bytes,\n-\t\t\t\t  unsigned int *smoothed_interval,\n-\t\t\t\t  unsigned int *moder_tbl_idx)\n+static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,\n+\t\t\t\t\t\t     unsigned int pkts,\n+\t\t\t\t\t\t     unsigned int bytes,\n+\t\t\t\t\t\t     unsigned int *smoothed_interval,\n+\t\t\t\t\t\t     unsigned int *moder_tbl_idx)\n {\n \tenum ena_intr_moder_level curr_moder_idx, new_moder_idx;\n \tstruct ena_intr_moder_entry *curr_moder_entry;\n@@ -1001,17 +996,20 @@ ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,\n \tif (curr_moder_idx == ENA_INTR_MODER_LOWEST) {\n \t\tif ((pkts > curr_moder_entry->pkts_per_interval) ||\n \t\t    (bytes > curr_moder_entry->bytes_per_interval))\n-\t\t\tnew_moder_idx = (enum ena_intr_moder_level)(curr_moder_idx + 1);\n+\t\t\tnew_moder_idx =\n+\t\t\t\t(enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);\n \t} else {\n-\t\tpred_moder_entry = &intr_moder_tbl[curr_moder_idx - 1];\n+\t\tpred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE];\n \n \t\tif ((pkts <= pred_moder_entry->pkts_per_interval) ||\n \t\t    (bytes <= pred_moder_entry->bytes_per_interval))\n-\t\t\tnew_moder_idx = (enum ena_intr_moder_level)(curr_moder_idx - 1);\n+\t\t\tnew_moder_idx =\n+\t\t\t\t(enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE);\n \t\telse if ((pkts > curr_moder_entry->pkts_per_interval) ||\n \t\t\t (bytes > curr_moder_entry->bytes_per_interval)) {\n \t\t\tif (curr_moder_idx != ENA_INTR_MODER_HIGHEST)\n-\t\t\t\tnew_moder_idx = (enum ena_intr_moder_level)(curr_moder_idx + 1);\n+\t\t\t\tnew_moder_idx =\n+\t\t\t\t\t(enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);\n \t\t}\n \t}\n \tnew_moder_entry = &intr_moder_tbl[new_moder_idx];\n@@ -1044,18 +1042,12 @@ static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,\n \n \tintr_reg->intr_control |=\n \t\t(tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)\n-\t\t& ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;\n+\t\t& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;\n \n \tif (unmask)\n \t\tintr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;\n }\n \n-int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,\n-\t\t\t\t   u32 len);\n-\n-int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,\n-\t\t\t\t\t  u32 funct_queue);\n-\n #if defined(__cplusplus)\n }\n #endif /* __cplusplus */\ndiff --git a/drivers/net/ena/base/ena_defs/ena_admin_defs.h b/drivers/net/ena/base/ena_defs/ena_admin_defs.h\nindex 7a031d903..04d4e9a59 100644\n--- a/drivers/net/ena/base/ena_defs/ena_admin_defs.h\n+++ b/drivers/net/ena/base/ena_defs/ena_admin_defs.h\n@@ -34,174 +34,140 @@\n #ifndef _ENA_ADMIN_H_\n #define _ENA_ADMIN_H_\n \n-/* admin commands opcodes */\n enum ena_admin_aq_opcode {\n-\t/* create submission queue */\n-\tENA_ADMIN_CREATE_SQ = 1,\n+\tENA_ADMIN_CREATE_SQ\t= 1,\n \n-\t/* destroy submission queue */\n-\tENA_ADMIN_DESTROY_SQ = 2,\n+\tENA_ADMIN_DESTROY_SQ\t= 2,\n \n-\t/* create completion queue */\n-\tENA_ADMIN_CREATE_CQ = 3,\n+\tENA_ADMIN_CREATE_CQ\t= 3,\n \n-\t/* destroy completion queue */\n-\tENA_ADMIN_DESTROY_CQ = 4,\n+\tENA_ADMIN_DESTROY_CQ\t= 4,\n \n-\t/* get capabilities of particular feature */\n-\tENA_ADMIN_GET_FEATURE = 8,\n+\tENA_ADMIN_GET_FEATURE\t= 8,\n \n-\t/* get capabilities of particular feature */\n-\tENA_ADMIN_SET_FEATURE = 9,\n+\tENA_ADMIN_SET_FEATURE\t= 9,\n \n-\t/* get statistics */\n-\tENA_ADMIN_GET_STATS = 11,\n+\tENA_ADMIN_GET_STATS\t= 11,\n };\n \n-/* admin command completion status codes */\n enum ena_admin_aq_completion_status {\n-\t/* Request completed successfully */\n-\tENA_ADMIN_SUCCESS = 0,\n+\tENA_ADMIN_SUCCESS\t\t\t= 0,\n \n-\t/* no resources to satisfy request */\n-\tENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,\n+\tENA_ADMIN_RESOURCE_ALLOCATION_FAILURE\t= 1,\n \n-\t/* Bad opcode in request descriptor */\n-\tENA_ADMIN_BAD_OPCODE = 2,\n+\tENA_ADMIN_BAD_OPCODE\t\t\t= 2,\n \n-\t/* Unsupported opcode in request descriptor */\n-\tENA_ADMIN_UNSUPPORTED_OPCODE = 3,\n+\tENA_ADMIN_UNSUPPORTED_OPCODE\t\t= 3,\n \n-\t/* Wrong request format */\n-\tENA_ADMIN_MALFORMED_REQUEST = 4,\n+\tENA_ADMIN_MALFORMED_REQUEST\t\t= 4,\n \n-\t/* One of parameters is not valid. Provided in ACQ entry\n-\t * extended_status\n-\t */\n-\tENA_ADMIN_ILLEGAL_PARAMETER = 5,\n+\t/* Additional status is provided in ACQ entry extended_status */\n+\tENA_ADMIN_ILLEGAL_PARAMETER\t\t= 5,\n \n-\t/* unexpected error */\n-\tENA_ADMIN_UNKNOWN_ERROR = 6,\n+\tENA_ADMIN_UNKNOWN_ERROR\t\t\t= 6,\n };\n \n-/* get/set feature subcommands opcodes */\n enum ena_admin_aq_feature_id {\n-\t/* list of all supported attributes/capabilities in the ENA */\n-\tENA_ADMIN_DEVICE_ATTRIBUTES = 1,\n+\tENA_ADMIN_DEVICE_ATTRIBUTES\t\t= 1,\n+\n+\tENA_ADMIN_MAX_QUEUES_NUM\t\t= 2,\n \n-\t/* max number of supported queues per for every queues type */\n-\tENA_ADMIN_MAX_QUEUES_NUM = 2,\n+\tENA_ADMIN_HW_HINTS\t\t\t= 3,\n \n-\t/* Receive Side Scaling (RSS) function */\n-\tENA_ADMIN_RSS_HASH_FUNCTION = 10,\n+\tENA_ADMIN_RSS_HASH_FUNCTION\t\t= 10,\n \n-\t/* stateless TCP/UDP/IP offload capabilities. */\n-\tENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,\n+\tENA_ADMIN_STATELESS_OFFLOAD_CONFIG\t= 11,\n \n-\t/* Multiple tuples flow table configuration */\n-\tENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,\n+\tENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG\t= 12,\n \n-\t/* max MTU, current MTU */\n-\tENA_ADMIN_MTU = 14,\n+\tENA_ADMIN_MTU\t\t\t\t= 14,\n \n-\t/* Receive Side Scaling (RSS) hash input */\n-\tENA_ADMIN_RSS_HASH_INPUT = 18,\n+\tENA_ADMIN_RSS_HASH_INPUT\t\t= 18,\n \n-\t/* interrupt moderation parameters */\n-\tENA_ADMIN_INTERRUPT_MODERATION = 20,\n+\tENA_ADMIN_INTERRUPT_MODERATION\t\t= 20,\n \n-\t/* AENQ configuration */\n-\tENA_ADMIN_AENQ_CONFIG = 26,\n+\tENA_ADMIN_AENQ_CONFIG\t\t\t= 26,\n \n-\t/* Link configuration */\n-\tENA_ADMIN_LINK_CONFIG = 27,\n+\tENA_ADMIN_LINK_CONFIG\t\t\t= 27,\n \n-\t/* Host attributes configuration */\n-\tENA_ADMIN_HOST_ATTR_CONFIG = 28,\n+\tENA_ADMIN_HOST_ATTR_CONFIG\t\t= 28,\n \n-\t/* Number of valid opcodes */\n-\tENA_ADMIN_FEATURES_OPCODE_NUM = 32,\n+\tENA_ADMIN_FEATURES_OPCODE_NUM\t\t= 32,\n };\n \n-/* descriptors and headers placement */\n enum ena_admin_placement_policy_type {\n-\t/* descriptors and headers are in OS memory */\n-\tENA_ADMIN_PLACEMENT_POLICY_HOST = 1,\n+\t/* descriptors and headers are in host memory */\n+\tENA_ADMIN_PLACEMENT_POLICY_HOST\t= 1,\n \n-\t/* descriptors and headers in device memory (a.k.a Low Latency\n+\t/* descriptors and headers are in device memory (a.k.a Low Latency\n \t * Queue)\n \t */\n-\tENA_ADMIN_PLACEMENT_POLICY_DEV = 3,\n+\tENA_ADMIN_PLACEMENT_POLICY_DEV\t= 3,\n };\n \n-/* link speeds */\n enum ena_admin_link_types {\n-\tENA_ADMIN_LINK_SPEED_1G = 0x1,\n+\tENA_ADMIN_LINK_SPEED_1G\t\t= 0x1,\n \n-\tENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,\n+\tENA_ADMIN_LINK_SPEED_2_HALF_G\t= 0x2,\n \n-\tENA_ADMIN_LINK_SPEED_5G = 0x4,\n+\tENA_ADMIN_LINK_SPEED_5G\t\t= 0x4,\n \n-\tENA_ADMIN_LINK_SPEED_10G = 0x8,\n+\tENA_ADMIN_LINK_SPEED_10G\t= 0x8,\n \n-\tENA_ADMIN_LINK_SPEED_25G = 0x10,\n+\tENA_ADMIN_LINK_SPEED_25G\t= 0x10,\n \n-\tENA_ADMIN_LINK_SPEED_40G = 0x20,\n+\tENA_ADMIN_LINK_SPEED_40G\t= 0x20,\n \n-\tENA_ADMIN_LINK_SPEED_50G = 0x40,\n+\tENA_ADMIN_LINK_SPEED_50G\t= 0x40,\n \n-\tENA_ADMIN_LINK_SPEED_100G = 0x80,\n+\tENA_ADMIN_LINK_SPEED_100G\t= 0x80,\n \n-\tENA_ADMIN_LINK_SPEED_200G = 0x100,\n+\tENA_ADMIN_LINK_SPEED_200G\t= 0x100,\n \n-\tENA_ADMIN_LINK_SPEED_400G = 0x200,\n+\tENA_ADMIN_LINK_SPEED_400G\t= 0x200,\n };\n \n-/* completion queue update policy */\n enum ena_admin_completion_policy_type {\n-\t/* cqe for each sq descriptor */\n-\tENA_ADMIN_COMPLETION_POLICY_DESC = 0,\n+\t/* completion queue entry for each sq descriptor */\n+\tENA_ADMIN_COMPLETION_POLICY_DESC\t\t= 0,\n \n-\t/* cqe upon request in sq descriptor */\n-\tENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,\n+\t/* completion queue entry upon request in sq descriptor */\n+\tENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND\t= 1,\n \n \t/* current queue head pointer is updated in OS memory upon sq\n \t * descriptor request\n \t */\n-\tENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,\n+\tENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND\t= 2,\n \n \t/* current queue head pointer is updated in OS memory for each sq\n \t * descriptor\n \t */\n-\tENA_ADMIN_COMPLETION_POLICY_HEAD = 3,\n+\tENA_ADMIN_COMPLETION_POLICY_HEAD\t\t= 3,\n };\n \n-/* type of get statistics command */\n+/* basic stats return ena_admin_basic_stats while extanded stats return a\n+ * buffer (string format) with additional statistics per queue and per\n+ * device id\n+ */\n enum ena_admin_get_stats_type {\n-\t/* Basic statistics */\n-\tENA_ADMIN_GET_STATS_TYPE_BASIC = 0,\n+\tENA_ADMIN_GET_STATS_TYPE_BASIC\t\t= 0,\n \n-\t/* Extended statistics */\n-\tENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,\n+\tENA_ADMIN_GET_STATS_TYPE_EXTENDED\t= 1,\n };\n \n-/* scope of get statistics command */\n enum ena_admin_get_stats_scope {\n-\tENA_ADMIN_SPECIFIC_QUEUE = 0,\n+\tENA_ADMIN_SPECIFIC_QUEUE\t= 0,\n \n-\tENA_ADMIN_ETH_TRAFFIC = 1,\n+\tENA_ADMIN_ETH_TRAFFIC\t\t= 1,\n };\n \n-/* ENA Admin Queue (AQ) common descriptor */\n struct ena_admin_aq_common_desc {\n-\t/* word 0 : */\n-\t/* command identificator to associate it with the completion\n-\t * 11:0 : command_id\n+\t/* 11:0 : command_id\n \t * 15:12 : reserved12\n \t */\n \tuint16_t command_id;\n \n-\t/* as appears in ena_aq_opcode */\n+\t/* as appears in ena_admin_aq_opcode */\n \tuint8_t opcode;\n \n \t/* 0 : phase\n@@ -214,24 +180,17 @@ struct ena_admin_aq_common_desc {\n \tuint8_t flags;\n };\n \n-/* used in ena_aq_entry. Can point directly to control data, or to a page\n- * list chunk. Used also at the end of indirect mode page list chunks, for\n- * chaining.\n+/* used in ena_admin_aq_entry. Can point directly to control data, or to a\n+ * page list chunk. Used also at the end of indirect mode page list chunks,\n+ * for chaining.\n  */\n struct ena_admin_ctrl_buff_info {\n-\t/* word 0 : indicates length of the buffer pointed by\n-\t * control_buffer_address.\n-\t */\n \tuint32_t length;\n \n-\t/* words 1:2 : points to control buffer (direct or indirect) */\n \tstruct ena_common_mem_addr address;\n };\n \n-/* submission queue full identification */\n struct ena_admin_sq {\n-\t/* word 0 : */\n-\t/* queue id */\n \tuint16_t sq_idx;\n \n \t/* 4:0 : reserved\n@@ -242,36 +201,25 @@ struct ena_admin_sq {\n \tuint8_t reserved1;\n };\n \n-/* AQ entry format */\n struct ena_admin_aq_entry {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* words 1:3 :  */\n \tunion {\n-\t\t/* command specific inline data */\n \t\tuint32_t inline_data_w1[3];\n \n-\t\t/* words 1:3 : points to control buffer (direct or\n-\t\t * indirect, chained if needed)\n-\t\t */\n \t\tstruct ena_admin_ctrl_buff_info control_buffer;\n \t} u;\n \n-\t/* command specific inline data */\n \tuint32_t inline_data_w4[12];\n };\n \n-/* ENA Admin Completion Queue (ACQ) common descriptor */\n struct ena_admin_acq_common_desc {\n-\t/* word 0 : */\n \t/* command identifier to associate it with the aq descriptor\n \t * 11:0 : command_id\n \t * 15:12 : reserved12\n \t */\n \tuint16_t command;\n \n-\t/* status of request execution */\n \tuint8_t status;\n \n \t/* 0 : phase\n@@ -279,33 +227,21 @@ struct ena_admin_acq_common_desc {\n \t */\n \tuint8_t flags;\n \n-\t/* word 1 : */\n-\t/* provides additional info */\n \tuint16_t extended_status;\n \n-\t/* submission queue head index, serves as a hint what AQ entries can\n-\t *    be revoked\n-\t */\n+\t/* serves as a hint what AQ entries can be revoked */\n \tuint16_t sq_head_indx;\n };\n \n-/* ACQ entry format */\n struct ena_admin_acq_entry {\n-\t/* words 0:1 :  */\n \tstruct ena_admin_acq_common_desc acq_common_descriptor;\n \n-\t/* response type specific data */\n \tuint32_t response_specific_data[14];\n };\n \n-/* ENA AQ Create Submission Queue command. Placed in control buffer pointed\n- * by AQ entry\n- */\n struct ena_admin_aq_create_sq_cmd {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* word 1 : */\n \t/* 4:0 : reserved0_w1\n \t * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx\n \t */\n@@ -337,7 +273,6 @@ struct ena_admin_aq_create_sq_cmd {\n \t */\n \tuint8_t sq_caps_3;\n \n-\t/* word 2 : */\n \t/* associated completion queue id. This CQ must be created prior to\n \t *    SQ creation\n \t */\n@@ -346,85 +281,62 @@ struct ena_admin_aq_create_sq_cmd {\n \t/* submission queue depth in entries */\n \tuint16_t sq_depth;\n \n-\t/* words 3:4 : SQ physical base address in OS memory. This field\n-\t * should not be used for Low Latency queues. Has to be page\n-\t * aligned.\n+\t/* SQ physical base address in OS memory. This field should not be\n+\t * used for Low Latency queues. Has to be page aligned.\n \t */\n \tstruct ena_common_mem_addr sq_ba;\n \n-\t/* words 5:6 : specifies queue head writeback location in OS\n-\t * memory. Valid if completion_policy is set to\n-\t * completion_policy_head_on_demand or completion_policy_head. Has\n-\t * to be cache aligned\n+\t/* specifies queue head writeback location in OS memory. Valid if\n+\t * completion_policy is set to completion_policy_head_on_demand or\n+\t * completion_policy_head. Has to be cache aligned\n \t */\n \tstruct ena_common_mem_addr sq_head_writeback;\n \n-\t/* word 7 : reserved word */\n \tuint32_t reserved0_w7;\n \n-\t/* word 8 : reserved word */\n \tuint32_t reserved0_w8;\n };\n \n-/* submission queue direction */\n enum ena_admin_sq_direction {\n-\tENA_ADMIN_SQ_DIRECTION_TX = 1,\n+\tENA_ADMIN_SQ_DIRECTION_TX\t= 1,\n \n-\tENA_ADMIN_SQ_DIRECTION_RX = 2,\n+\tENA_ADMIN_SQ_DIRECTION_RX\t= 2,\n };\n \n-/* ENA Response for Create SQ Command. Appears in ACQ entry as\n- * response_specific_data\n- */\n struct ena_admin_acq_create_sq_resp_desc {\n-\t/* words 0:1 : Common Admin Queue completion descriptor */\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n \n-\t/* word 2 : */\n-\t/* sq identifier */\n \tuint16_t sq_idx;\n \n \tuint16_t reserved;\n \n-\t/* word 3 : queue doorbell address as an offset to PCIe MMIO REG BAR */\n+\t/* queue doorbell address as an offset to PCIe MMIO REG BAR */\n \tuint32_t sq_doorbell_offset;\n \n-\t/* word 4 : low latency queue ring base address as an offset to\n-\t * PCIe MMIO LLQ_MEM BAR\n+\t/* low latency queue ring base address as an offset to PCIe MMIO\n+\t * LLQ_MEM BAR\n \t */\n \tuint32_t llq_descriptors_offset;\n \n-\t/* word 5 : low latency queue headers' memory as an offset to PCIe\n-\t * MMIO LLQ_MEM BAR\n+\t/* low latency queue headers' memory as an offset to PCIe MMIO\n+\t * LLQ_MEM BAR\n \t */\n \tuint32_t llq_headers_offset;\n };\n \n-/* ENA AQ Destroy Submission Queue command. Placed in control buffer\n- * pointed by AQ entry\n- */\n struct ena_admin_aq_destroy_sq_cmd {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* words 1 :  */\n \tstruct ena_admin_sq sq;\n };\n \n-/* ENA Response for Destroy SQ Command. Appears in ACQ entry as\n- * response_specific_data\n- */\n struct ena_admin_acq_destroy_sq_resp_desc {\n-\t/* words 0:1 : Common Admin Queue completion descriptor */\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n };\n \n-/* ENA AQ Create Completion Queue command */\n struct ena_admin_aq_create_cq_cmd {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* word 1 : */\n \t/* 4:0 : reserved5\n \t * 5 : interrupt_mode_enabled - if set, cq operates\n \t *    in interrupt mode, otherwise - polling\n@@ -441,62 +353,39 @@ struct ena_admin_aq_create_cq_cmd {\n \t/* completion queue depth in # of entries. must be power of 2 */\n \tuint16_t cq_depth;\n \n-\t/* word 2 : msix vector assigned to this cq */\n+\t/* msix vector assigned to this cq */\n \tuint32_t msix_vector;\n \n-\t/* words 3:4 : cq physical base address in OS memory. CQ must be\n-\t * physically contiguous\n+\t/* cq physical base address in OS memory. CQ must be physically\n+\t * contiguous\n \t */\n \tstruct ena_common_mem_addr cq_ba;\n };\n \n-/* ENA Response for Create CQ Command. Appears in ACQ entry as response\n- * specific data\n- */\n struct ena_admin_acq_create_cq_resp_desc {\n-\t/* words 0:1 : Common Admin Queue completion descriptor */\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n \n-\t/* word 2 : */\n-\t/* cq identifier */\n \tuint16_t cq_idx;\n \n-\t/* actual cq depth in # of entries */\n+\t/* actual cq depth in number of entries */\n \tuint16_t cq_actual_depth;\n \n-\t/* word 3 : cpu numa node address as an offset to PCIe MMIO REG BAR */\n \tuint32_t numa_node_register_offset;\n \n-\t/* word 4 : completion head doorbell address as an offset to PCIe\n-\t * MMIO REG BAR\n-\t */\n \tuint32_t cq_head_db_register_offset;\n \n-\t/* word 5 : interrupt unmask register address as an offset into\n-\t * PCIe MMIO REG BAR\n-\t */\n \tuint32_t cq_interrupt_unmask_register_offset;\n };\n \n-/* ENA AQ Destroy Completion Queue command. Placed in control buffer\n- * pointed by AQ entry\n- */\n struct ena_admin_aq_destroy_cq_cmd {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* word 1 : */\n-\t/* associated queue id. */\n \tuint16_t cq_idx;\n \n \tuint16_t reserved1;\n };\n \n-/* ENA Response for Destroy CQ Command. Appears in ACQ entry as\n- * response_specific_data\n- */\n struct ena_admin_acq_destroy_cq_resp_desc {\n-\t/* words 0:1 : Common Admin Queue completion descriptor */\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n };\n \n@@ -504,21 +393,15 @@ struct ena_admin_acq_destroy_cq_resp_desc {\n  * buffer pointed by AQ entry\n  */\n struct ena_admin_aq_get_stats_cmd {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* words 1:3 :  */\n \tunion {\n \t\t/* command specific inline data */\n \t\tuint32_t inline_data_w1[3];\n \n-\t\t/* words 1:3 : points to control buffer (direct or\n-\t\t * indirect, chained if needed)\n-\t\t */\n \t\tstruct ena_admin_ctrl_buff_info control_buffer;\n \t} u;\n \n-\t/* word 4 : */\n \t/* stats type as defined in enum ena_admin_get_stats_type */\n \tuint8_t type;\n \n@@ -527,7 +410,6 @@ struct ena_admin_aq_get_stats_cmd {\n \n \tuint16_t reserved3;\n \n-\t/* word 5 : */\n \t/* queue id. used when scope is specific_queue */\n \tuint16_t queue_idx;\n \n@@ -539,89 +421,60 @@ struct ena_admin_aq_get_stats_cmd {\n \n /* Basic Statistics Command. */\n struct ena_admin_basic_stats {\n-\t/* word 0 :  */\n \tuint32_t tx_bytes_low;\n \n-\t/* word 1 :  */\n \tuint32_t tx_bytes_high;\n \n-\t/* word 2 :  */\n \tuint32_t tx_pkts_low;\n \n-\t/* word 3 :  */\n \tuint32_t tx_pkts_high;\n \n-\t/* word 4 :  */\n \tuint32_t rx_bytes_low;\n \n-\t/* word 5 :  */\n \tuint32_t rx_bytes_high;\n \n-\t/* word 6 :  */\n \tuint32_t rx_pkts_low;\n \n-\t/* word 7 :  */\n \tuint32_t rx_pkts_high;\n \n-\t/* word 8 :  */\n \tuint32_t rx_drops_low;\n \n-\t/* word 9 :  */\n \tuint32_t rx_drops_high;\n };\n \n-/* ENA Response for Get Statistics Command. Appears in ACQ entry as\n- * response_specific_data\n- */\n struct ena_admin_acq_get_stats_resp {\n-\t/* words 0:1 : Common Admin Queue completion descriptor */\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n \n-\t/* words 2:11 :  */\n \tstruct ena_admin_basic_stats basic_stats;\n };\n \n-/* ENA Get/Set Feature common descriptor. Appears as inline word in\n- * ena_aq_entry\n- */\n struct ena_admin_get_set_feature_common_desc {\n-\t/* word 0 : */\n \t/* 1:0 : select - 0x1 - current value; 0x3 - default\n \t *    value\n \t * 7:3 : reserved3\n \t */\n \tuint8_t flags;\n \n-\t/* as appears in ena_feature_id */\n+\t/* as appears in ena_admin_aq_feature_id */\n \tuint8_t feature_id;\n \n-\t/* reserved16 */\n \tuint16_t reserved16;\n };\n \n-/* ENA Device Attributes Feature descriptor. */\n struct ena_admin_device_attr_feature_desc {\n-\t/* word 0 : implementation id */\n \tuint32_t impl_id;\n \n-\t/* word 1 : device version */\n \tuint32_t device_version;\n \n-\t/* word 2 : bit map of which bits are supported value of 1\n-\t * indicated that this feature is supported and can perform SET/GET\n-\t * for it\n-\t */\n+\t/* bitmap of ena_admin_aq_feature_id */\n \tuint32_t supported_features;\n \n-\t/* word 3 :  */\n \tuint32_t reserved3;\n \n-\t/* word 4 : Indicates how many bits are used physical address\n-\t * access.\n-\t */\n+\t/* Indicates how many bits are used physical address access. */\n \tuint32_t phys_addr_width;\n \n-\t/* word 5 : Indicates how many bits are used virtual address access. */\n+\t/* Indicates how many bits are used virtual address access. */\n \tuint32_t virt_addr_width;\n \n \t/* unicast MAC address (in Network byte order) */\n@@ -629,36 +482,27 @@ struct ena_admin_device_attr_feature_desc {\n \n \tuint8_t reserved7[2];\n \n-\t/* word 8 : Max supported MTU value */\n \tuint32_t max_mtu;\n };\n \n-/* ENA Max Queues Feature descriptor. */\n struct ena_admin_queue_feature_desc {\n-\t/* word 0 : Max number of submission queues (including LLQs) */\n+\t/* including LLQs */\n \tuint32_t max_sq_num;\n \n-\t/* word 1 : Max submission queue depth */\n \tuint32_t max_sq_depth;\n \n-\t/* word 2 : Max number of completion queues */\n \tuint32_t max_cq_num;\n \n-\t/* word 3 : Max completion queue depth */\n \tuint32_t max_cq_depth;\n \n-\t/* word 4 : Max number of LLQ submission queues */\n \tuint32_t max_llq_num;\n \n-\t/* word 5 : Max submission queue depth of LLQ */\n \tuint32_t max_llq_depth;\n \n-\t/* word 6 : Max header size */\n \tuint32_t max_header_size;\n \n-\t/* word 7 : */\n-\t/* Maximum Descriptors number, including meta descriptors, allowed\n-\t *    for a single Tx packet\n+\t/* Maximum Descriptors number, including meta descriptor, allowed for\n+\t *    a single Tx packet\n \t */\n \tuint16_t max_packet_tx_descs;\n \n@@ -666,86 +510,69 @@ struct ena_admin_queue_feature_desc {\n \tuint16_t max_packet_rx_descs;\n };\n \n-/* ENA MTU Set Feature descriptor. */\n struct ena_admin_set_feature_mtu_desc {\n-\t/* word 0 : mtu payload size (exclude L2) */\n+\t/* exclude L2 */\n \tuint32_t mtu;\n };\n \n-/* ENA host attributes Set Feature descriptor. */\n struct ena_admin_set_feature_host_attr_desc {\n-\t/* words 0:1 : host OS info base address in OS memory. host info is\n-\t * 4KB of physically contiguous\n+\t/* host OS info base address in OS memory. host info is 4KB of\n+\t * physically contiguous\n \t */\n \tstruct ena_common_mem_addr os_info_ba;\n \n-\t/* words 2:3 : host debug area base address in OS memory. debug\n-\t * area must be physically contiguous\n+\t/* host debug area base address in OS memory. debug area must be\n+\t * physically contiguous\n \t */\n \tstruct ena_common_mem_addr debug_ba;\n \n-\t/* word 4 : debug area size */\n+\t/* debug area size */\n \tuint32_t debug_area_size;\n };\n \n-/* ENA Interrupt Moderation Get Feature descriptor. */\n struct ena_admin_feature_intr_moder_desc {\n-\t/* word 0 : */\n \t/* interrupt delay granularity in usec */\n \tuint16_t intr_delay_resolution;\n \n \tuint16_t reserved;\n };\n \n-/* ENA Link Get Feature descriptor. */\n struct ena_admin_get_feature_link_desc {\n-\t/* word 0 : Link speed in Mb */\n+\t/* Link speed in Mb */\n \tuint32_t speed;\n \n-\t/* word 1 : supported speeds (bit field of enum ena_admin_link\n-\t * types)\n-\t */\n+\t/* bit field of enum ena_admin_link types */\n \tuint32_t supported;\n \n-\t/* word 2 : */\n-\t/* 0 : autoneg - auto negotiation\n+\t/* 0 : autoneg\n \t * 1 : duplex - Full Duplex\n \t * 31:2 : reserved2\n \t */\n \tuint32_t flags;\n };\n \n-/* ENA AENQ Feature descriptor. */\n struct ena_admin_feature_aenq_desc {\n-\t/* word 0 : bitmask for AENQ groups the device can report */\n+\t/* bitmask for AENQ groups the device can report */\n \tuint32_t supported_groups;\n \n-\t/* word 1 : bitmask for AENQ groups to report */\n+\t/* bitmask for AENQ groups to report */\n \tuint32_t enabled_groups;\n };\n \n-/* ENA Stateless Offload Feature descriptor. */\n struct ena_admin_feature_offload_desc {\n-\t/* word 0 : */\n-\t/* Trasmit side stateless offload\n-\t * 0 : TX_L3_csum_ipv4 - IPv4 checksum\n-\t * 1 : TX_L4_ipv4_csum_part - TCP/UDP over IPv4\n-\t *    checksum, the checksum field should be initialized\n-\t *    with pseudo header checksum\n-\t * 2 : TX_L4_ipv4_csum_full - TCP/UDP over IPv4\n-\t *    checksum\n-\t * 3 : TX_L4_ipv6_csum_part - TCP/UDP over IPv6\n-\t *    checksum, the checksum field should be initialized\n-\t *    with pseudo header checksum\n-\t * 4 : TX_L4_ipv6_csum_full - TCP/UDP over IPv6\n-\t *    checksum\n-\t * 5 : tso_ipv4 - TCP/IPv4 Segmentation Offloading\n-\t * 6 : tso_ipv6 - TCP/IPv6 Segmentation Offloading\n-\t * 7 : tso_ecn - TCP Segmentation with ECN\n+\t/* 0 : TX_L3_csum_ipv4\n+\t * 1 : TX_L4_ipv4_csum_part - The checksum field\n+\t *    should be initialized with pseudo header checksum\n+\t * 2 : TX_L4_ipv4_csum_full\n+\t * 3 : TX_L4_ipv6_csum_part - The checksum field\n+\t *    should be initialized with pseudo header checksum\n+\t * 4 : TX_L4_ipv6_csum_full\n+\t * 5 : tso_ipv4\n+\t * 6 : tso_ipv6\n+\t * 7 : tso_ecn\n \t */\n \tuint32_t tx;\n \n-\t/* word 1 : */\n \t/* Receive side supported stateless offload\n \t * 0 : RX_L3_csum_ipv4 - IPv4 checksum\n \t * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum\n@@ -754,118 +581,94 @@ struct ena_admin_feature_offload_desc {\n \t */\n \tuint32_t rx_supported;\n \n-\t/* word 2 : */\n-\t/* Receive side enabled stateless offload */\n \tuint32_t rx_enabled;\n };\n \n-/* hash functions */\n enum ena_admin_hash_functions {\n-\t/* Toeplitz hash */\n-\tENA_ADMIN_TOEPLITZ = 1,\n+\tENA_ADMIN_TOEPLITZ\t= 1,\n \n-\t/* CRC32 hash */\n-\tENA_ADMIN_CRC32 = 2,\n+\tENA_ADMIN_CRC32\t\t= 2,\n };\n \n-/* ENA RSS flow hash control buffer structure */\n struct ena_admin_feature_rss_flow_hash_control {\n-\t/* word 0 : number of valid keys */\n \tuint32_t keys_num;\n \n-\t/* word 1 :  */\n \tuint32_t reserved;\n \n-\t/* Toeplitz keys */\n \tuint32_t key[10];\n };\n \n-/* ENA RSS Flow Hash Function */\n struct ena_admin_feature_rss_flow_hash_function {\n-\t/* word 0 : */\n-\t/* supported hash functions\n-\t * 7:0 : funcs - supported hash functions (bitmask\n-\t *    accroding to ena_admin_hash_functions)\n-\t */\n+\t/* 7:0 : funcs - bitmask of ena_admin_hash_functions */\n \tuint32_t supported_func;\n \n-\t/* word 1 : */\n-\t/* selected hash func\n-\t * 7:0 : selected_func - selected hash function\n-\t *    (bitmask accroding to ena_admin_hash_functions)\n+\t/* 7:0 : selected_func - bitmask of\n+\t *    ena_admin_hash_functions\n \t */\n \tuint32_t selected_func;\n \n-\t/* word 2 : initial value */\n+\t/* initial value */\n \tuint32_t init_val;\n };\n \n /* RSS flow hash protocols */\n enum ena_admin_flow_hash_proto {\n-\t/* tcp/ipv4 */\n-\tENA_ADMIN_RSS_TCP4 = 0,\n+\tENA_ADMIN_RSS_TCP4\t= 0,\n \n-\t/* udp/ipv4 */\n-\tENA_ADMIN_RSS_UDP4 = 1,\n+\tENA_ADMIN_RSS_UDP4\t= 1,\n \n-\t/* tcp/ipv6 */\n-\tENA_ADMIN_RSS_TCP6 = 2,\n+\tENA_ADMIN_RSS_TCP6\t= 2,\n \n-\t/* udp/ipv6 */\n-\tENA_ADMIN_RSS_UDP6 = 3,\n+\tENA_ADMIN_RSS_UDP6\t= 3,\n \n-\t/* ipv4 not tcp/udp */\n-\tENA_ADMIN_RSS_IP4 = 4,\n+\tENA_ADMIN_RSS_IP4\t= 4,\n \n-\t/* ipv6 not tcp/udp */\n-\tENA_ADMIN_RSS_IP6 = 5,\n+\tENA_ADMIN_RSS_IP6\t= 5,\n \n-\t/* fragmented ipv4 */\n-\tENA_ADMIN_RSS_IP4_FRAG = 6,\n+\tENA_ADMIN_RSS_IP4_FRAG\t= 6,\n \n-\t/* not ipv4/6 */\n-\tENA_ADMIN_RSS_NOT_IP = 7,\n+\tENA_ADMIN_RSS_NOT_IP\t= 7,\n \n-\t/* max number of protocols */\n-\tENA_ADMIN_RSS_PROTO_NUM = 16,\n+\t/* TCPv6 with extension header */\n+\tENA_ADMIN_RSS_TCP6_EX\t= 8,\n+\n+\t/* IPv6 with extension header */\n+\tENA_ADMIN_RSS_IP6_EX\t= 9,\n+\n+\tENA_ADMIN_RSS_PROTO_NUM\t= 16,\n };\n \n /* RSS flow hash fields */\n enum ena_admin_flow_hash_fields {\n \t/* Ethernet Dest Addr */\n-\tENA_ADMIN_RSS_L2_DA = 0,\n+\tENA_ADMIN_RSS_L2_DA\t= BIT(0),\n \n \t/* Ethernet Src Addr */\n-\tENA_ADMIN_RSS_L2_SA = 1,\n+\tENA_ADMIN_RSS_L2_SA\t= BIT(1),\n \n \t/* ipv4/6 Dest Addr */\n-\tENA_ADMIN_RSS_L3_DA = 2,\n+\tENA_ADMIN_RSS_L3_DA\t= BIT(2),\n \n \t/* ipv4/6 Src Addr */\n-\tENA_ADMIN_RSS_L3_SA = 5,\n+\tENA_ADMIN_RSS_L3_SA\t= BIT(3),\n \n \t/* tcp/udp Dest Port */\n-\tENA_ADMIN_RSS_L4_DP = 6,\n+\tENA_ADMIN_RSS_L4_DP\t= BIT(4),\n \n \t/* tcp/udp Src Port */\n-\tENA_ADMIN_RSS_L4_SP = 7,\n+\tENA_ADMIN_RSS_L4_SP\t= BIT(5),\n };\n \n-/* hash input fields for flow protocol */\n struct ena_admin_proto_input {\n-\t/* word 0 : */\n \t/* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */\n \tuint16_t fields;\n \n \tuint16_t reserved2;\n };\n \n-/* ENA RSS hash control buffer structure */\n struct ena_admin_feature_rss_hash_control {\n-\t/* supported input fields */\n \tstruct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];\n \n-\t/* selected input fields */\n \tstruct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];\n \n \tstruct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];\n@@ -873,11 +676,9 @@ struct ena_admin_feature_rss_hash_control {\n \tstruct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];\n };\n \n-/* ENA RSS flow hash input */\n struct ena_admin_feature_rss_flow_hash_input {\n-\t/* word 0 : */\n \t/* supported hash input sorting\n-\t * 1 : L3_sort - support swap L3 addresses if DA\n+\t * 1 : L3_sort - support swap L3 addresses if DA is\n \t *    smaller than SA\n \t * 2 : L4_sort - support swap L4 ports if DP smaller\n \t *    SP\n@@ -893,46 +694,37 @@ struct ena_admin_feature_rss_flow_hash_input {\n \tuint16_t enabled_input_sort;\n };\n \n-/* Operating system type */\n enum ena_admin_os_type {\n-\t/* Linux OS */\n-\tENA_ADMIN_OS_LINUX = 1,\n+\tENA_ADMIN_OS_LINUX\t= 1,\n \n-\t/* Windows OS */\n-\tENA_ADMIN_OS_WIN = 2,\n+\tENA_ADMIN_OS_WIN\t= 2,\n \n-\t/* DPDK OS */\n-\tENA_ADMIN_OS_DPDK = 3,\n+\tENA_ADMIN_OS_DPDK\t= 3,\n \n-\t/* FreeBSD OS */\n-\tENA_ADMIN_OS_FREEBSD = 4,\n+\tENA_ADMIN_OS_FREEBSD\t= 4,\n \n-\t/* PXE OS */\n-\tENA_ADMIN_OS_IPXE = 5,\n+\tENA_ADMIN_OS_IPXE\t= 5,\n };\n \n-/* host info */\n struct ena_admin_host_info {\n-\t/* word 0 : OS type defined in enum ena_os_type */\n+\t/* defined in enum ena_admin_os_type */\n \tuint32_t os_type;\n \n \t/* os distribution string format */\n \tuint8_t os_dist_str[128];\n \n-\t/* word 33 : OS distribution numeric format */\n+\t/* OS distribution numeric format */\n \tuint32_t os_dist;\n \n \t/* kernel version string format */\n \tuint8_t kernel_ver_str[32];\n \n-\t/* word 42 : Kernel version numeric format */\n+\t/* Kernel version numeric format */\n \tuint32_t kernel_ver;\n \n-\t/* word 43 : */\n-\t/* driver version\n-\t * 7:0 : major - major\n-\t * 15:8 : minor - minor\n-\t * 23:16 : sub_minor - sub minor\n+\t/* 7:0 : major\n+\t * 15:8 : minor\n+\t * 23:16 : sub_minor\n \t */\n \tuint32_t driver_version;\n \n@@ -940,220 +732,200 @@ struct ena_admin_host_info {\n \tuint32_t supported_network_features[4];\n };\n \n-/* ENA RSS indirection table entry */\n struct ena_admin_rss_ind_table_entry {\n-\t/* word 0 : */\n-\t/* cq identifier */\n \tuint16_t cq_idx;\n \n \tuint16_t reserved;\n };\n \n-/* ENA RSS indirection table */\n struct ena_admin_feature_rss_ind_table {\n-\t/* word 0 : */\n \t/* min supported table size (2^min_size) */\n \tuint16_t min_size;\n \n \t/* max supported table size (2^max_size) */\n \tuint16_t max_size;\n \n-\t/* word 1 : */\n \t/* table size (2^size) */\n \tuint16_t size;\n \n \tuint16_t reserved;\n \n-\t/* word 2 : index of the inline entry. 0xFFFFFFFF means invalid */\n+\t/* index of the inline entry. 0xFFFFFFFF means invalid */\n \tuint32_t inline_index;\n \n-\t/* words 3 : used for updating single entry, ignored when setting\n-\t * the entire table through the control buffer.\n+\t/* used for updating single entry, ignored when setting the entire\n+\t * table through the control buffer.\n \t */\n \tstruct ena_admin_rss_ind_table_entry inline_entry;\n };\n \n-/* ENA Get Feature command */\n+/* When hint value is 0, driver should use it's own predefined value */\n+struct ena_admin_ena_hw_hints {\n+\t/* value in ms */\n+\tuint16_t mmio_read_timeout;\n+\n+\t/* value in ms */\n+\tuint16_t driver_watchdog_timeout;\n+\n+\t/* Per packet tx completion timeout. value in ms */\n+\tuint16_t missing_tx_completion_timeout;\n+\n+\tuint16_t missed_tx_completion_count_threshold_to_reset;\n+\n+\t/* value in ms */\n+\tuint16_t admin_completion_tx_timeout;\n+\n+\tuint16_t netdev_wd_timeout;\n+\n+\tuint16_t max_tx_sgl_size;\n+\n+\tuint16_t max_rx_sgl_size;\n+\n+\tuint16_t reserved[8];\n+};\n+\n struct ena_admin_get_feat_cmd {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* words 1:3 : points to control buffer (direct or indirect,\n-\t * chained if needed)\n-\t */\n \tstruct ena_admin_ctrl_buff_info control_buffer;\n \n-\t/* words 4 :  */\n \tstruct ena_admin_get_set_feature_common_desc feat_common;\n \n-\t/* words 5:15 :  */\n-\tunion {\n-\t\t/* raw words */\n-\t\tuint32_t raw[11];\n-\t} u;\n+\tuint32_t raw[11];\n };\n \n-/* ENA Get Feature command response */\n struct ena_admin_get_feat_resp {\n-\t/* words 0:1 :  */\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n \n-\t/* words 2:15 :  */\n \tunion {\n-\t\t/* raw words */\n \t\tuint32_t raw[14];\n \n-\t\t/* words 2:10 : Get Device Attributes */\n \t\tstruct ena_admin_device_attr_feature_desc dev_attr;\n \n-\t\t/* words 2:5 : Max queues num */\n \t\tstruct ena_admin_queue_feature_desc max_queue;\n \n-\t\t/* words 2:3 : AENQ configuration */\n \t\tstruct ena_admin_feature_aenq_desc aenq;\n \n-\t\t/* words 2:4 : Get Link configuration */\n \t\tstruct ena_admin_get_feature_link_desc link;\n \n-\t\t/* words 2:4 : offload configuration */\n \t\tstruct ena_admin_feature_offload_desc offload;\n \n-\t\t/* words 2:4 : rss flow hash function */\n \t\tstruct ena_admin_feature_rss_flow_hash_function flow_hash_func;\n \n-\t\t/* words 2 : rss flow hash input */\n \t\tstruct ena_admin_feature_rss_flow_hash_input flow_hash_input;\n \n-\t\t/* words 2:3 : rss indirection table */\n \t\tstruct ena_admin_feature_rss_ind_table ind_table;\n \n-\t\t/* words 2 : interrupt moderation configuration */\n \t\tstruct ena_admin_feature_intr_moder_desc intr_moderation;\n+\n+\t\tstruct ena_admin_ena_hw_hints hw_hints;\n \t} u;\n };\n \n-/* ENA Set Feature command */\n struct ena_admin_set_feat_cmd {\n-\t/* words 0 :  */\n \tstruct ena_admin_aq_common_desc aq_common_descriptor;\n \n-\t/* words 1:3 : points to control buffer (direct or indirect,\n-\t * chained if needed)\n-\t */\n \tstruct ena_admin_ctrl_buff_info control_buffer;\n \n-\t/* words 4 :  */\n \tstruct ena_admin_get_set_feature_common_desc feat_common;\n \n-\t/* words 5:15 :  */\n \tunion {\n-\t\t/* raw words */\n \t\tuint32_t raw[11];\n \n-\t\t/* words 5 : mtu size */\n+\t\t/* mtu size */\n \t\tstruct ena_admin_set_feature_mtu_desc mtu;\n \n-\t\t/* words 5:7 : host attributes */\n+\t\t/* host attributes */\n \t\tstruct ena_admin_set_feature_host_attr_desc host_attr;\n \n-\t\t/* words 5:6 : AENQ configuration */\n+\t\t/* AENQ configuration */\n \t\tstruct ena_admin_feature_aenq_desc aenq;\n \n-\t\t/* words 5:7 : rss flow hash function */\n+\t\t/* rss flow hash function */\n \t\tstruct ena_admin_feature_rss_flow_hash_function flow_hash_func;\n \n-\t\t/* words 5 : rss flow hash input */\n+\t\t/* rss flow hash input */\n \t\tstruct ena_admin_feature_rss_flow_hash_input flow_hash_input;\n \n-\t\t/* words 5:6 : rss indirection table */\n+\t\t/* rss indirection table */\n \t\tstruct ena_admin_feature_rss_ind_table ind_table;\n \t} u;\n };\n \n-/* ENA Set Feature command response */\n struct ena_admin_set_feat_resp {\n-\t/* words 0:1 :  */\n \tstruct ena_admin_acq_common_desc acq_common_desc;\n \n-\t/* words 2:15 :  */\n \tunion {\n-\t\t/* raw words */\n \t\tuint32_t raw[14];\n \t} u;\n };\n \n-/* ENA Asynchronous Event Notification Queue descriptor.  */\n struct ena_admin_aenq_common_desc {\n-\t/* word 0 : */\n \tuint16_t group;\n \n \tuint16_t syndrom;\n \n-\t/* word 1 : */\n \t/* 0 : phase */\n \tuint8_t flags;\n \n \tuint8_t reserved1[3];\n \n-\t/* word 2 : Timestamp LSB */\n \tuint32_t timestamp_low;\n \n-\t/* word 3 : Timestamp MSB */\n \tuint32_t timestamp_high;\n };\n \n /* asynchronous event notification groups */\n enum ena_admin_aenq_group {\n-\t/* Link State Change */\n-\tENA_ADMIN_LINK_CHANGE = 0,\n+\tENA_ADMIN_LINK_CHANGE\t\t= 0,\n \n-\tENA_ADMIN_FATAL_ERROR = 1,\n+\tENA_ADMIN_FATAL_ERROR\t\t= 1,\n \n-\tENA_ADMIN_WARNING = 2,\n+\tENA_ADMIN_WARNING\t\t= 2,\n \n-\tENA_ADMIN_NOTIFICATION = 3,\n+\tENA_ADMIN_NOTIFICATION\t\t= 3,\n \n-\tENA_ADMIN_KEEP_ALIVE = 4,\n+\tENA_ADMIN_KEEP_ALIVE\t\t= 4,\n \n-\tENA_ADMIN_AENQ_GROUPS_NUM = 5,\n+\tENA_ADMIN_AENQ_GROUPS_NUM\t= 5,\n };\n \n-/* syndorm of AENQ notification group */\n enum ena_admin_aenq_notification_syndrom {\n-\tENA_ADMIN_SUSPEND = 0,\n+\tENA_ADMIN_SUSPEND\t= 0,\n+\n+\tENA_ADMIN_RESUME\t= 1,\n \n-\tENA_ADMIN_RESUME = 1,\n+\tENA_ADMIN_UPDATE_HINTS\t= 2,\n };\n \n-/* ENA Asynchronous Event Notification generic descriptor.  */\n struct ena_admin_aenq_entry {\n-\t/* words 0:3 :  */\n \tstruct ena_admin_aenq_common_desc aenq_common_desc;\n \n \t/* command specific inline data */\n \tuint32_t inline_data_w4[12];\n };\n \n-/* ENA Asynchronous Event Notification Queue Link Change descriptor.  */\n struct ena_admin_aenq_link_change_desc {\n-\t/* words 0:3 :  */\n \tstruct ena_admin_aenq_common_desc aenq_common_desc;\n \n-\t/* word 4 : */\n \t/* 0 : link_status */\n \tuint32_t flags;\n };\n \n-/* ENA MMIO Readless response interface */\n+struct ena_admin_aenq_keep_alive_desc {\n+\tstruct ena_admin_aenq_common_desc aenq_common_desc;\n+\n+\tuint32_t rx_drops_low;\n+\n+\tuint32_t rx_drops_high;\n+};\n+\n struct ena_admin_ena_mmio_req_read_less_resp {\n-\t/* word 0 : */\n-\t/* request id */\n \tuint16_t req_id;\n \n-\t/* register offset */\n \tuint16_t reg_off;\n \n-\t/* word 1 : value is valid when poll is cleared */\n+\t/* value is valid when poll is cleared */\n \tuint32_t reg_val;\n };\n \n@@ -1220,8 +992,7 @@ struct ena_admin_ena_mmio_req_read_less_resp {\n \n /* feature_rss_flow_hash_function */\n #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)\n-#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK \\\n-\tGENMASK(7, 0)\n+#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)\n \n /* feature_rss_flow_hash_input */\n #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1\n@@ -1247,653 +1018,392 @@ struct ena_admin_ena_mmio_req_read_less_resp {\n #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)\n \n #if !defined(ENA_DEFS_LINUX_MAINLINE)\n-static inline uint16_t\n-get_ena_admin_aq_common_desc_command_id(\n-\t\tconst struct ena_admin_aq_common_desc *p)\n+static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)\n {\n \treturn p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;\n }\n \n-static inline void\n-set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p,\n-\t\t\t\t\tuint16_t val)\n+static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)\n {\n \tp->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)\n+static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)\n {\n \treturn p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;\n }\n \n-static inline void\n-set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p,\n-\t\t\t\t   uint8_t val)\n+static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)\n {\n \tp->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_common_desc_ctrl_data(\n-\t\tconst struct ena_admin_aq_common_desc *p)\n+static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)\n {\n-\treturn (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >>\n-\t       ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;\n+\treturn (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p,\n-\t\t\t\t       uint8_t val)\n+static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)\n {\n-\tp->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT)\n-\t\t     & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;\n+\tp->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_common_desc_ctrl_data_indirect(\n-\t\tconst struct ena_admin_aq_common_desc *p)\n+static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)\n {\n-\treturn (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK)\n-\t\t>> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;\n+\treturn (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_aq_common_desc_ctrl_data_indirect(\n-\t\tstruct ena_admin_aq_common_desc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)\n {\n-\tp->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT)\n-\t\t     & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;\n+\tp->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)\n+static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)\n {\n-\treturn (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK)\n-\t\t>> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;\n+\treturn (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)\n+static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)\n {\n-\tp->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &\n-\t\t\t  ENA_ADMIN_SQ_SQ_DIRECTION_MASK;\n+\tp->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;\n }\n \n-static inline uint16_t\n-get_ena_admin_acq_common_desc_command_id(\n-\t\tconst struct ena_admin_acq_common_desc *p)\n+static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)\n {\n \treturn p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;\n }\n \n-static inline void\n-set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p,\n-\t\t\t\t\t uint16_t val)\n+static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)\n {\n \tp->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)\n+static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)\n {\n \treturn p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;\n }\n \n-static inline void\n-set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p,\n-\t\t\t\t    uint8_t val)\n+static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)\n {\n \tp->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_create_sq_cmd_sq_direction(\n-\t\tconst struct ena_admin_aq_create_sq_cmd *p)\n+static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)\n {\n-\treturn (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK)\n-\t\t>> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;\n+\treturn (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_aq_create_sq_cmd_sq_direction(\n-\t\tstruct ena_admin_aq_create_sq_cmd *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)\n {\n-\tp->sq_identity |= (val <<\n-\t\t\t   ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT)\n-\t\t\t  & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;\n+\tp->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_create_sq_cmd_placement_policy(\n-\t\tconst struct ena_admin_aq_create_sq_cmd *p)\n+static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)\n {\n \treturn p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;\n }\n \n-static inline void\n-set_ena_admin_aq_create_sq_cmd_placement_policy(\n-\t\tstruct ena_admin_aq_create_sq_cmd *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)\n {\n \tp->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_create_sq_cmd_completion_policy(\n-\t\tconst struct ena_admin_aq_create_sq_cmd *p)\n+static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)\n {\n-\treturn (p->sq_caps_2\n-\t\t& ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK)\n-\t\t>> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;\n+\treturn (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_aq_create_sq_cmd_completion_policy(\n-\t\tstruct ena_admin_aq_create_sq_cmd *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)\n {\n-\tp->sq_caps_2 |=\n-\t\t(val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT)\n-\t\t& ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;\n+\tp->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(\n-\t\tconst struct ena_admin_aq_create_sq_cmd *p)\n+static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)\n {\n-\treturn p->sq_caps_3 &\n-\t\tENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;\n+\treturn p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;\n }\n \n-static inline void\n-set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(\n-\t\tstruct ena_admin_aq_create_sq_cmd *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)\n {\n-\tp->sq_caps_3 |= val &\n-\t\tENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;\n+\tp->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(\n-\t\tconst struct ena_admin_aq_create_cq_cmd *p)\n+static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)\n {\n-\treturn (p->cq_caps_1 &\n-\t\tENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK)\n-\t\t>> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;\n+\treturn (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(\n-\t\tstruct ena_admin_aq_create_cq_cmd *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)\n {\n-\tp->cq_caps_1 |=\n-\t(val <<\tENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT)\n-\t& ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;\n+\tp->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(\n-\t\tconst struct ena_admin_aq_create_cq_cmd *p)\n+static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)\n {\n-\treturn p->cq_caps_2\n-\t       & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;\n+\treturn p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;\n }\n \n-static inline void\n-set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(\n-\t\tstruct ena_admin_aq_create_cq_cmd *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)\n {\n-\tp->cq_caps_2 |=\n-\t\tval & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;\n+\tp->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_get_set_feature_common_desc_select(\n-\t\tconst struct ena_admin_get_set_feature_common_desc *p)\n+static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)\n {\n \treturn p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;\n }\n \n-static inline void\n-set_ena_admin_get_set_feature_common_desc_select(\n-\t\tstruct ena_admin_get_set_feature_common_desc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)\n {\n \tp->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_get_feature_link_desc_autoneg(\n-\t\tconst struct ena_admin_get_feature_link_desc *p)\n+static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)\n {\n \treturn p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;\n }\n \n-static inline void\n-set_ena_admin_get_feature_link_desc_autoneg(\n-\t\tstruct ena_admin_get_feature_link_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)\n {\n \tp->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_get_feature_link_desc_duplex(\n-\t\tconst struct ena_admin_get_feature_link_desc *p)\n+static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)\n {\n-\treturn (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK)\n-\t\t>> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;\n+\treturn (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_get_feature_link_desc_duplex(\n-\t\tstruct ena_admin_get_feature_link_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)\n {\n-\tp->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT)\n-\t\t\t& ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;\n+\tp->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)\n {\n \treturn p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n \tp->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->tx &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;\n+\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->tx |= (val <<\n-\t\t  ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;\n+\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->tx &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;\n+\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->tx |= (val <<\n-\t\t  ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;\n+\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->tx &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;\n+\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->tx |= (val <<\n-\t\t  ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;\n+\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->tx &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;\n+\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->tx |= (val <<\n-\t\t  ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;\n+\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_tso_ipv4(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;\n+\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_tso_ipv4(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;\n+\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_tso_ipv6(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;\n+\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_tso_ipv6(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;\n+\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_tso_ecn(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;\n+\treturn (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_tso_ecn(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;\n+\tp->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn p->rx_supported &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;\n+\treturn p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->rx_supported |=\n-\t\tval & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;\n+\tp->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->rx_supported &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;\n+\treturn (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->rx_supported |=\n-\t\t(val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT)\n-\t\t& ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;\n+\tp->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->rx_supported &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;\n+\treturn (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->rx_supported |=\n-\t\t(val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT)\n-\t\t& ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;\n+\tp->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_offload_desc_RX_hash(\n-\t\tconst struct ena_admin_feature_offload_desc *p)\n+static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)\n {\n-\treturn (p->rx_supported &\n-\t\tENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;\n+\treturn (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_offload_desc_RX_hash(\n-\t\tstruct ena_admin_feature_offload_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)\n {\n-\tp->rx_supported |=\n-\t\t(val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT)\n-\t\t& ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;\n+\tp->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_rss_flow_hash_function_funcs(\n-\t\tconst struct ena_admin_feature_rss_flow_hash_function *p)\n+static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)\n {\n-\treturn p->supported_func &\n-\t\tENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;\n+\treturn p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;\n }\n \n-static inline void\n-set_ena_admin_feature_rss_flow_hash_function_funcs(\n-\t\tstruct ena_admin_feature_rss_flow_hash_function *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)\n {\n-\tp->supported_func |=\n-\t\tval & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;\n+\tp->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_feature_rss_flow_hash_function_selected_func(\n-\t\tconst struct ena_admin_feature_rss_flow_hash_function *p)\n+static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)\n {\n-\treturn p->selected_func &\n-\t\tENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;\n+\treturn p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;\n }\n \n-static inline void\n-set_ena_admin_feature_rss_flow_hash_function_selected_func(\n-\t\tstruct ena_admin_feature_rss_flow_hash_function *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)\n {\n-\tp->selected_func |=\n-\t\tval &\n-\t\tENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;\n+\tp->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;\n }\n \n-static inline uint16_t\n-get_ena_admin_feature_rss_flow_hash_input_L3_sort(\n-\t\tconst struct ena_admin_feature_rss_flow_hash_input *p)\n+static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)\n {\n-\treturn (p->supported_input_sort &\n-\t\t\tENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;\n+\treturn (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_rss_flow_hash_input_L3_sort(\n-\t\tstruct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)\n+static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)\n {\n-\tp->supported_input_sort |=\n-\t\t(val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT)\n-\t\t& ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;\n+\tp->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;\n }\n \n-static inline uint16_t\n-get_ena_admin_feature_rss_flow_hash_input_L4_sort(\n-\t\tconst struct ena_admin_feature_rss_flow_hash_input *p)\n+static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)\n {\n-\treturn (p->supported_input_sort &\n-\t\tENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;\n+\treturn (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_rss_flow_hash_input_L4_sort(\n-\t\tstruct ena_admin_feature_rss_flow_hash_input *p,\n-\t\tuint16_t val)\n+static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)\n {\n-\tp->supported_input_sort |=\n-\t\t(val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT)\n-\t\t & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;\n+\tp->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;\n }\n \n-static inline uint16_t\n-get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(\n-\t\tconst struct ena_admin_feature_rss_flow_hash_input *p)\n+static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)\n {\n-\treturn (p->enabled_input_sort &\n-\t\tENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;\n+\treturn (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(\n-\t\tstruct ena_admin_feature_rss_flow_hash_input *p,\n-\t\tuint16_t val)\n+static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)\n {\n-\tp->enabled_input_sort |=\n-\t\t(val <<\n-\t\t ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT)\n-\t\t& ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;\n+\tp->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;\n }\n \n-static inline uint16_t\n-get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(\n-\t\tconst struct ena_admin_feature_rss_flow_hash_input *p)\n+static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)\n {\n-\treturn (p->enabled_input_sort &\n-\t\tENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK)\n-\t\t>> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;\n+\treturn (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(\n-\t\tstruct ena_admin_feature_rss_flow_hash_input *p,\n-\t\tuint16_t val)\n+static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)\n {\n-\tp->enabled_input_sort |=\n-\t\t(val <<\n-\t\t ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT)\n-\t\t& ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;\n+\tp->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_host_info_major(const struct ena_admin_host_info *p)\n+static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)\n {\n \treturn p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;\n }\n \n-static inline void\n-set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)\n+static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)\n {\n \tp->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)\n+static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)\n {\n-\treturn (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK)\n-\t\t>> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;\n+\treturn (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)\n+static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)\n {\n-\tp->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT)\n-\t\t& ENA_ADMIN_HOST_INFO_MINOR_MASK;\n+\tp->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)\n+static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)\n {\n-\treturn (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK)\n-\t\t>> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;\n+\treturn (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;\n }\n \n-static inline void\n-set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)\n+static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)\n {\n-\tp->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT)\n-\t\t\t     & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;\n+\tp->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;\n }\n \n-static inline uint8_t\n-get_ena_admin_aenq_common_desc_phase(\n-\t\tconst struct ena_admin_aenq_common_desc *p)\n+static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)\n {\n \treturn p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;\n }\n \n-static inline void\n-set_ena_admin_aenq_common_desc_phase(\n-\t\tstruct ena_admin_aenq_common_desc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)\n {\n \tp->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;\n }\n \n-static inline uint32_t\n-get_ena_admin_aenq_link_change_desc_link_status(\n-\t\tconst struct ena_admin_aenq_link_change_desc *p)\n+static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)\n {\n \treturn p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;\n }\n \n-static inline void\n-set_ena_admin_aenq_link_change_desc_link_status(\n-\t\tstruct ena_admin_aenq_link_change_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)\n {\n \tp->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;\n }\ndiff --git a/drivers/net/ena/base/ena_defs/ena_common_defs.h b/drivers/net/ena/base/ena_defs/ena_common_defs.h\nindex 95e0f3897..072e6c1f1 100644\n--- a/drivers/net/ena/base/ena_defs/ena_common_defs.h\n+++ b/drivers/net/ena/base/ena_defs/ena_common_defs.h\n@@ -34,17 +34,13 @@\n #ifndef _ENA_COMMON_H_\n #define _ENA_COMMON_H_\n \n-/* spec version */\n-#define ENA_COMMON_SPEC_VERSION_MAJOR\t0 /* spec version major */\n-#define ENA_COMMON_SPEC_VERSION_MINOR\t10 /* spec version minor */\n+#define ENA_COMMON_SPEC_VERSION_MAJOR\t0 /*  */\n+#define ENA_COMMON_SPEC_VERSION_MINOR\t10 /*  */\n \n /* ENA operates with 48-bit memory addresses. ena_mem_addr_t */\n struct ena_common_mem_addr {\n-\t/* word 0 : low 32 bit of the memory address */\n \tuint32_t mem_addr_low;\n \n-\t/* word 1 : */\n-\t/* high 16 bits of the memory address */\n \tuint16_t mem_addr_high;\n \n \t/* MBZ */\ndiff --git a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h\nindex 6bc3d6a7c..4cf0b205b 100644\n--- a/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h\n+++ b/drivers/net/ena/base/ena_defs/ena_eth_io_defs.h\n@@ -34,35 +34,30 @@\n #ifndef _ENA_ETH_IO_H_\n #define _ENA_ETH_IO_H_\n \n-/* Layer 3 protocol index */\n enum ena_eth_io_l3_proto_index {\n-\tENA_ETH_IO_L3_PROTO_UNKNOWN = 0,\n+\tENA_ETH_IO_L3_PROTO_UNKNOWN\t= 0,\n \n-\tENA_ETH_IO_L3_PROTO_IPV4 = 8,\n+\tENA_ETH_IO_L3_PROTO_IPV4\t= 8,\n \n-\tENA_ETH_IO_L3_PROTO_IPV6 = 11,\n+\tENA_ETH_IO_L3_PROTO_IPV6\t= 11,\n \n-\tENA_ETH_IO_L3_PROTO_FCOE = 21,\n+\tENA_ETH_IO_L3_PROTO_FCOE\t= 21,\n \n-\tENA_ETH_IO_L3_PROTO_ROCE = 22,\n+\tENA_ETH_IO_L3_PROTO_ROCE\t= 22,\n };\n \n-/* Layer 4 protocol index */\n enum ena_eth_io_l4_proto_index {\n-\tENA_ETH_IO_L4_PROTO_UNKNOWN = 0,\n+\tENA_ETH_IO_L4_PROTO_UNKNOWN\t\t= 0,\n \n-\tENA_ETH_IO_L4_PROTO_TCP = 12,\n+\tENA_ETH_IO_L4_PROTO_TCP\t\t\t= 12,\n \n-\tENA_ETH_IO_L4_PROTO_UDP = 13,\n+\tENA_ETH_IO_L4_PROTO_UDP\t\t\t= 13,\n \n-\tENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,\n+\tENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE\t= 23,\n };\n \n-/* ENA IO Queue Tx descriptor */\n struct ena_eth_io_tx_desc {\n-\t/* word 0 : */\n-\t/* length, request id and control flags\n-\t * 15:0 : length - Buffer length in bytes, must\n+\t/* 15:0 : length - Buffer length in bytes, must\n \t *    include any packet trailers that the ENA supposed\n \t *    to update like End-to-End CRC, Authentication GMAC\n \t *    etc. This length must not include the\n@@ -85,9 +80,7 @@ struct ena_eth_io_tx_desc {\n \t */\n \tuint32_t len_ctrl;\n \n-\t/* word 1 : */\n-\t/* ethernet control\n-\t * 3:0 : l3_proto_idx - L3 protocol. This field\n+\t/* 3:0 : l3_proto_idx - L3 protocol. This field\n \t *    required when l3_csum_en,l3_csum or tso_en are set.\n \t * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and\n \t *    DF flags of the IPv4 header is 0. Otherwise must\n@@ -119,10 +112,8 @@ struct ena_eth_io_tx_desc {\n \t */\n \tuint32_t meta_ctrl;\n \n-\t/* word 2 : Buffer address bits[31:0] */\n \tuint32_t buff_addr_lo;\n \n-\t/* word 3 : */\n \t/* address high and header size\n \t * 15:0 : addr_hi - Buffer Pointer[47:32]\n \t * 23:16 : reserved16_w2\n@@ -141,20 +132,16 @@ struct ena_eth_io_tx_desc {\n \tuint32_t buff_addr_hi_hdr_sz;\n };\n \n-/* ENA IO Queue Tx Meta descriptor */\n struct ena_eth_io_tx_meta_desc {\n-\t/* word 0 : */\n-\t/* length, request id and control flags\n-\t * 9:0 : req_id_lo - Request ID[9:0]\n+\t/* 9:0 : req_id_lo - Request ID[9:0]\n \t * 11:10 : reserved10 - MBZ\n \t * 12 : reserved12 - MBZ\n \t * 13 : reserved13 - MBZ\n \t * 14 : ext_valid - if set, offset fields in Word2\n-\t *    are valid Also MSS High in Word 0 and Outer L3\n-\t *    Offset High in WORD 0 and bits [31:24] in Word 3\n-\t * 15 : word3_valid - If set Crypto Info[23:0] of\n-\t *    Word 3 is valid\n-\t * 19:16 : mss_hi_ptp\n+\t *    are valid Also MSS High in Word 0 and bits [31:24]\n+\t *    in Word 3\n+\t * 15 : reserved15\n+\t * 19:16 : mss_hi\n \t * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:\n \t *    Extended Metadata Descriptor\n \t * 21 : meta_store - Store extended metadata in queue\n@@ -175,19 +162,13 @@ struct ena_eth_io_tx_meta_desc {\n \t */\n \tuint32_t len_ctrl;\n \n-\t/* word 1 : */\n-\t/* word 1\n-\t * 5:0 : req_id_hi\n+\t/* 5:0 : req_id_hi\n \t * 31:6 : reserved6 - MBZ\n \t */\n \tuint32_t word1;\n \n-\t/* word 2 : */\n-\t/* word 2\n-\t * 7:0 : l3_hdr_len - the header length L3 IP header.\n-\t * 15:8 : l3_hdr_off - the offset of the first byte\n-\t *    in the L3 header from the beginning of the to-be\n-\t *    transmitted packet.\n+\t/* 7:0 : l3_hdr_len\n+\t * 15:8 : l3_hdr_off\n \t * 21:16 : l4_hdr_len_in_words - counts the L4 header\n \t *    length in words. there is an explicit assumption\n \t *    that L4 header appears right after L3 header and\n@@ -196,13 +177,10 @@ struct ena_eth_io_tx_meta_desc {\n \t */\n \tuint32_t word2;\n \n-\t/* word 3 : */\n \tuint32_t reserved;\n };\n \n-/* ENA IO Queue Tx completions descriptor */\n struct ena_eth_io_tx_cdesc {\n-\t/* word 0 : */\n \t/* Request ID[15:0] */\n \tuint16_t req_id;\n \n@@ -214,24 +192,19 @@ struct ena_eth_io_tx_cdesc {\n \t */\n \tuint8_t flags;\n \n-\t/* word 1 : */\n \tuint16_t sub_qid;\n \n-\t/* indicates location of submission queue head */\n \tuint16_t sq_head_idx;\n };\n \n-/* ENA IO Queue Rx descriptor */\n struct ena_eth_io_rx_desc {\n-\t/* word 0 : */\n \t/* In bytes. 0 means 64KB */\n \tuint16_t length;\n \n \t/* MBZ */\n \tuint8_t reserved2;\n \n-\t/* control flags\n-\t * 0 : phase\n+\t/* 0 : phase\n \t * 1 : reserved1 - MBZ\n \t * 2 : first - Indicates first descriptor in\n \t *    transaction\n@@ -242,32 +215,27 @@ struct ena_eth_io_rx_desc {\n \t */\n \tuint8_t ctrl;\n \n-\t/* word 1 : */\n \tuint16_t req_id;\n \n \t/* MBZ */\n \tuint16_t reserved6;\n \n-\t/* word 2 : Buffer address bits[31:0] */\n \tuint32_t buff_addr_lo;\n \n-\t/* word 3 : */\n-\t/* Buffer Address bits[47:16] */\n \tuint16_t buff_addr_hi;\n \n \t/* MBZ */\n \tuint16_t reserved16_w3;\n };\n \n-/* ENA IO Queue Rx Completion Base Descriptor (4-word format). Note: all\n- * ethernet parsing information are valid only when last=1\n+/* 4-word format Note: all ethernet parsing information are valid only when\n+ * last=1\n  */\n struct ena_eth_io_rx_cdesc_base {\n-\t/* word 0 : */\n-\t/* 4:0 : l3_proto_idx - L3 protocol index\n-\t * 6:5 : src_vlan_cnt - Source VLAN count\n+\t/* 4:0 : l3_proto_idx\n+\t * 6:5 : src_vlan_cnt\n \t * 7 : reserved7 - MBZ\n-\t * 12:8 : l4_proto_idx - L4 protocol index\n+\t * 12:8 : l4_proto_idx\n \t * 13 : l3_csum_err - when set, either the L3\n \t *    checksum error detected, or, the controller didn't\n \t *    validate the checksum. This bit is valid only when\n@@ -292,56 +260,43 @@ struct ena_eth_io_rx_cdesc_base {\n \t */\n \tuint32_t status;\n \n-\t/* word 1 : */\n \tuint16_t length;\n \n \tuint16_t req_id;\n \n-\t/* word 2 : 32-bit hash result */\n+\t/* 32-bit hash result */\n \tuint32_t hash;\n \n-\t/* word 3 : */\n-\t/* submission queue number */\n \tuint16_t sub_qid;\n \n \tuint16_t reserved;\n };\n \n-/* ENA IO Queue Rx Completion Descriptor (8-word format) */\n+/* 8-word format */\n struct ena_eth_io_rx_cdesc_ext {\n-\t/* words 0:3 : Rx Completion Extended */\n \tstruct ena_eth_io_rx_cdesc_base base;\n \n-\t/* word 4 : Completed Buffer address bits[31:0] */\n \tuint32_t buff_addr_lo;\n \n-\t/* word 5 : */\n-\t/* the buffer address used bits[47:32] */\n \tuint16_t buff_addr_hi;\n \n \tuint16_t reserved16;\n \n-\t/* word 6 : Reserved */\n \tuint32_t reserved_w6;\n \n-\t/* word 7 : Reserved */\n \tuint32_t reserved_w7;\n };\n \n-/* ENA Interrupt Unmask Register */\n struct ena_eth_io_intr_reg {\n-\t/* word 0 : */\n-\t/* 14:0 : rx_intr_delay - rx interrupt delay value\n-\t * 29:15 : tx_intr_delay - tx interrupt delay value\n-\t * 30 : intr_unmask - if set, unmasks interrupt\n+\t/* 14:0 : rx_intr_delay\n+\t * 29:15 : tx_intr_delay\n+\t * 30 : intr_unmask\n \t * 31 : reserved\n \t */\n \tuint32_t intr_control;\n };\n \n-/* ENA NUMA Node configuration register */\n struct ena_eth_io_numa_node_cfg_reg {\n-\t/* word 0 : */\n \t/* 7:0 : numa\n \t * 30:8 : reserved\n \t * 31 : enabled\n@@ -388,10 +343,8 @@ struct ena_eth_io_numa_node_cfg_reg {\n #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)\n #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14\n #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)\n-#define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT 15\n-#define ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK BIT(15)\n-#define ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT 16\n-#define ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK GENMASK(19, 16)\n+#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16\n+#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)\n #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20\n #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)\n #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21\n@@ -463,803 +416,544 @@ struct ena_eth_io_numa_node_cfg_reg {\n #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)\n \n #if !defined(ENA_DEFS_LINUX_MAINLINE)\n-static inline uint32_t get_ena_eth_io_tx_desc_length(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p)\n {\n \treturn p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;\n }\n \n-static inline void set_ena_eth_io_tx_desc_length(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n \tp->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_req_id_hi(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_meta_desc(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_META_DESC_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_phase(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_PHASE_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_phase(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_PHASE_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_first(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_FIRST_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_first(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_FIRST_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_last(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_LAST_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_last(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_LAST_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_LAST_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_comp_req(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_comp_req(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p)\n {\n \treturn p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;\n }\n \n-static inline void set_ena_eth_io_tx_desc_l3_proto_idx(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n \tp->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_DF(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_DF_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_DF(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_DF_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_DF_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_tso_en(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_tso_en(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_TSO_EN_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_l4_proto_idx(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_l3_csum_en(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_l4_csum_en(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_l4_csum_partial(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT;\n+\treturn (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_req_id_lo(\n-\t\tstruct ena_eth_io_tx_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;\n+\tp->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p)\n {\n \treturn p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;\n }\n \n-static inline void set_ena_eth_io_tx_desc_addr_hi(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n \tp->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_desc_header_length(\n-\t\tconst struct ena_eth_io_tx_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p)\n {\n-\treturn (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK)\n-\t\t>> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT;\n+\treturn (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_desc_header_length(\n-\t\tstruct ena_eth_io_tx_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val)\n {\n-\tp->buff_addr_hi_hdr_sz |=\n-\t\t(val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT)\n-\t\t& ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;\n+\tp->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p)\n {\n \treturn p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(\n-\t\tstruct ena_eth_io_tx_meta_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n \tp->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n-{\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT;\n-}\n-\n-static inline void set_ena_eth_io_tx_meta_desc_ext_valid(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n-{\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;\n-}\n-\n-static inline uint32_t get_ena_eth_io_tx_meta_desc_word3_valid(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_word3_valid(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_WORD3_VALID_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_WORD3_VALID_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi_ptp(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_mss_hi_ptp(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_meta_store(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_meta_desc(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_phase(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_PHASE_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_first(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_first(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_FIRST_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_last(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_last(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_LAST_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT;\n+\treturn (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_comp_req(\n-\t\tstruct ena_eth_io_tx_meta_desc *p, uint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;\n+\tp->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p)\n {\n \treturn p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(\n-\t\tstruct ena_eth_io_tx_meta_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n \tp->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p)\n {\n \treturn p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(\n-\t\tstruct ena_eth_io_tx_meta_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n \tp->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT;\n+\treturn (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(\n-\t\tstruct ena_eth_io_tx_meta_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->word2 |=\n-\t\t(val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;\n+\tp->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT;\n+\treturn (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(\n-\t\tstruct ena_eth_io_tx_meta_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->word2 |=\n-\t\t(val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;\n+\tp->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(\n-\t\tconst struct ena_eth_io_tx_meta_desc *p)\n+static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p)\n {\n-\treturn (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK)\n-\t\t>> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT;\n+\treturn (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT;\n }\n \n-static inline void set_ena_eth_io_tx_meta_desc_mss_lo(\n-\t\tstruct ena_eth_io_tx_meta_desc *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)\n {\n-\tp->word2 |=\n-\t\t(val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT)\n-\t\t& ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;\n+\tp->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;\n }\n \n-static inline uint8_t get_ena_eth_io_tx_cdesc_phase(\n-\t\tconst struct ena_eth_io_tx_cdesc *p)\n+static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p)\n {\n \treturn p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;\n }\n \n-static inline void set_ena_eth_io_tx_cdesc_phase(\n-\t\tstruct ena_eth_io_tx_cdesc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val)\n {\n \tp->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;\n }\n \n-static inline uint8_t get_ena_eth_io_rx_desc_phase(\n-\t\tconst struct ena_eth_io_rx_desc *p)\n+static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p)\n {\n \treturn p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;\n }\n \n-static inline void set_ena_eth_io_rx_desc_phase(\n-\t\tstruct ena_eth_io_rx_desc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val)\n {\n \tp->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK;\n }\n \n-static inline uint8_t get_ena_eth_io_rx_desc_first(\n-\t\tconst struct ena_eth_io_rx_desc *p)\n+static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p)\n {\n-\treturn (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK)\n-\t\t>> ENA_ETH_IO_RX_DESC_FIRST_SHIFT;\n+\treturn (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_desc_first(\n-\t\tstruct ena_eth_io_rx_desc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val)\n {\n-\tp->ctrl |=\n-\t\t(val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT)\n-\t\t& ENA_ETH_IO_RX_DESC_FIRST_MASK;\n+\tp->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK;\n }\n \n-static inline uint8_t get_ena_eth_io_rx_desc_last(\n-\t\tconst struct ena_eth_io_rx_desc *p)\n+static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p)\n {\n-\treturn (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK)\n-\t\t>> ENA_ETH_IO_RX_DESC_LAST_SHIFT;\n+\treturn (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_desc_last(\n-\t\tstruct ena_eth_io_rx_desc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val)\n {\n-\tp->ctrl |=\n-\t\t(val << ENA_ETH_IO_RX_DESC_LAST_SHIFT)\n-\t\t& ENA_ETH_IO_RX_DESC_LAST_MASK;\n+\tp->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK;\n }\n \n-static inline uint8_t get_ena_eth_io_rx_desc_comp_req(\n-\t\tconst struct ena_eth_io_rx_desc *p)\n+static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p)\n {\n-\treturn (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK)\n-\t\t>> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT;\n+\treturn (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_desc_comp_req(\n-\t\tstruct ena_eth_io_rx_desc *p,\n-\t\tuint8_t val)\n+static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val)\n {\n-\tp->ctrl |=\n-\t\t(val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT)\n-\t\t& ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;\n+\tp->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)\n {\n \treturn p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n \tp->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p,\n-\t\tuint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |=\n-\t\t(val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_phase(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_first(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_last(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(\n-\t\tconst struct ena_eth_io_rx_cdesc_base *p)\n+static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p)\n {\n-\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK)\n-\t\t>> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT;\n+\treturn (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT;\n }\n \n-static inline void set_ena_eth_io_rx_cdesc_base_buffer(\n-\t\tstruct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n+static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)\n {\n-\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT)\n-\t\t& ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;\n+\tp->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(\n-\t\tconst struct ena_eth_io_intr_reg *p)\n+static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p)\n {\n \treturn p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;\n }\n \n-static inline void set_ena_eth_io_intr_reg_rx_intr_delay(\n-\t\tstruct ena_eth_io_intr_reg *p, uint32_t val)\n+static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)\n {\n \tp->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(\n-\t\tconst struct ena_eth_io_intr_reg *p)\n+static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p)\n {\n-\treturn (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK)\n-\t\t>> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT;\n+\treturn (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT;\n }\n \n-static inline void set_ena_eth_io_intr_reg_tx_intr_delay(\n-\t\tstruct ena_eth_io_intr_reg *p, uint32_t val)\n+static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)\n {\n-\tp->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)\n-\t\t& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;\n+\tp->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(\n-\t\tconst struct ena_eth_io_intr_reg *p)\n+static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p)\n {\n-\treturn (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK)\n-\t\t>> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT;\n+\treturn (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT;\n }\n \n-static inline void set_ena_eth_io_intr_reg_intr_unmask(\n-\t\tstruct ena_eth_io_intr_reg *p, uint32_t val)\n+static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val)\n {\n-\tp->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT)\n-\t\t& ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;\n+\tp->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(\n-\t\tconst struct ena_eth_io_numa_node_cfg_reg *p)\n+static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p)\n {\n \treturn p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;\n }\n \n-static inline void set_ena_eth_io_numa_node_cfg_reg_numa(\n-\t\tstruct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)\n+static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)\n {\n \tp->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;\n }\n \n-static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(\n-\t\tconst struct ena_eth_io_numa_node_cfg_reg *p)\n+static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p)\n {\n-\treturn (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK)\n-\t\t>> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;\n+\treturn (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;\n }\n \n-static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(\n-\t\tstruct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)\n+static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)\n {\n-\tp->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT)\n-\t\t& ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;\n+\tp->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;\n }\n \n #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */\ndiff --git a/drivers/net/ena/base/ena_defs/ena_gen_info.h b/drivers/net/ena/base/ena_defs/ena_gen_info.h\nindex 3d2520963..e87bcfd88 100644\n--- a/drivers/net/ena/base/ena_defs/ena_gen_info.h\n+++ b/drivers/net/ena/base/ena_defs/ena_gen_info.h\n@@ -31,5 +31,5 @@\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n \n-#define\tENA_GEN_DATE\t\"Sun Jun  5 10:24:39 IDT 2016\"\n-#define\tENA_GEN_COMMIT\t\"17146ed\"\n+#define\tENA_GEN_DATE\t\"Sun Oct 23 12:27:32 IDT 2016\"\n+#define\tENA_GEN_COMMIT\t\"79d82fa\"\ndiff --git a/drivers/net/ena/base/ena_defs/ena_includes.h b/drivers/net/ena/base/ena_defs/ena_includes.h\nindex a86c876fe..30a920a8e 100644\n--- a/drivers/net/ena/base/ena_defs/ena_includes.h\n+++ b/drivers/net/ena/base/ena_defs/ena_includes.h\n@@ -35,5 +35,3 @@\n #include \"ena_regs_defs.h\"\n #include \"ena_admin_defs.h\"\n #include \"ena_eth_io_defs.h\"\n-#include \"ena_efa_admin_defs.h\"\n-#include \"ena_efa_io_defs.h\"\ndiff --git a/drivers/net/ena/base/ena_defs/ena_regs_defs.h b/drivers/net/ena/base/ena_defs/ena_regs_defs.h\nindex d02412781..b0870f254 100644\n--- a/drivers/net/ena/base/ena_defs/ena_regs_defs.h\n+++ b/drivers/net/ena/base/ena_defs/ena_regs_defs.h\n@@ -34,6 +34,38 @@\n #ifndef _ENA_REGS_H_\n #define _ENA_REGS_H_\n \n+enum ena_regs_reset_reason_types {\n+\tENA_REGS_RESET_NORMAL\t\t\t= 0,\n+\n+\tENA_REGS_RESET_KEEP_ALIVE_TO\t\t= 1,\n+\n+\tENA_REGS_RESET_ADMIN_TO\t\t\t= 2,\n+\n+\tENA_REGS_RESET_MISS_TX_CMPL\t\t= 3,\n+\n+\tENA_REGS_RESET_INV_RX_REQ_ID\t\t= 4,\n+\n+\tENA_REGS_RESET_INV_TX_REQ_ID\t\t= 5,\n+\n+\tENA_REGS_RESET_TOO_MANY_RX_DESCS\t= 6,\n+\n+\tENA_REGS_RESET_INIT_ERR\t\t\t= 7,\n+\n+\tENA_REGS_RESET_DRIVER_INVALID_STATE\t= 8,\n+\n+\tENA_REGS_RESET_OS_TRIGGER\t\t= 9,\n+\n+\tENA_REGS_RESET_OS_NETDEV_WD\t\t= 10,\n+\n+\tENA_REGS_RESET_SHUTDOWN\t\t\t= 11,\n+\n+\tENA_REGS_RESET_USER_TRIGGER\t\t= 12,\n+\n+\tENA_REGS_RESET_GENERIC\t\t\t= 13,\n+\n+\tENA_REGS_RESET_MISS_INTERRUPT\t\t= 14,\n+};\n+\n /* ena_registers offsets */\n #define ENA_REGS_VERSION_OFF\t\t0x0\n #define ENA_REGS_CONTROLLER_VERSION_OFF\t\t0x4\n@@ -80,6 +112,8 @@\n #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK\t\t0x3e\n #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT\t\t8\n #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK\t\t0xff00\n+#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT\t\t16\n+#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK\t\t0xf0000\n \n /* aq_caps register */\n #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK\t\t0xffff\n@@ -104,6 +138,8 @@\n #define ENA_REGS_DEV_CTL_QUIESCENT_MASK\t\t0x4\n #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT\t\t3\n #define ENA_REGS_DEV_CTL_IO_RESUME_MASK\t\t0x8\n+#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT\t\t28\n+#define ENA_REGS_DEV_CTL_RESET_REASON_MASK\t\t0xf0000000\n \n /* dev_sts register */\n #define ENA_REGS_DEV_STS_READY_MASK\t\t0x1\ndiff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c\nindex 290a5666f..4c4989a3f 100644\n--- a/drivers/net/ena/base/ena_eth_com.c\n+++ b/drivers/net/ena/base/ena_eth_com.c\n@@ -43,11 +43,10 @@ static inline struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(\n \thead_masked = io_cq->head & (io_cq->q_depth - 1);\n \texpected_phase = io_cq->phase;\n \n-\tcdesc = (struct ena_eth_io_rx_cdesc_base *)\n-\t\t((unsigned char *)io_cq->cdesc_addr.virt_addr\n+\tcdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr\n \t\t\t+ (head_masked * io_cq->cdesc_entry_size_in_bytes));\n \n-\tdesc_phase = (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>\n+\tdesc_phase = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>\n \t\t\tENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;\n \n \tif (desc_phase != expected_phase)\n@@ -74,7 +73,7 @@ static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)\n \n \toffset = tail_masked * io_sq->desc_entry_size;\n \n-\treturn (unsigned char *)io_sq->desc_addr.virt_addr + offset;\n+\treturn (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset);\n }\n \n static inline void ena_com_copy_curr_sq_desc_to_dev(struct ena_com_io_sq *io_sq)\n@@ -86,8 +85,8 @@ static inline void ena_com_copy_curr_sq_desc_to_dev(struct ena_com_io_sq *io_sq)\n \tif (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)\n \t\treturn;\n \n-\tmemcpy_toio((unsigned char *)io_sq->desc_addr.pbuf_dev_addr + offset,\n-\t\t    (unsigned char *)io_sq->desc_addr.virt_addr + offset,\n+\tmemcpy_toio(io_sq->desc_addr.pbuf_dev_addr + offset,\n+\t\t    io_sq->desc_addr.virt_addr + offset,\n \t\t    io_sq->desc_entry_size);\n }\n \n@@ -125,11 +124,11 @@ static inline struct ena_eth_io_rx_cdesc_base *\n {\n \tidx &= (io_cq->q_depth - 1);\n \treturn (struct ena_eth_io_rx_cdesc_base *)\n-\t\t((unsigned char *)io_cq->cdesc_addr.virt_addr +\n-\t\t\tidx * io_cq->cdesc_entry_size_in_bytes);\n+\t\t((uintptr_t)io_cq->cdesc_addr.virt_addr +\n+\t\tidx * io_cq->cdesc_entry_size_in_bytes);\n }\n \n-static inline int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,\n+static inline u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,\n \t\t\t\t\t   u16 *first_cdesc_idx)\n {\n \tstruct ena_eth_io_rx_cdesc_base *cdesc;\n@@ -143,7 +142,7 @@ static inline int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,\n \n \t\tena_com_cq_inc_head(io_cq);\n \t\tcount++;\n-\t\tlast = (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>\n+\t\tlast = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>\n \t\t\tENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;\n \t} while (!last);\n \n@@ -183,9 +182,8 @@ static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,\n \treturn false;\n }\n \n-static inline void ena_com_create_and_store_tx_meta_desc(\n-\tstruct ena_com_io_sq *io_sq,\n-\tstruct ena_com_tx_ctx *ena_tx_ctx)\n+static inline void ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,\n+\t\t\t\t\t\t\t struct ena_com_tx_ctx *ena_tx_ctx)\n {\n \tstruct ena_eth_io_tx_meta_desc *meta_desc = NULL;\n \tstruct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;\n@@ -203,8 +201,8 @@ static inline void ena_com_create_and_store_tx_meta_desc(\n \t\tENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;\n \t/* bits 10-13 of the mss */\n \tmeta_desc->len_ctrl |= ((ena_meta->mss >> 10) <<\n-\t\tENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT) &\n-\t\tENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK;\n+\t\tENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) &\n+\t\tENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;\n \n \t/* Extended meta desc */\n \tmeta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;\n@@ -237,11 +235,11 @@ static inline void ena_com_create_and_store_tx_meta_desc(\n static inline void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,\n \t\t\t\t\tstruct ena_eth_io_rx_cdesc_base *cdesc)\n {\n-\tena_rx_ctx->l3_proto = (enum ena_eth_io_l3_proto_index)(cdesc->status &\n-\t\tENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK);\n-\tena_rx_ctx->l4_proto = (enum ena_eth_io_l4_proto_index)\n-\t\t((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>\n-\t\tENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT);\n+\tena_rx_ctx->l3_proto = cdesc->status &\n+\t\tENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;\n+\tena_rx_ctx->l4_proto =\n+\t\t(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>\n+\t\tENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;\n \tena_rx_ctx->l3_csum_err =\n \t\t(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >>\n \t\tENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;\n@@ -280,8 +278,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,\n \tbool have_meta;\n \tu64 addr_hi;\n \n-\tENA_ASSERT(io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX,\n-\t\t   \"wrong Q type\");\n+\tENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX,\n+\t\t \"wrong Q type\");\n \n \t/* num_bufs +1 for potential meta desc */\n \tif (ena_com_sq_empty_space(io_sq) < (num_bufs + 1)) {\n@@ -410,8 +408,8 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,\n \tu16 nb_hw_desc;\n \tu16 i;\n \n-\tENA_ASSERT(io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_RX,\n-\t\t   \"wrong Q type\");\n+\tENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,\n+\t\t \"wrong Q type\");\n \n \tnb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);\n \tif (nb_hw_desc == 0) {\n@@ -455,8 +453,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,\n {\n \tstruct ena_eth_io_rx_desc *desc;\n \n-\tENA_ASSERT(io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_RX,\n-\t\t   \"wrong Q type\");\n+\tENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,\n+\t\t \"wrong Q type\");\n \n \tif (unlikely(ena_com_sq_empty_space(io_sq) == 0))\n \t\treturn ENA_COM_NO_SPACE;\n@@ -475,8 +473,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,\n \n \tdesc->buff_addr_lo = (u32)ena_buf->paddr;\n \tdesc->buff_addr_hi =\n-\t\t((ena_buf->paddr &\n-\t\t  GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);\n+\t\t((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);\n \n \tena_com_sq_update_tail(io_sq);\n \n@@ -493,20 +490,37 @@ int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id)\n \texpected_phase = io_cq->phase;\n \n \tcdesc = (struct ena_eth_io_tx_cdesc *)\n-\t\t((unsigned char *)io_cq->cdesc_addr.virt_addr\n-\t\t+ (masked_head * io_cq->cdesc_entry_size_in_bytes));\n+\t\t((uintptr_t)io_cq->cdesc_addr.virt_addr +\n+\t\t(masked_head * io_cq->cdesc_entry_size_in_bytes));\n \n \t/* When the current completion descriptor phase isn't the same as the\n \t * expected, it mean that the device still didn't update\n \t * this completion.\n \t */\n-\tcdesc_phase = cdesc->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;\n+\tcdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK;\n \tif (cdesc_phase != expected_phase)\n \t\treturn ENA_COM_TRY_AGAIN;\n \n+\tif (unlikely(cdesc->req_id >= io_cq->q_depth)) {\n+\t\tena_trc_err(\"Invalid req id %d\\n\", cdesc->req_id);\n+\t\treturn ENA_COM_INVAL;\n+\t}\n+\n \tena_com_cq_inc_head(io_cq);\n \n-\t*req_id = cdesc->req_id;\n+\t*req_id = READ_ONCE(cdesc->req_id);\n \n \treturn 0;\n }\n+\n+bool ena_com_cq_empty(struct ena_com_io_cq *io_cq)\n+{\n+\tstruct ena_eth_io_rx_cdesc_base *cdesc;\n+\n+\tcdesc = ena_com_get_next_rx_cdesc(io_cq);\n+\tif (cdesc)\n+\t\treturn false;\n+\telse\n+\t\treturn true;\n+}\n+\ndiff --git a/drivers/net/ena/base/ena_eth_com.h b/drivers/net/ena/base/ena_eth_com.h\nindex 71a880c0f..56ea4ae64 100644\n--- a/drivers/net/ena/base/ena_eth_com.h\n+++ b/drivers/net/ena/base/ena_eth_com.h\n@@ -92,10 +92,12 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,\n \n int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);\n \n+bool ena_com_cq_empty(struct ena_com_io_cq *io_cq);\n+\n static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,\n \t\t\t\t       struct ena_eth_io_intr_reg *intr_reg)\n {\n-\tENA_REG_WRITE32(intr_reg->intr_control, io_cq->unmask_reg);\n+\tENA_REG_WRITE32(io_cq->bus, intr_reg->intr_control, io_cq->unmask_reg);\n }\n \n static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq)\n@@ -118,7 +120,7 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)\n \tena_trc_dbg(\"write submission queue doorbell for queue: %d tail: %d\\n\",\n \t\t    io_sq->qid, tail);\n \n-\tENA_REG_WRITE32(tail, io_sq->db_addr);\n+\tENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);\n \n \treturn 0;\n }\n@@ -135,7 +137,7 @@ static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)\n \tif (io_cq->cq_head_db_reg && need_update) {\n \t\tena_trc_dbg(\"Write completion queue doorbell for queue %d: head: %d\\n\",\n \t\t\t    io_cq->qid, head);\n-\t\tENA_REG_WRITE32(head, io_cq->cq_head_db_reg);\n+\t\tENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);\n \t\tio_cq->last_head_update = head;\n \t}\n \n@@ -153,7 +155,7 @@ static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,\n \tnuma_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)\n \t\t| ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;\n \n-\tENA_REG_WRITE32(numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);\n+\tENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);\n }\n \n static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)\ndiff --git a/drivers/net/ena/base/ena_plat.h b/drivers/net/ena/base/ena_plat.h\nindex b5b645456..278175f39 100644\n--- a/drivers/net/ena/base/ena_plat.h\n+++ b/drivers/net/ena/base/ena_plat.h\n@@ -42,8 +42,6 @@\n #else\n #include \"ena_plat_dpdk.h\"\n #endif\n-#elif defined(__FreeBSD__)\n-#include \"ena_plat_dpdk.h\"\n #elif defined(_WIN32)\n #include \"ena_plat_windows.h\"\n #else\ndiff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h\nindex 93345199a..e2af4ee2c 100644\n--- a/drivers/net/ena/base/ena_plat_dpdk.h\n+++ b/drivers/net/ena/base/ena_plat_dpdk.h\n@@ -73,10 +73,10 @@ typedef uint64_t dma_addr_t;\n #define ENA_COM_INVAL\t-EINVAL\n #define ENA_COM_NO_SPACE\t-ENOSPC\n #define ENA_COM_NO_DEVICE\t-ENODEV\n-#define ENA_COM_PERMISSION\t-EPERM\n #define ENA_COM_TIMER_EXPIRED\t-ETIME\n #define ENA_COM_FAULT\t-EFAULT\n #define ENA_COM_TRY_AGAIN\t-EAGAIN\n+#define ENA_COM_UNSUPPORTED    -EOPNOTSUPP\n \n #define ____cacheline_aligned __rte_cache_aligned\n \n@@ -138,6 +138,15 @@ typedef uint64_t dma_addr_t;\n #define ena_trc_err(format, arg...) do { } while (0)\n #endif /* RTE_LIBRTE_ENA_COM_DEBUG */\n \n+#define ENA_WARN(cond, format, arg...)                                 \\\n+do {                                                                   \\\n+       if (unlikely(cond)) {                                           \\\n+               ena_trc_err(                                            \\\n+                       \"Warn failed on %s:%s:%d:\" format,              \\\n+                       __FILE__, __func__, __LINE__, ##arg);           \\\n+       }                                                               \\\n+} while (0)\n+\n /* Spinlock related methods */\n #define ena_spinlock_t rte_spinlock_t\n #define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock)\n@@ -177,10 +186,21 @@ typedef uint64_t dma_addr_t;\n #define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)\n /* pthread condition doesn't need to be rearmed after usage */\n #define ENA_WAIT_EVENT_CLEAR(...)\n+#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))\n \n #define ena_wait_event_t ena_wait_queue_t\n #define ENA_MIGHT_SLEEP()\n \n+#define ENA_TIME_EXPIRE(timeout)  (timeout < rte_get_timer_cycles())\n+#define ENA_GET_SYSTEM_TIMEOUT(timeout_us)                             \\\n+       (timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())\n+\n+/*\n+ * Each rte_memzone should have unique name.\n+ * To satisfy it, count number of allocations and add it to name.\n+ */\n+extern uint32_t ena_alloc_cnt;\n+\n #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle)\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tconst struct rte_memzone *mz;\t\t\t\t\\\n@@ -200,7 +220,8 @@ typedef uint64_t dma_addr_t;\n \t\t   ENA_TOUCH(dmadev);\t\t\t\t\t\\\n \t\t   rte_memzone_free(handle); })\n \n-#define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, node, dev_node) \\\n+#define ENA_MEM_ALLOC_COHERENT_NODE(\t\t\t\t\t\\\n+\tdmadev, size, virt, phys, mem_handle, node, dev_node)\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tconst struct rte_memzone *mz;\t\t\t\t\\\n \t\tchar z_name[RTE_MEMZONE_NAMESIZE];\t\t\t\\\n@@ -212,6 +233,7 @@ typedef uint64_t dma_addr_t;\n \t\tmemset(mz->addr, 0, size);\t\t\t\t\\\n \t\tvirt = mz->addr;\t\t\t\t\t\\\n \t\tphys = mz->iova;\t\t\t\t\t\\\n+\t\t(void)mem_handle;\t\t\t\t\t\\\n \t} while (0)\n \n #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \\\n@@ -230,8 +252,10 @@ typedef uint64_t dma_addr_t;\n #define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)\n #define ENA_MEM_FREE(dmadev, ptr) ({ENA_TOUCH(dmadev); rte_free(ptr); })\n \n-#define ENA_REG_WRITE32(value, reg) rte_write32_relaxed((value), (reg))\n-#define ENA_REG_READ32(reg) rte_read32_relaxed((reg))\n+#define ENA_REG_WRITE32(bus, value, reg)\t\t\t\t\\\n+\t({ (void)(bus); rte_write32_relaxed((value), (reg)); })\n+#define ENA_REG_READ32(bus, reg)\t\t\t\t\t\\\n+\t({ (void)(bus); rte_read32_relaxed((reg)); })\n \n #define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)\n #define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)\n@@ -247,4 +271,11 @@ typedef uint64_t dma_addr_t;\n #define PTR_ERR(error) ((long)(void *)error)\n #define might_sleep()\n \n+#define lower_32_bits(x) ((uint32_t)(x))\n+#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))\n+\n+#ifndef READ_ONCE\n+#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var))))\n+#endif\n+\n #endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */\ndiff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex 190ed40d1..71d6838a0 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -114,6 +114,12 @@ struct ena_stats {\n #define ENA_STAT_GLOBAL_ENTRY(stat) \\\n \tENA_STAT_ENTRY(stat, dev)\n \n+/*\n+ * Each rte_memzone should have unique name.\n+ * To satisfy it, count number of allocation and add it to name.\n+ */\n+uint32_t ena_alloc_cnt;\n+\n static const struct ena_stats ena_stats_global_strings[] = {\n \tENA_STAT_GLOBAL_ENTRY(tx_timeout),\n \tENA_STAT_GLOBAL_ENTRY(io_suspend),\n@@ -195,6 +201,8 @@ static const struct rte_pci_id pci_id_ena_map[] = {\n \t{ .device_id = 0 },\n };\n \n+static struct ena_aenq_handlers empty_aenq_handlers;\n+\n static int ena_device_init(struct ena_com_dev *ena_dev,\n \t\t\t   struct ena_com_dev_get_features_ctx *get_feat_ctx);\n static int ena_dev_configure(struct rte_eth_dev *dev);\n@@ -346,9 +354,6 @@ static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,\n \t\tena_meta->mss = mbuf->tso_segsz;\n \t\tena_meta->l3_hdr_len = mbuf->l3_len;\n \t\tena_meta->l3_hdr_offset = mbuf->l2_len;\n-\t\t/* this param needed only for TSO */\n-\t\tena_meta->l3_outer_hdr_len = 0;\n-\t\tena_meta->l3_outer_hdr_offset = 0;\n \n \t\tena_tx_ctx->meta_valid = true;\n \t} else {\n@@ -388,7 +393,7 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev)\n \trc = ena_com_set_host_attributes(ena_dev);\n \tif (rc) {\n \t\tRTE_LOG(ERR, PMD, \"Cannot set host attributes\\n\");\n-\t\tif (rc != -EPERM)\n+\t\tif (rc != -ENA_COM_UNSUPPORTED)\n \t\t\tgoto err;\n \t}\n \n@@ -441,7 +446,7 @@ static void ena_config_debug_area(struct ena_adapter *adapter)\n \trc = ena_com_set_host_attributes(&adapter->ena_dev);\n \tif (rc) {\n \t\tRTE_LOG(WARNING, PMD, \"Cannot set host attributes\\n\");\n-\t\tif (rc != -EPERM)\n+\t\tif (rc != -ENA_COM_UNSUPPORTED)\n \t\t\tgoto err;\n \t}\n \n@@ -496,7 +501,7 @@ static int ena_rss_reta_update(struct rte_eth_dev *dev,\n \t\t\tret = ena_com_indirect_table_fill_entry(ena_dev,\n \t\t\t\t\t\t\t\ti,\n \t\t\t\t\t\t\t\tentry_value);\n-\t\t\tif (unlikely(ret && (ret != ENA_COM_PERMISSION))) {\n+\t\t\tif (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {\n \t\t\t\tRTE_LOG(ERR, PMD,\n \t\t\t\t\t\"Cannot fill indirect table\\n\");\n \t\t\t\tret = -ENOTSUP;\n@@ -506,7 +511,7 @@ static int ena_rss_reta_update(struct rte_eth_dev *dev,\n \t}\n \n \tret = ena_com_indirect_table_set(ena_dev);\n-\tif (unlikely(ret && (ret != ENA_COM_PERMISSION))) {\n+\tif (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {\n \t\tRTE_LOG(ERR, PMD, \"Cannot flush the indirect table\\n\");\n \t\tret = -ENOTSUP;\n \t\tgoto err;\n@@ -537,7 +542,7 @@ static int ena_rss_reta_query(struct rte_eth_dev *dev,\n \t\treturn -EINVAL;\n \n \tret = ena_com_indirect_table_get(ena_dev, indirect_table);\n-\tif (unlikely(ret && (ret != ENA_COM_PERMISSION))) {\n+\tif (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {\n \t\tRTE_LOG(ERR, PMD, \"cannot get indirect table\\n\");\n \t\tret = -ENOTSUP;\n \t\tgoto err;\n@@ -571,7 +576,7 @@ static int ena_rss_init_default(struct ena_adapter *adapter)\n \t\tval = i % nb_rx_queues;\n \t\trc = ena_com_indirect_table_fill_entry(ena_dev, i,\n \t\t\t\t\t\t       ENA_IO_RXQ_IDX(val));\n-\t\tif (unlikely(rc && (rc != ENA_COM_PERMISSION))) {\n+\t\tif (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {\n \t\t\tRTE_LOG(ERR, PMD, \"Cannot fill indirect table\\n\");\n \t\t\tgoto err_fill_indir;\n \t\t}\n@@ -579,19 +584,19 @@ static int ena_rss_init_default(struct ena_adapter *adapter)\n \n \trc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,\n \t\t\t\t\tENA_HASH_KEY_SIZE, 0xFFFFFFFF);\n-\tif (unlikely(rc && (rc != ENA_COM_PERMISSION))) {\n+\tif (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {\n \t\tRTE_LOG(INFO, PMD, \"Cannot fill hash function\\n\");\n \t\tgoto err_fill_indir;\n \t}\n \n \trc = ena_com_set_default_hash_ctrl(ena_dev);\n-\tif (unlikely(rc && (rc != ENA_COM_PERMISSION))) {\n+\tif (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {\n \t\tRTE_LOG(INFO, PMD, \"Cannot fill hash control\\n\");\n \t\tgoto err_fill_indir;\n \t}\n \n \trc = ena_com_indirect_table_set(ena_dev);\n-\tif (unlikely(rc && (rc != ENA_COM_PERMISSION))) {\n+\tif (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {\n \t\tRTE_LOG(ERR, PMD, \"Cannot flush the indirect table\\n\");\n \t\tgoto err_fill_indir;\n \t}\n@@ -1236,7 +1241,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev,\n \tena_com_set_mmio_read_mode(ena_dev, readless_supported);\n \n \t/* reset device */\n-\trc = ena_com_dev_reset(ena_dev);\n+\trc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);\n \tif (rc) {\n \t\tRTE_LOG(ERR, PMD, \"cannot reset device\\n\");\n \t\tgoto err_mmio_read_less;\n@@ -1252,7 +1257,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev,\n \tena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);\n \n \t/* ENA device administration layer init */\n-\trc = ena_com_admin_init(ena_dev, NULL, true);\n+\trc = ena_com_admin_init(ena_dev, &empty_aenq_handlers, true);\n \tif (rc) {\n \t\tRTE_LOG(ERR, PMD,\n \t\t\t\"cannot initialize ena admin queue with device\\n\");\n@@ -1854,3 +1859,24 @@ ena_init_log(void)\n \tif (ena_logtype_driver >= 0)\n \t\trte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);\n }\n+\n+/******************************************************************************\n+ ******************************** AENQ Handlers *******************************\n+ *****************************************************************************/\n+/**\n+ * This handler will called for unknown event group or unimplemented handlers\n+ **/\n+static void unimplemented_aenq_handler(__rte_unused void *data,\n+\t\t\t\t       __rte_unused struct ena_admin_aenq_entry *aenq_e)\n+{\n+\t// Unimplemented handler\n+}\n+\n+static struct ena_aenq_handlers empty_aenq_handlers = {\n+\t.handlers = {\n+\t\t[ENA_ADMIN_LINK_CHANGE] = unimplemented_aenq_handler,\n+\t\t[ENA_ADMIN_NOTIFICATION] = unimplemented_aenq_handler,\n+\t\t[ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler\n+\t},\n+\t.unimplemented_handler = unimplemented_aenq_handler\n+};\n",
    "prefixes": [
        "v5",
        "02/27"
    ]
}