Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 40867,
    "url": "http://patches.dpdk.org/api/patches/40867/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com",
    "date": "2018-06-08T16:45:15",
    "name": "[dpdk-dev,06/16] crypto/cpt/base: add sym crypto request prepare for CPT",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "830260af409adad8720e72ba1b94689c1852fa8a",
    "submitter": {
        "id": 893,
        "url": "http://patches.dpdk.org/api/people/893/?format=api",
        "name": "Anoob Joseph",
        "email": "anoob.joseph@caviumnetworks.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com/mbox/",
    "series": [
        {
            "id": 58,
            "url": "http://patches.dpdk.org/api/series/58/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=58",
            "date": "2018-06-08T16:45:09",
            "name": "Adding Cavium's crypto device(CPT) driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/58/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/40867/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/40867/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 34D5A1BAF5;\n\tFri,  8 Jun 2018 18:49:09 +0200 (CEST)",
            "from NAM04-SN1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr700058.outbound.protection.outlook.com [40.107.70.58])\n\tby dpdk.org (Postfix) with ESMTP id C9A035F51\n\tfor <dev@dpdk.org>; Fri,  8 Jun 2018 18:49:07 +0200 (CEST)",
            "from ajoseph83.caveonetworks.com.caveonetworks.com (115.113.156.2)\n\tby SN6PR07MB4911.namprd07.prod.outlook.com (2603:10b6:805:3c::29)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.820.15;\n\tFri, 8 Jun 2018 16:49:01 +0000"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=fq+dCjl+O1Olox7RRGcxN8T0EkwfJrvc/r7vzaR4a84=;\n\tb=oWFd46nWez1jW9kUYAmxFuxPZqYJ2GSEsrv6r3IumI67GsK+zqu+AbyO3IRvW/qXmPjrBFSd3kJ4OTcnzKbv/M0F7t0zqNVjxyQgbeJF9YOuSGy7sy7a7rjvdJdy6wpNRcU6PDopdSawmcTLb4+KzWrlumYww8pBa5kuu+gYUv0=",
        "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ",
        "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>",
        "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>",
        "Cc": "Ankur Dwivedi <ankur.dwivedi@cavium.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tMurthy NSSR <Nidadavolu.Murthy@cavium.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@cavium.com>,\n\tRagothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>,\n\tSrisivasubramanian Srinivasan\n\t<Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org",
        "Date": "Fri,  8 Jun 2018 22:15:15 +0530",
        "Message-Id": "<1528476325-15585-7-git-send-email-anoob.joseph@caviumnetworks.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>",
        "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[115.113.156.2]",
        "X-ClientProxiedBy": "BM1PR01CA0071.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:1::11) To SN6PR07MB4911.namprd07.prod.outlook.com\n\t(2603:10b6:805:3c::29)",
        "X-MS-PublicTrafficType": "Email",
        "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(7020095)(4652020)(5600026)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020);\n\tSRVR:SN6PR07MB4911; ",
        "X-Microsoft-Exchange-Diagnostics": [
            "1; SN6PR07MB4911;\n\t3:4s8CcQtOAtGULlYVYVHuaVd91ZmVkbzMkeIDaqZfE/GfnY1vxkbNMWwh6H88iQsRJfG/26U64qfIyjJKFOqQtrUfjQcS9S5L93oFQo2hVhpqOz9KKpr0+4MIvrs+XB2etIumk7mxg934lzSeeCJhtly6AF5gUhcI75hw04k+kbpg4lf/xZm+j5zUrd+twzeDEWBEsl5uJFJARWWagep3T62roMMGNGxhQEvYmJbnJ6DUtb73VD+WoxdQVJpDecsL;\n\t25:G4DeRYjPFJrVZXS4f4Qr8PM8O6NyKL6ZRTQulVu/XrSgZYqQhfXL6n/H4AhpRCTrlTXEHsKcqgjpA6I9R4naIwDTFbscK6q8lADOFvCl+2sH8fIBqkdeQZlgI6mND5Yp76rDHFRV3qtxliX5lJNQzQFOJmzjPdBHaiYAUOTyEnel+QGMOP+AWQMMVDonHtLYyn2Q6MRNQSxNbj1dduVKxBqXi9ba6kRwQTX5LquwNtkkIgsL1i734beC4sixbWMQhIyasfpfgOWJskJoFVjdK8w/A9vyVJSPhIPy/jXpBI92kE7VehSDhpO2e5NkHIGdIcTZivD7xXh+fiXEcWRQaw==;\n\t31:BFccUIuIjh4cDxAaFGgWtze8HUArxtMQDVrLYl0h7p1DWzIsi83aB4KeFkkWYgluo3QrQ71D/6lOFCUTRzkVMrl8WFSoZpjPqvTG6DJ4huWUhR/QDLhEiw5JqQej9qSfknd6Wpfqhd840j18AWsFSvxpABrqhTaR1OX46gNnHDMiqtfSwHLIyi2f8iB9eq+tMt9kSUeqDgcLqdOSfwIk2g1wJjzGOEKGhMbPI6GHWQI=",
            "1; SN6PR07MB4911;\n\t20:coq6Rhnb16LSW8WDJ/BmKD6NUrEyTxdm7GxHUdnf1QFtlAyaJwB3luq8vj3WiFY5wKSuzAK/sJjPpTWfBoCntSlN+zLlEr4dAvFXrFS6XpbBt2e9FaABaYQCer013DLZMFhNPP1mfpl3rndOICbJs+DzPqFApwGbcgIHz50omJobPWdWN73KuidcYHMXKiJw4Ltiwyj3zOC3jGjf8/DzAQfdEo7z5lqB1/mZk3HZjvhHrQEyh/2hNuTPKhV30WPvvVuXMp77++MXH6oXxZsAxvHB51WbYLJ/hoR+nVsZ7vbXdq3wSG+z5lACQnJgNjnvVcTrR91P0n1kxE1gwcwa0U5bLDwhXE54MmaDyy77/mmCri3CCfq1hD5Fb2fxrND36TemrfMjt7yOCoXEFxD1SpEdIUx1VsEy4Q68k9A9HCJ4yOKVD3yu/8wZBUgC4KnWKDUmz+3z7AGRla++NOS87SFSwaI6NaM+2Gu9RJLJKWssTL//vi9wbaBX/+CkzfP2eo7tfo0Re0dyOqVWThz1dIq/lK10vFQgX96NlU5L8mTnFMSgh6c2VJnD1Zu2SBrudPfUFqXYcUAbanb0tA19H/JseToca4x0vhUZ7rcYKfA=;\n\t4:LJ7w9/6x0WTql8q2iUGBuHukjic4PYv1cs5DGpuop7MRZ6czZYE/o12eC3Awhrm4TKrtvju887kjRL5zQR0Tkt/ik5qrCG0ITLTtenUZaHaPZTMCVLMbSc12DOX36KfMBFV3iPMbYBHdd/4cCZhVMaRC3FsRHSpy7gESigE9WblkWdlXj45nbzU3pqUy1M4pMqeyXuYHylvcLBs8MIabpWrEarTShj3Zr+3mhlXTTwZwFAblCP6hLzQQejnHb0qSZYAT5NRV20rRFVa76HX4xw==",
            "=?us-ascii?Q?1; SN6PR07MB4911;\n\t23:Kx0G/7fJngPtODg1mh95CaefuKcTsdKEe8K/H8Bar?=\n\tS3HXzhzPi3cttpqtkxuix4ikItSSG9+LJ8pS/3dwLaMkkbagET6ZPXSAksuwDX38VSeBa46acr0rpB3P1UJ2obb7zfUKE+GSmO+mxvstUmWpsaDNdgtB21k5+UZ0zEdwTOY7Y8ijENXHIaS53ehpXdY8YDKYaX8ZCNv7Re2MpF2AYn+eKFM2kDTdZrhgKuOK+Zztvv7gHUs6zLIHrRkX+E+VjY1URnSzZO4fWp5rGWAftP+DcADejMbuSVdlXmGxhZFYu8FpsKhky+KAduP0Fv42znrzxcrVeGKM8l3vLWgXul/UbkEjM7qfoWV5T2F3hUo3xrsQpCFuuoiv+TK/i3bnp6wstZXGP5O63AcbBprreAAVxC3fulVcDjjP3+plO1NE5WVbZf9TXdIyrP5DfUElZNQZ0OI9ERM5VPkVJ8IbBS8/jk/8jpDiHvv0EgxqjGW3XhRcsSeHqMlD2CxCe5YYpCmAtLOrYWLOJtwDDJxXDgd4V2dknHpihNFp1pHK8uJGb9tnCO9LN/pHEnNQgCkXq941TDOOJCBWzCPM91MWOrH+xjahowFdFzE10iP3yEGNFk3brwrwGGxEe0/qVZBwHCE59jfzFSs1jK1eO1rdX5FESVGUoUKdqVSY9PSgRoPFzxXwrw/MGC1iC8tE2CtyzrELHcaD1mGLOEZgK53326vZgHwRcLomjZShZYaZiWqC8sbbUHg8spR8VghQdE1GBYoN3+7023xL9CAv6b23uquh1CcGHUCDIZ8/Ymx1HUF50zGJQ1DBolfeNmwt2BsEsgAQRjbw5DBpJE+YtzWU9OwVBDzXwRYjSzxEAJGc7guHT9COdUz2E+ORh2CHGjDsz8xzgaS3jDWYmT/FZOe+w5cpmLPpG5modV94YHgCRcY3XSrAKBHP/lS6dm2G2JkhQ5c9UXjaqd7Aa7ZJhnPbSvBzAbMsvL5hnXDu5sj3kk0LbxXF9RWCuVNwuqdqHBNpYmfydOAPMjFNTgVLS/x8KlWsAxAIe3RbyEizmby4De797teYrlK0WXawlOWFSRYB+5JZCLKcr4ufIJ3WRyzrAWTwLah/HM5puWcjWFvCWitYUzvJ1s6noXmROJtbTUtJ5YXSGJvZ+SY/bLzHa/ib1Oqmp/ImV38NxghSeufJzaWQQtNA247qkK94Yeruswd4aRI4n75WQX3sUnqZGHDJovghelOgDFPZs09y60rDjiWwzaCNEmH4svaLOLl8A8V3zPoYs16y0wRxaW/0utJYMZB4Yo9v08nYFGDFe8HnOZ/9k50lFgqziBRrB66dDul",
            "1; SN6PR07MB4911;\n\t6:ZSA1Blf69ctqO9kRJB+Cz3sMkTNFui9PLx7IuPeZzeVkGaRD17kUX6NxmLSIq4TcsYxHB1sdPKxkyWBVTjKCEV8a8utQ01yQ75uit8itJwYLRR8XzIQ1OQe4btNHaPBBN+nVBf0WssR/z30gYFVVi/ymF6UIi0SCWd7xxIMD2TI8nJf+PVBmk6i+iICapL2EuzXtctO9riKZpEK3Ng1HKuaKRbTnOoUsjTLsy7XoOynT8K8eEt38DbbnOL4iPQQrfhcsTA4YY/AK4Ypomh0cjb2tP51sUagPTlFgPdj7HaU7RGbvp2QvXHNPpudk3yMzGIRa3y2y/qXZiqYhTooya9oz7UbtfLU1LjeN866246q50jqzH2MIjSMgQR8d9WI1R/rxQzIZNsnHkoJcoWqvQwVWBLxlSJbrkmfLrygdSHmrNL7l3jGQWTy1KSpdiXf5doRbevHwL/zxEfjvtx6Gag==;\n\t5:RHdgn6bWQUOEL9deQjr/vrObnx+7CsJqg/dimd5mE4ja7gdlC/jz1UG0FX+s90jp7atvQ4T89iySMpOt/MdE2cWQUy78maywUgqS9y/qB94GyJOx3T6bMxl+OmxUp51OGLyabr9GqA7dVOuyeX+vhdTaugHhHJPuwjzfJ17EbCE=;\n\t24:pEaV+Vt4R6HvE3yJZJwdoHpePxQyN209M8S/ONUSF5UjBPBHHqkPYDIEZ1dEvlr0fCSTtsHbWYmtmKQvzk8rh8CO5KdKxUk0s1ODvLaXrWY=",
            "1; SN6PR07MB4911;\n\t7:XjJjtH0PrJZMSo6dAQqVP2tWbfV1UJQctzy4b4lTF98jvrqIUTgd0m0m0ShFZewpUkcM3T0kAxK97oqR1xm/gkIV/gZm1sWQ/o4uhBBOWxBHGK23/dc8G0anMM3xpnwOzYocQyZT4fvwmqP9sKbFO4Y/tnOFA2LdSLdyU9Wb8K1Wro80OXMi6tUZ4t2PJoYT+rTyGnZAcn+3M+VJxcZw9oQ+Fd3TM3nQIbIQLPw7+Adf4lMW3VKoZ5wEOQ4rSzG0"
        ],
        "X-MS-TrafficTypeDiagnostic": "SN6PR07MB4911:",
        "X-Microsoft-Antispam-PRVS": "<SN6PR07MB49119CBE4CC7D1CB182868AFF87B0@SN6PR07MB4911.namprd07.prod.outlook.com>",
        "X-Exchange-Antispam-Report-Test": "UriScan:;",
        "X-MS-Exchange-SenderADCheck": "1",
        "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(8121501046)(5005006)(10201501046)(93006095)(3002001)(3231254)(944501410)(52105095)(149027)(150027)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123562045)(20161123558120)(20161123564045)(6072148)(201708071742011)(7699016);\n\tSRVR:SN6PR07MB4911; BCL:0; PCL:0; RULEID:; SRVR:SN6PR07MB4911; ",
        "X-Forefront-PRVS": "06973FFAD3",
        "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(376002)(396003)(346002)(39380400002)(366004)(39860400002)(189003)(199004)(26005)(52116002)(956004)(305945005)(8676002)(81156014)(50226002)(8936002)(81166006)(7736002)(68736007)(105586002)(106356001)(3846002)(6116002)(72206003)(478600001)(6486002)(97736004)(6506007)(16586007)(6512007)(53946003)(53936002)(47776003)(486006)(25786009)(5660300001)(50466002)(48376002)(6666003)(4326008)(54906003)(76176011)(36756003)(110136005)(66066001)(8656006)(2906002)(316002)(55236004)(11346002)(16526019)(386003)(186003)(59450400001)(446003)(476003)(42882007)(44832011)(2616005)(51416003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:SN6PR07MB4911;\n\tH:ajoseph83.caveonetworks.com.caveonetworks.com; FPR:; SPF:None;\n\tLANG:en; PTR:InfoNoRecords; MX:1; A:1; ",
        "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)",
        "X-Microsoft-Antispam-Message-Info": "qNJW73Mu4dLjqixiitXMXzIyWjgS+K3HcNYG0fMh9EX83Y1Qs16DsSjqOdKLTLu5ilbxrhSRm1tIS7rGPftemiijrolAF9wZ2MvsESobUiU0800HVXFhl+x9uIZWlnkFW0L1TXXIPbr8Xe/mqJLvBBn5rWogmDScm00ug9GXCB4nBfPl1i5e+JjfQurQ94CN",
        "SpamDiagnosticOutput": "1:99",
        "SpamDiagnosticMetadata": "NSPM",
        "X-MS-Office365-Filtering-Correlation-Id": "44c76f33-465e-47c1-9dfa-08d5cd5fbefc",
        "X-OriginatorOrg": "caviumnetworks.com",
        "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Jun 2018 16:49:01.6958\n\t(UTC)",
        "X-MS-Exchange-CrossTenant-Network-Message-Id": "44c76f33-465e-47c1-9dfa-08d5cd5fbefc",
        "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted",
        "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194",
        "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN6PR07MB4911",
        "Subject": "[dpdk-dev] [PATCH 06/16] crypto/cpt/base: add sym crypto request\n\tprepare for CPT",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Ankur Dwivedi <ankur.dwivedi@cavium.com>\n\nThese functions help in preparing symmetric crypto requests\nfor the supported cipher/auth/aead. This includes all supported\nalgos except Kasumi, Snow3G, Zuc, HMAC_ONLY and HASH_ONLY cases.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>\nSigned-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>\nSigned-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>\nSigned-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>\n---\n drivers/crypto/cpt/base/cpt.h     |  129 +++++\n drivers/crypto/cpt/base/cpt_ops.c | 1021 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 1150 insertions(+)",
    "diff": "diff --git a/drivers/crypto/cpt/base/cpt.h b/drivers/crypto/cpt/base/cpt.h\nindex 11407ae..54b1cb6 100644\n--- a/drivers/crypto/cpt/base/cpt.h\n+++ b/drivers/crypto/cpt/base/cpt.h\n@@ -54,6 +54,135 @@\n \tvoid *marker;\n } app_data_t;\n \n+/*\n+ * Parameters for Flexi Crypto\n+ * requests\n+ */\n+#define VALID_AAD_BUF 0x01\n+#define VALID_MAC_BUF 0x02\n+#define VALID_IV_BUF 0x04\n+#define SINGLE_BUF_INPLACE 0x08\n+#define SINGLE_BUF_HEADTAILROOM 0x10\n+\n+#define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)\n+#define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)\n+#define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)\n+#define ENCR_DLEN(__d_lens) (__d_lens >> 32)\n+#define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)\n+\n+typedef struct fc_params {\n+\t/* 0th cache line */\n+\tunion {\n+\t\tbuf_ptr_t bufs[1];\n+\t\tstruct {\n+\t\t\tiov_ptr_t *src_iov;\n+\t\t\tiov_ptr_t *dst_iov;\n+\t\t};\n+\t};\n+\tvoid *iv_buf;\n+\tvoid *auth_iv_buf;\n+\tbuf_ptr_t meta_buf;\n+\tbuf_ptr_t ctx_buf;\n+\tuint64_t rsvd2;\n+\n+\t/* 1st cache line */\n+\tbuf_ptr_t aad_buf;\n+\tbuf_ptr_t mac_buf;\n+\n+} fc_params_t;\n+\n+/*\n+ * Parameters for digest\n+ * generate requests\n+ * Only src_iov, op, ctx_buf, mac_buf, prep_req\n+ * meta_buf, auth_data_len are used for digest gen.\n+ */\n+typedef struct fc_params digest_params_t;\n+\n+/* Cipher Algorithms */\n+typedef mc_cipher_type_t cipher_type_t;\n+\n+/* Auth Algorithms */\n+typedef mc_hash_type_t auth_type_t;\n+\n+/* Flexi Crypto Operations */\n+/*\n+ * Encr | Encr + Hmac | HASH-HMAC generation\n+ */\n+/*\n+ * ZUC/SNOW3g enc cipher/cipher+auth/auth-gen operation\n+ */\n+/*\n+ * kasumi enc cipher/cipher+auth/auth-gen operation\n+ * F8 iv_buf: 64 bits Bigendian format\n+ * COUNT[63-32] || BEARER[31-27] ||\n+ * DIRECTION[26] || 0...0[25-0]\n+ * F9 mac gen auth_iv_buf: 64 bits BE + 8 bits\n+ * COUNT[63-32] || FRESH[31-0]\n+ * 0...0[7-1] || DIRECTION[0]\n+ */\n+void *cpt_fc_enc_hmac_prep(uint32_t flags,\n+\t\t\t   uint64_t d_offs,\n+\t\t\t   uint64_t d_lens,\n+\t\t\t   fc_params_t *params,\n+\t\t\t   void *op,\n+\t\t\t   int *ret);\n+/*\n+ * Decr | Decr + Hmac\n+ */\n+/*\n+ * ZUC/SNOW3g dec cipher/cipher+auth operation\n+ */\n+/*\n+ * kasumi dec cipher/cipher+auth/ operation\n+ * F8 iv_buf: 64 bits Bigendian format\n+ * COUNT[63-32] || BEARER[31-27] ||\n+ * DIRECTION[26] || 0...0[25-0]\n+ */\n+void *cpt_fc_dec_hmac_prep(uint32_t flags,\n+\t\t\t   uint64_t d_offs,\n+\t\t\t   uint64_t d_lens,\n+\t\t\t   fc_params_t *params,\n+\t\t\t   void *op,\n+\t\t\t   int *ret);\n+\n+/* Flexi Crypto Ctrl Operations */\n+int32_t cpt_fc_ciph_set_key(cpt_instance_t *inst,\n+\t\t\t    void *ctx,\n+\t\t\t    cipher_type_t type,\n+\t\t\t    uint8_t *key,\n+\t\t\t    uint16_t key_len,\n+\t\t\t    uint8_t *salt);\n+\n+int32_t cpt_fc_ciph_set_iv(cpt_instance_t *inst,\n+\t\t\t   void *ctx,\n+\t\t\t   uint8_t *iv,\n+\t\t\t   uint16_t iv_len);\n+\n+int32_t cpt_fc_auth_set_key(cpt_instance_t *inst,\n+\t\t\t    void *ctx,\n+\t\t\t    auth_type_t type,\n+\t\t\t    uint8_t *key,\n+\t\t\t    uint16_t key_len,\n+\t\t\t    uint16_t mac_len);\n+\n+void\n+cpt_fc_salt_update(void *ctx,\n+\t\t   uint8_t *salt);\n+/*\n+ * Get's size of contiguous meta buffer\n+ * to be allocated per op\n+ */\n+int32_t  cpt_fc_get_op_meta_len(void);\n+\n+/* Get context length for a session */\n+int32_t cpt_fc_get_ctx_len(void);\n+\n+/* Provides meta length required when it is\n+ * direct mode i.e single buf inplace\n+ */\n+int32_t cpt_fc_get_op_sb_meta_len(void);\n+\n /* Instance operations */\n \n /* Enqueue an SE/AE request */\ndiff --git a/drivers/crypto/cpt/base/cpt_ops.c b/drivers/crypto/cpt/base/cpt_ops.c\nindex e340006..31f8064 100644\n--- a/drivers/crypto/cpt/base/cpt_ops.c\n+++ b/drivers/crypto/cpt/base/cpt_ops.c\n@@ -86,6 +86,14 @@ int32_t cpt_fc_get_ctx_len(void)\n \treturn sizeof(struct cpt_ctx);\n }\n \n+inline void\n+cpt_fc_salt_update(void *ctx,\n+\t\t   uint8_t *salt)\n+{\n+\tstruct cpt_ctx *cpt_ctx = ctx;\n+\tmemcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);\n+}\n+\n int\n cpt_fc_ciph_set_key(cpt_instance_t *instance,\n \t\t    void *ctx, cipher_type_t type, uint8_t *key,\n@@ -306,3 +314,1016 @@ int32_t cpt_fc_get_ctx_len(void)\n \t*ctrl_flags = htobe64(*ctrl_flags);\n \treturn 0;\n }\n+\n+static inline uint32_t\n+fill_sg_comp(sg_comp_t *list,\n+\t     uint32_t i,\n+\t     phys_addr_t dma_addr,\n+\t     void *vaddr,\n+\t     uint32_t size)\n+{\n+\tsg_comp_t *to = &list[i>>2];\n+\n+\tto->u.s.len[i%4] = htobe16(size);\n+\tto->ptr[i%4] = htobe64(dma_addr);\n+\t(void) vaddr;\n+\ti++;\n+\treturn i;\n+}\n+\n+static inline uint32_t\n+fill_sg_comp_from_buf(sg_comp_t *list,\n+\t\t      uint32_t i,\n+\t\t      buf_ptr_t *from)\n+{\n+\tsg_comp_t *to = &list[i>>2];\n+\n+\tto->u.s.len[i%4] = htobe16(from->size);\n+\tto->ptr[i%4] = htobe64(from->dma_addr);\n+\ti++;\n+\treturn i;\n+}\n+\n+static inline uint32_t\n+fill_sg_comp_from_buf_min(sg_comp_t *list,\n+\t\t\t  uint32_t i,\n+\t\t\t  buf_ptr_t *from,\n+\t\t\t  uint32_t *psize)\n+{\n+\tsg_comp_t *to = &list[i >> 2];\n+\tuint32_t size = *psize;\n+\tuint32_t e_len;\n+\n+\te_len = (size > from->size) ? from->size : size;\n+\tto->u.s.len[i % 4] = htobe16(e_len);\n+\tto->ptr[i % 4] = htobe64(from->dma_addr);\n+\t*psize -= e_len;\n+\ti++;\n+\treturn i;\n+}\n+\n+/*\n+ * This fills the MC expected SGIO list\n+ * from IOV given by user.\n+ */\n+static inline uint32_t\n+fill_sg_comp_from_iov(sg_comp_t *list,\n+\t\t      uint32_t i,\n+\t\t      iov_ptr_t *from, uint32_t from_offset,\n+\t\t      uint32_t *psize, buf_ptr_t *extra_buf,\n+\t\t      uint32_t extra_offset)\n+{\n+\tint32_t j;\n+\tuint32_t extra_len = extra_buf ? extra_buf->size : 0;\n+\tuint32_t size = *psize - extra_len;\n+\tbuf_ptr_t *bufs;\n+\n+\tbufs = from->bufs;\n+\tfor (j = 0; (j < from->buf_cnt) && size; j++) {\n+\t\tphys_addr_t e_dma_addr;\n+\t\tuint32_t e_len;\n+\t\tsg_comp_t *to = &list[i >> 2];\n+\n+\t\tif (!bufs[j].size)\n+\t\t\tcontinue;\n+\n+\t\tif (unlikely(from_offset)) {\n+\t\t\tif (from_offset >= bufs[j].size) {\n+\t\t\t\tfrom_offset -= bufs[j].size;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\te_dma_addr = bufs[j].dma_addr + from_offset;\n+\t\t\te_len = (size > (bufs[j].size - from_offset)) ?\n+\t\t\t\t(bufs[j].size - from_offset) : size;\n+\t\t\tfrom_offset = 0;\n+\t\t} else {\n+\t\t\te_dma_addr = bufs[j].dma_addr;\n+\t\t\te_len = (size > bufs[j].size) ?\n+\t\t\t\tbufs[j].size : size;\n+\t\t}\n+\n+\t\tto->u.s.len[i % 4] = htobe16(e_len);\n+\t\tto->ptr[i % 4] = htobe64(e_dma_addr);\n+\n+\t\tif (extra_len && (e_len >= extra_offset)) {\n+\t\t\t/* Break the data at given offset */\n+\t\t\tuint32_t next_len = e_len - extra_offset;\n+\t\t\tphys_addr_t next_dma = e_dma_addr + extra_offset;\n+\n+\t\t\tif (!extra_offset) {\n+\t\t\t\ti--;\n+\t\t\t} else {\n+\t\t\t\te_len = extra_offset;\n+\t\t\t\tsize -= e_len;\n+\t\t\t\tto->u.s.len[i % 4] = htobe16(e_len);\n+\t\t\t}\n+\n+\t\t\t/* Insert extra data ptr */\n+\t\t\tif (extra_len) {\n+\t\t\t\ti++;\n+\t\t\t\tto = &list[i >> 2];\n+\t\t\t\tto->u.s.len[i % 4] = htobe16(extra_buf->size);\n+\t\t\t\tto->ptr[i % 4] = htobe64(extra_buf->dma_addr);\n+\n+\t\t\t\t/* size already decremented by extra len */\n+\t\t\t}\n+\n+\t\t\t/* insert the rest of the data */\n+\t\t\tif (next_len) {\n+\t\t\t\ti++;\n+\t\t\t\tto = &list[i >> 2];\n+\t\t\t\tto->u.s.len[i % 4] = htobe16(next_len);\n+\t\t\t\tto->ptr[i % 4] = htobe64(next_dma);\n+\t\t\t\tsize -= next_len;\n+\t\t\t}\n+\t\t\textra_len = 0;\n+\n+\t\t} else {\n+\t\t\tsize -= e_len;\n+\t\t}\n+\t\tif (extra_offset)\n+\t\t\textra_offset -= size;\n+\t\ti++;\n+\t}\n+\n+\t*psize = size;\n+\treturn (uint32_t)i;\n+}\n+\n+static inline int  __attribute__((always_inline))\n+cpt_enc_hmac_prep(uint32_t flags,\n+\t\t  uint64_t d_offs,\n+\t\t  uint64_t d_lens,\n+\t\t  fc_params_t *fc_params,\n+\t\t  void *op,\n+\t\t  void **prep_req)\n+{\n+\tuint32_t iv_offset = 0;\n+\tint32_t inputlen, outputlen, enc_dlen, auth_dlen;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tuint32_t cipher_type, hash_type;\n+\tuint32_t mac_len, size;\n+\tuint8_t iv_len = 16;\n+\tcpt_request_info_t *req;\n+\tbuf_ptr_t *meta_p, *aad_buf = NULL;\n+\tuint32_t encr_offset, auth_offset;\n+\tuint32_t encr_data_len, auth_data_len, aad_len = 0;\n+\tuint32_t passthrough_len = 0;\n+\tvoid *m_vaddr, *offset_vaddr;\n+\tuint64_t m_dma, offset_dma, ctx_dma;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\tvoid *c_vaddr;\n+\tuint64_t c_dma;\n+\tint32_t m_size;\n+\topcode_info_t opcode;\n+\n+\tmeta_p = &fc_params->meta_buf;\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!fc_params || !meta_p->vaddr || !meta_p->size)\n+\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\tm_vaddr = meta_p->vaddr;\n+\tm_dma = meta_p->dma_addr;\n+\tm_size = meta_p->size;\n+\n+\tencr_offset = ENCR_OFFSET(d_offs);\n+\tauth_offset = AUTH_OFFSET(d_offs);\n+\tencr_data_len = ENCR_DLEN(d_lens);\n+\tauth_data_len = AUTH_DLEN(d_lens);\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * We dont support both aad\n+\t\t * and auth data separately\n+\t\t */\n+\t\tauth_data_len = 0;\n+\t\tauth_offset = 0;\n+\t\taad_len = fc_params->aad_buf.size;\n+\t\taad_buf = &fc_params->aad_buf;\n+\t}\n+\tcpt_ctx = fc_params->ctx_buf.vaddr;\n+\tcipher_type = cpt_ctx->enc_cipher;\n+\thash_type = cpt_ctx->hash_type;\n+\tmac_len = cpt_ctx->mac_len;\n+\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* start cpt request info struct at 8 byte boundary */\n+\tsize = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\treq = (cpt_request_info_t *)((uint8_t *)m_vaddr + size);\n+\n+\tsize += sizeof(cpt_request_info_t);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\tif (hash_type == GMAC_TYPE)\n+\t\tencr_data_len = 0;\n+\n+\tif (unlikely(!(flags & VALID_IV_BUF))) {\n+\t\tiv_len = 0;\n+\t\tiv_offset = ENCR_IV_OFFSET(d_offs);\n+\t}\n+\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * When AAD is given, data above encr_offset is pass through\n+\t\t * Since AAD is given as separate pointer and not as offset,\n+\t\t * this is a special case as we need to fragment input data\n+\t\t * into passthrough + encr_data and then insert AAD in between.\n+\t\t */\n+\t\tif (hash_type != GMAC_TYPE) {\n+\t\t\tpassthrough_len = encr_offset;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tencr_offset = passthrough_len + aad_len + iv_len;\n+\t\t\tauth_data_len = aad_len + encr_data_len;\n+\t\t} else {\n+\t\t\tpassthrough_len = 16 + aad_len;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tauth_data_len = aad_len;\n+\t\t}\n+\t} else {\n+\t\tencr_offset += iv_len;\n+\t\tauth_offset += iv_len;\n+\t}\n+\n+\t/* Initialising ctrl and opcode\n+\t * fields in cpt request structure\n+\t */\n+\n+\treq->se_req = SE_CORE_REQ;\n+\t/*\n+\t * We are using DMA mode but indicate that\n+\t * SGIO list is already populated.\n+\t */\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\n+\t/* Encryption */\n+\topcode.s.major = MAJOR_OP_FC;\n+\topcode.s.minor = 0;\n+\n+\tauth_dlen = auth_offset + auth_data_len;\n+\tenc_dlen = encr_data_len + encr_offset;\n+\tif (unlikely(encr_data_len & 0xf)) {\n+\t\tif ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))\n+\t\t\tenc_dlen = ROUNDUP8(encr_data_len) + encr_offset;\n+\t\telse if (likely((cipher_type == AES_CBC) ||\n+\t\t\t\t(cipher_type == AES_ECB)))\n+\t\t\tenc_dlen = ROUNDUP16(encr_data_len) + encr_offset;\n+\t}\n+\n+\t/* TODO: MC issue */\n+\tif (unlikely(hash_type == GMAC_TYPE)) {\n+\t\tencr_offset = auth_dlen;\n+\t\tenc_dlen = 0;\n+\t}\n+\n+\tif (unlikely(auth_dlen > enc_dlen)) {\n+\t\tinputlen = auth_dlen;\n+\t\toutputlen = auth_dlen + mac_len;\n+\t} else {\n+\t\tinputlen = enc_dlen;\n+\t\toutputlen = enc_dlen + mac_len;\n+\t}\n+\n+\t/*GP op header */\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = htobe16(encr_data_len);\n+\tvq_cmd_w0.s.param2 = htobe16(auth_data_len);\n+\t/*\n+\t * In 83XX since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((flags & SINGLE_BUF_INPLACE) &&\n+\t\t   (flags & SINGLE_BUF_HEADTAILROOM))) {\n+\t\tvoid *dm_vaddr = fc_params->bufs[0].vaddr;\n+\t\tuint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;\n+\t\t/*\n+\t\t * This flag indicates that there is 24 bytes head room and\n+\t\t * 8 bytes tail room available, so that we get to do\n+\t\t * DIRECT MODE with limitation\n+\t\t */\n+\n+\t\toffset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;\n+\t\toffset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;\n+\n+\t\t/* DPTR */\n+\t\treq->ist.ei1 = offset_dma;\n+\t\t/* RPTR should just exclude offset control word */\n+\t\treq->ist.ei2 = dm_dma_addr - iv_len;\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr\n+\t\t\t\t\t\t    + outputlen - iv_len);\n+\t\t/* *req->alternate_caddr = ((uint64_t)0xdeadbeefdeadbeef) */\n+\n+\t\tvq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);\n+\n+\t\tvq_cmd_w0.s.opcode = htobe16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr\n+\t\t\t\t\t\t      + OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\thtobe64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\t} else {\n+\t\tuint32_t i, g_size_bytes, s_size_bytes;\n+\t\tuint64_t dptr_dma, rptr_dma;\n+\t\tsg_comp_t *gather_comp;\n+\t\tsg_comp_t *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\n+\t\t/* This falls under strict SG mode */\n+\t\toffset_vaddr = m_vaddr;\n+\t\toffset_dma = m_dma;\n+\t\tsize = OFF_CTRL_LEN + iv_len;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\topcode.s.major |= DMA_MODE;\n+\n+\t\tvq_cmd_w0.s.opcode = htobe16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr\n+\t\t\t\t\t\t      + OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\thtobe64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\t\tdptr_dma = m_dma;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\n+\t\ti = 0;\n+\n+\t\t/* Offset control word that includes iv */\n+\t\ti = fill_sg_comp(gather_comp, i, offset_dma,\n+\t\t\t\t offset_vaddr, OFF_CTRL_LEN + iv_len);\n+\n+\t\t/* Add input data */\n+\t\tsize = inputlen - iv_len;\n+\t\tif (likely(size)) {\n+\t\t\tuint32_t aad_offset = aad_len ? passthrough_len : 0;\n+\n+\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\ti = fill_sg_comp_from_buf_min(gather_comp, i,\n+\t\t\t\t\t\t\t      fc_params->bufs,\n+\t\t\t\t\t\t\t      &size);\n+\t\t\t} else {\n+\n+\t\t\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t\t\t  fc_params->src_iov,\n+\t\t\t\t\t\t\t  0, &size,\n+\t\t\t\t\t\t\t  aad_buf, aad_offset);\n+\t\t\t}\n+\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tPMD_TX_LOG(ERR, \"Insufficient buffer space,\"\n+\t\t\t\t\t   \" size %d need\\n\", size);\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = htobe16(i);\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\t/*\n+\t\t * Output Scatter list\n+\t\t */\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\t/* Add IV */\n+\t\tif (likely(iv_len)) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t\t\t (uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n+\n+\t\t/* output data or output data + digest*/\n+\t\tif (unlikely(flags & VALID_MAC_BUF)) {\n+\t\t\tsize = outputlen - iv_len - mac_len;\n+\t\t\tif (size) {\n+\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\t\tscatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t     fc_params->dst_iov,\n+\t\t\t\t\t\t\t\t0,\n+\t\t\t\t\t\t\t\t&size,\n+\t\t\t\t\t\t\t\taad_buf,\n+\t\t\t\t\t\t\t\taad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\t\t\t/* mac_data */\n+\t\t\tif (mac_len) {\n+\t\t\t\ti = fill_sg_comp_from_buf(scatter_comp, i,\n+\t\t\t\t\t\t\t  &fc_params->mac_buf);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Output including mac */\n+\t\t\tsize = outputlen - iv_len;\n+\t\t\tif (likely(size)) {\n+\t\t\t\tuint32_t aad_offset =\n+\t\t\t\t\taad_len ? passthrough_len : 0;\n+\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\t\tscatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp,\n+\t\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\t     fc_params->dst_iov,\n+\t\t\t\t\t\t\t\t0,\n+\t\t\t\t\t\t\t\t&size,\n+\t\t\t\t\t\t\t\taad_buf,\n+\t\t\t\t\t\t\t\taad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (unlikely(size)) {\n+\t\t\t\t\tPMD_TX_LOG(ERR, \"Insufficient buffer\"\n+\t\t\t\t\t\" space, size %d need\\n\", size);\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[3] = htobe16(i);\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len incase of SG mode */\n+\t\tvq_cmd_w0.s.dlen = htobe16(size);\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\t/* cpt alternate completion address saved earlier */\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\t\trptr_dma = c_dma - 8;\n+\n+\t\treq->ist.ei1 = dptr_dma;\n+\t\treq->ist.ei2 = rptr_dma;\n+\t}\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);\n+\n+\tctx_dma = fc_params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, fctx);\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = ctx_dma;\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr  = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op  = op;\n+\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!(m_size >= 0)) {\n+\t\tPMD_TX_LOG(ERR, \"!!! Buffer Overflow %d\\n\",\n+\t\t\t   m_size);\n+\t\tabort();\n+\t}\n+#endif\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n+static inline int\n+cpt_dec_hmac_prep(uint32_t flags,\n+\t\t  uint64_t d_offs,\n+\t\t  uint64_t d_lens,\n+\t\t  fc_params_t *fc_params,\n+\t\t  void *op,\n+\t\t  void **prep_req)\n+{\n+\tuint32_t iv_offset = 0, size;\n+\tint32_t inputlen, outputlen, enc_dlen, auth_dlen;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tint32_t hash_type, mac_len, m_size;\n+\tuint8_t iv_len = 16;\n+\tcpt_request_info_t *req;\n+\tbuf_ptr_t *meta_p, *aad_buf = NULL;\n+\tuint32_t encr_offset, auth_offset;\n+\tuint32_t encr_data_len, auth_data_len, aad_len = 0;\n+\tuint32_t passthrough_len = 0;\n+\tvoid *m_vaddr, *offset_vaddr;\n+\tuint64_t m_dma, offset_dma, ctx_dma;\n+\topcode_info_t opcode;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\tvoid *c_vaddr;\n+\tuint64_t c_dma;\n+\n+\tmeta_p = &fc_params->meta_buf;\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!fc_params || !meta_p->vaddr || !meta_p->size)\n+\t\treturn ERR_BAD_INPUT_ARG;\n+#endif\n+\tm_vaddr = meta_p->vaddr;\n+\tm_dma = meta_p->dma_addr;\n+\tm_size = meta_p->size;\n+\n+\tencr_offset = ENCR_OFFSET(d_offs);\n+\tauth_offset = AUTH_OFFSET(d_offs);\n+\tencr_data_len = ENCR_DLEN(d_lens);\n+\tauth_data_len = AUTH_DLEN(d_lens);\n+\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * We dont support both aad\n+\t\t * and auth data separately\n+\t\t */\n+\t\tauth_data_len = 0;\n+\t\tauth_offset = 0;\n+\t\taad_len = fc_params->aad_buf.size;\n+\t\taad_buf = &fc_params->aad_buf;\n+\t}\n+\n+\tcpt_ctx = fc_params->ctx_buf.vaddr;\n+\thash_type = cpt_ctx->hash_type;\n+\tmac_len = cpt_ctx->mac_len;\n+\n+\tif (hash_type == GMAC_TYPE)\n+\t\tencr_data_len = 0;\n+\n+\tif (unlikely(!(flags & VALID_IV_BUF))) {\n+\t\tiv_len = 0;\n+\t\tiv_offset = ENCR_IV_OFFSET(d_offs);\n+\t}\n+\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * When AAD is given, data above encr_offset is pass through\n+\t\t * Since AAD is given as separate pointer and not as offset,\n+\t\t * this is a special case as we need to fragment input data\n+\t\t * into passthrough + encr_data and then insert AAD in between.\n+\t\t */\n+\t\tif (hash_type != GMAC_TYPE) {\n+\t\t\tpassthrough_len = encr_offset;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tencr_offset = passthrough_len + aad_len + iv_len;\n+\t\t\tauth_data_len = aad_len + encr_data_len;\n+\t\t} else {\n+\t\t\tpassthrough_len = 16 + aad_len;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tauth_data_len = aad_len;\n+\t\t}\n+\t} else {\n+\t\tencr_offset += iv_len;\n+\t\tauth_offset += iv_len;\n+\t}\n+\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t       (uint8_t *)m_vaddr;\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* start cpt request info structure at 8 byte alignment */\n+\tsize = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\treq = (cpt_request_info_t *)((uint8_t *)m_vaddr + size);\n+\n+\tsize += sizeof(cpt_request_info_t);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Initialising ctrl and opcode\n+\t * fields in cpt request structure\n+\t */\n+\n+\treq->se_req = SE_CORE_REQ;\n+\t/*\n+\t * We are using DMA mode but indicate that\n+\t * SGIO list is already populated.\n+\t */\n+\treq->dma_mode = CTRL_DMA_MODE_SGIO;\n+\n+\t/* Decryption */\n+\topcode.s.major = MAJOR_OP_FC;\n+\topcode.s.minor = 1;\n+\n+\tenc_dlen = encr_offset + encr_data_len;\n+\tauth_dlen = auth_offset + auth_data_len;\n+\n+\tif (auth_dlen > enc_dlen) {\n+\t\tinputlen = auth_dlen + mac_len;\n+\t\toutputlen = auth_dlen;\n+\t} else {\n+\t\tinputlen = enc_dlen + mac_len;\n+\t\toutputlen = enc_dlen;\n+\t}\n+\n+\tif (hash_type == GMAC_TYPE)\n+\t\tencr_offset = inputlen;\n+\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = htobe16(encr_data_len);\n+\tvq_cmd_w0.s.param2 = htobe16(auth_data_len);\n+\n+\t/*\n+\t * In 83XX since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((flags & SINGLE_BUF_INPLACE) &&\n+\t\t   (flags & SINGLE_BUF_HEADTAILROOM))) {\n+\t\tvoid *dm_vaddr = fc_params->bufs[0].vaddr;\n+\t\tuint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;\n+\t\t/*\n+\t\t * This flag indicates that there is 24 bytes head room and\n+\t\t * 8 bytes tail room available, so that we get to do\n+\t\t * DIRECT MODE with limitation\n+\t\t */\n+\n+\t\toffset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;\n+\t\toffset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;\n+\t\treq->ist.ei1 = offset_dma;\n+\n+\t\t/* RPTR should just exclude offset control word */\n+\t\treq->ist.ei2 = dm_dma_addr - iv_len;\n+\n+\t\t/* In direct mode,changing the alternate completion code address\n+\t\t * to start of rptr,the assumption is that most auth iv failure\n+\t\t * are reported at first byte only.This will not give the\n+\t\t * correct alternate completion code the auth iv fail is\n+\t\t * reported  after some bytes.\n+\t\t * FIXME\n+\t\t */\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr -\n+\t\t\t\t\tiv_len);\n+\t\t/* since this is decryption,\n+\t\t * don't touch the content of\n+\t\t * alternate ccode space as it contains\n+\t\t * hmac.\n+\t\t */\n+\n+\t\tvq_cmd_w0.s.dlen = htobe16(inputlen + OFF_CTRL_LEN);\n+\n+\t\tvq_cmd_w0.s.opcode = htobe16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t      OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\thtobe64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\t} else {\n+\t\tuint64_t dptr_dma, rptr_dma;\n+\t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tsg_comp_t *gather_comp;\n+\t\tsg_comp_t *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\t\tuint8_t i = 0;\n+\n+\t\t/* This falls under strict SG mode */\n+\t\toffset_vaddr = m_vaddr;\n+\t\toffset_dma = m_dma;\n+\t\tsize = OFF_CTRL_LEN + iv_len;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\topcode.s.major |= DMA_MODE;\n+\n+\t\tvq_cmd_w0.s.opcode = htobe16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t      OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\thtobe64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\t\tdptr_dma = m_dma;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\t\ti = 0;\n+\n+\t\t/* Offset control word that includes iv */\n+\t\ti = fill_sg_comp(gather_comp, i, offset_dma,\n+\t\t\t\t offset_vaddr, OFF_CTRL_LEN + iv_len);\n+\n+\t\t/* Add input data */\n+\t\tif (flags & VALID_MAC_BUF) {\n+\t\t\tsize = inputlen - iv_len - mac_len;\n+\t\t\tif (size) {\n+\t\t\t\t/* input data only */\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\t\tgather_comp, i,\n+\t\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\tuint32_t aad_offset = aad_len ?\n+\t\t\t\t\t\tpassthrough_len : 0;\n+\n+\t\t\t\t\ti = fill_sg_comp_from_iov(gather_comp,\n+\t\t\t\t\t\t\t   i,\n+\t\t\t\t\t\t\t   fc_params->src_iov,\n+\t\t\t\t\t\t\t   0, &size,\n+\t\t\t\t\t\t\t   aad_buf,\n+\t\t\t\t\t\t\t   aad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\n+\t\t\t/* mac data */\n+\t\t\tif (mac_len) {\n+\t\t\t\ti = fill_sg_comp_from_buf(gather_comp, i,\n+\t\t\t\t\t\t\t  &fc_params->mac_buf);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* input data + mac */\n+\t\t\tsize = inputlen - iv_len;\n+\t\t\tif (size) {\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\t\tgather_comp, i,\n+\t\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\tuint32_t aad_offset = aad_len ?\n+\t\t\t\t\t\tpassthrough_len : 0;\n+\n+\t\t\t\t\tif (!fc_params->src_iov)\n+\t\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t\t\t\t       i = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t\t\t     fc_params->src_iov,\n+\t\t\t\t\t\t\t     0, &size,\n+\t\t\t\t\t\t\t     aad_buf,\n+\t\t\t\t\t\t\t     aad_offset);\n+\t\t\t\t}\n+\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = htobe16(i);\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\t/*\n+\t\t * Output Scatter List\n+\t\t */\n+\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\t/* Add iv */\n+\t\tif (iv_len) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t\t\t (uint8_t *)offset_vaddr + OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n+\n+\t\t/* Add output data */\n+\t\tsize = outputlen - iv_len;\n+\t\tif (size) {\n+\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t/* handle single buffer here */\n+\t\t\t\ti = fill_sg_comp_from_buf_min(scatter_comp, i,\n+\t\t\t\t\t\t\t      fc_params->bufs,\n+\t\t\t\t\t\t\t      &size);\n+\t\t\t} else {\n+\t\t\t\tuint32_t aad_offset = aad_len ?\n+\t\t\t\t\tpassthrough_len : 0;\n+\n+\t\t\t\tif (!fc_params->dst_iov)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t\t  fc_params->dst_iov, 0,\n+\t\t\t\t\t\t\t  &size, aad_buf,\n+\t\t\t\t\t\t\t  aad_offset);\n+\t\t\t}\n+\n+\t\t\tif (unlikely(size))\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\n+\t\t((uint16_t *)in_buffer)[3] = htobe16(i);\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len incase of SG mode */\n+\t\tvq_cmd_w0.s.dlen = htobe16(size);\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\t/* cpt alternate completion address saved earlier */\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\t\trptr_dma = c_dma - 8;\n+\t\tsize += COMPLETION_CODE_SIZE;\n+\n+\t\treq->ist.ei1 = dptr_dma;\n+\t\treq->ist.ei2 = rptr_dma;\n+\t}\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = htobe64(vq_cmd_w0.u64);\n+\n+\tctx_dma = fc_params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, fctx);\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = ctx_dma;\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr  = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+#ifdef CPTVF_STRICT_PARAM_CHECK\n+\tif (!(m_size >= 0)) {\n+\t\tPMD_TX_LOG(ERR, \"!!! Buffer Overflow %d\\n\",\n+\t\t\t   m_size);\n+\t\tabort();\n+\t}\n+#endif\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n+void *\n+cpt_fc_dec_hmac_prep(uint32_t flags,\n+\t\t     uint64_t d_offs,\n+\t\t     uint64_t d_lens,\n+\t\t     fc_params_t *fc_params,\n+\t\t     void *op, int *ret_val)\n+{\n+\tstruct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;\n+\tuint8_t fc_type;\n+\tvoid *prep_req = NULL;\n+\tint ret;\n+\n+\tfc_type = ctx->fc_type;\n+\n+\tif (likely(fc_type == FC_GEN)) {\n+\t\tret = cpt_dec_hmac_prep(flags, d_offs, d_lens,\n+\t\t\t\t\tfc_params, op, &prep_req);\n+\t} else {\n+\t\t/*\n+\t\t * For AUTH_ONLY case,\n+\t\t * MC only supports digest generation and verification\n+\t\t * should be done in software by memcmp()\n+\t\t */\n+\n+\t\tret = ERR_EIO;\n+\t}\n+\n+\tif (unlikely(!prep_req))\n+\t\t*ret_val = ret;\n+\treturn prep_req;\n+}\n+\n+void *__hot\n+cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n+\t\t     fc_params_t *fc_params, void *op, int *ret_val)\n+{\n+\tstruct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;\n+\tuint8_t fc_type;\n+\tvoid *prep_req = NULL;\n+\tint ret;\n+\n+\tfc_type = ctx->fc_type;\n+\n+\t/* Common api for rest of the ops */\n+\tif (likely(fc_type == FC_GEN)) {\n+\t\tret = cpt_enc_hmac_prep(flags, d_offs, d_lens,\n+\t\t\t\t\tfc_params, op, &prep_req);\n+\t} else {\n+\t\tret = ERR_EIO;\n+\t}\n+\n+\tif (unlikely(!prep_req))\n+\t\t*ret_val = ret;\n+\treturn prep_req;\n+}\n",
    "prefixes": [
        "dpdk-dev",
        "06/16"
    ]
}