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GET /api/patches/40864/?format=api
{ "id": 40864, "url": "http://patches.dpdk.org/api/patches/40864/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1528476325-15585-4-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1528476325-15585-4-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1528476325-15585-4-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-06-08T16:45:12", "name": "[dpdk-dev,03/16] crypto/cpt/base: add hardware initialization API for CPT", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fd54e91fd69fff008a82484a1b9d6b33fad90c52", "submitter": { "id": 893, "url": "http://patches.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1528476325-15585-4-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 58, "url": "http://patches.dpdk.org/api/series/58/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=58", "date": "2018-06-08T16:45:09", "name": "Adding Cavium's crypto device(CPT) driver", "version": 1, "mbox": "http://patches.dpdk.org/series/58/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/40864/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/40864/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 10A911B76D;\n\tFri, 8 Jun 2018 18:48:57 +0200 (CEST)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam02on0050.outbound.protection.outlook.com [104.47.36.50])\n\tby dpdk.org (Postfix) with ESMTP id BFD6F5F17\n\tfor <dev@dpdk.org>; Fri, 8 Jun 2018 18:48:54 +0200 (CEST)", "from ajoseph83.caveonetworks.com.caveonetworks.com (115.113.156.2)\n\tby SN6PR07MB4911.namprd07.prod.outlook.com (2603:10b6:805:3c::29)\n\twith Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.820.15;\n\tFri, 8 Jun 2018 16:48:48 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=5lCTEv37vxRNquAWLPZve66DT8tfxb7QA10irfWlaDo=;\n\tb=DTcahU0TnEbypu/JT4HAbdac/uHQ+rcwPrqRCpw3f4psbxqfKXZgKQ8B2NuGuYgg8SHL6/C6d5AoggfW1S8vUZsYXCQWAf/NV7pG7Xm8wCpLVSHHzaVlabHonxZpMbajz81BJFcIthD7Vq0p+OHw/JXpgrM+TyqTExkFI6ghKAk=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Nithin Dabilpuram <nithin.dabilpuram@cavium.com>,\n\tAnkur Dwivedi <ankur.dwivedi@cavium.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tMurthy NSSR <Nidadavolu.Murthy@cavium.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tRagothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>,\n\tSrisivasubramanian Srinivasan\n\t<Srisivasubramanian.Srinivasan@cavium.com>, dev@dpdk.org", "Date": "Fri, 8 Jun 2018 22:15:12 +0530", "Message-Id": "<1528476325-15585-4-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "BM1PR01CA0071.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:1::11) To SN6PR07MB4911.namprd07.prod.outlook.com\n\t(2603:10b6:805:3c::29)", "X-MS-PublicTrafficType": "Email", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(7020095)(4652020)(5600026)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020);\n\tSRVR:SN6PR07MB4911; ", "X-Microsoft-Exchange-Diagnostics": [ "1; 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"yuwl3DZXExsw2tTbL7LONeN5lPV9XAXjf2h+9J/VjzbL7tbPLBcp9mlFo4eoIx4ZVRsGxwzSoANuQmHT+4TMHK3izy7SOFr7OThV5f8qDHYKbuo4BZNwvN3IXhwywB349vPOQQyL/aQICkQckPjTetAd0Q4bKmBtdrrn7enscaNs5y3v6kpyy5ESayC81pno", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Office365-Filtering-Correlation-Id": "de22e199-9281-45c6-a731-08d5cd5fb753", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Jun 2018 16:48:48.8768\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "de22e199-9281-45c6-a731-08d5cd5fb753", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN6PR07MB4911", "Subject": "[dpdk-dev] [PATCH 03/16] crypto/cpt/base: add hardware\n\tinitialization API for CPT", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>\n\nAdds hardware device initialization specific api for Cavium CPT device.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>\nSigned-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>\nSigned-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>\nSigned-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>\n---\n drivers/crypto/cpt/base/cpt8xxx_device.c | 200 ++++++++++++++++\n drivers/crypto/cpt/base/cpt8xxx_device.h | 85 +++++++\n drivers/crypto/cpt/base/cpt_debug.h | 231 +++++++++++++++++++\n drivers/crypto/cpt/base/cpt_device.c | 383 +++++++++++++++++++++++++++++++\n drivers/crypto/cpt/base/cpt_device.h | 162 +++++++++++++\n drivers/crypto/cpt/base/cpt_vf_mbox.c | 176 ++++++++++++++\n drivers/crypto/cpt/base/cpt_vf_mbox.h | 60 +++++\n 7 files changed, 1297 insertions(+)\n create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.c\n create mode 100644 drivers/crypto/cpt/base/cpt8xxx_device.h\n create mode 100644 drivers/crypto/cpt/base/cpt_debug.h\n create mode 100644 drivers/crypto/cpt/base/cpt_device.c\n create mode 100644 drivers/crypto/cpt/base/cpt_device.h\n create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.c\n create mode 100644 drivers/crypto/cpt/base/cpt_vf_mbox.h", "diff": "diff --git a/drivers/crypto/cpt/base/cpt8xxx_device.c b/drivers/crypto/cpt/base/cpt8xxx_device.c\nnew file mode 100644\nindex 0000000..cdce96f\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt8xxx_device.c\n@@ -0,0 +1,200 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#include \"cpt8xxx_device.h\"\n+\n+/*\n+ * VF HAL functions\n+ * Access its own BAR0/4 registers by passing VF number as 0.\n+ * OS/PCI maps them accordingly.\n+ */\n+\n+/* Send a mailbox message to PF\n+ * @vf: vf from which this message to be sent\n+ * @mbx: Message to be sent\n+ */\n+void cptvf_send_msg_to_pf(struct cpt_vf *cptvf, cpt_mbox_t *mbx)\n+{\n+\t/* Writing mbox(1) causes interrupt */\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VFX_PF_MBOXX(0, 0, 0), mbx->msg);\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VFX_PF_MBOXX(0, 0, 1), mbx->data);\n+}\n+\n+/* Read Interrupt status of the VF\n+ * @vf: vf number\n+ */\n+uint64_t cptvf_read_vf_misc_intr_status(struct cpt_vf *cptvf)\n+{\n+\treturn CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));\n+}\n+\n+/* Clear mailbox interrupt of the VF\n+ * @vf: vf number\n+ */\n+void cptvf_clear_mbox_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.mbox = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/* Clear swerr interrupt of the VF\n+ * @vf: vf number\n+ */\n+void cptvf_clear_swerr_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.swerr = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/* Clear doorbell overflow interrupt of the VF\n+ * @vf: vf number\n+ */\n+void cptvf_clear_dovf_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.dovf = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/* Clear instruction NCB read error interrupt of the VF\n+ * @vf: vf number\n+ */\n+void cptvf_clear_irde_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.irde = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/* Clear NCB result write response error interrupt of the VF\n+ * @vf: vf number\n+ */\n+void cptvf_clear_nwrp_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.nwrp = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/* Clear hwerr interrupt of the VF\n+ * @vf: vf number\n+ */\n+void cptvf_clear_hwerr_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.hwerr = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/* Clear translation fault interrupt of the VF\n+ * @vf: vf number\n+ */\n+void cptvf_clear_fault_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\tCPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.fault = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\tCPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/* Write to VQX_CTL register\n+ */\n+void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val)\n+{\n+\tcptx_vqx_ctl_t vqx_ctl;\n+\n+\tvqx_ctl.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_CTL(0, 0));\n+\tvqx_ctl.s.ena = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_CTL(0, 0), vqx_ctl.u);\n+}\n+\n+/* Write to VQX_INPROG register\n+ */\n+void cptvf_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val)\n+{\n+\tcptx_vqx_inprog_t vqx_inprg;\n+\n+\tvqx_inprg.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_INPROG(0, 0));\n+\tvqx_inprg.s.inflight = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_INPROG(0, 0), vqx_inprg.u);\n+}\n+\n+/* Write to VQX_DONE_WAIT NUMWAIT register\n+ */\n+void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val)\n+{\n+\tcptx_vqx_done_wait_t vqx_dwait;\n+\n+\tvqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_DONE_WAIT(0, 0));\n+\tvqx_dwait.s.num_wait = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);\n+}\n+\n+/* Write to VQX_DONE_WAIT NUM_WAIT register\n+ */\n+void cptvf_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val)\n+{\n+\tcptx_vqx_done_wait_t vqx_dwait;\n+\n+\tvqx_dwait.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_DONE_WAIT(0, 0));\n+\tvqx_dwait.s.time_wait = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_DONE_WAIT(0, 0), vqx_dwait.u);\n+}\n+\n+/* Write to VQX_SADDR register\n+ */\n+void cptvf_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val)\n+{\n+\tcptx_vqx_saddr_t vqx_saddr;\n+\n+\tvqx_saddr.u = val;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_SADDR(0, 0), vqx_saddr.u);\n+}\ndiff --git a/drivers/crypto/cpt/base/cpt8xxx_device.h b/drivers/crypto/cpt/base/cpt8xxx_device.h\nnew file mode 100644\nindex 0000000..b7d7dcd\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt8xxx_device.h\n@@ -0,0 +1,85 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __CPT81XX_DEVICE_H\n+#define __CPT81XX_DEVICE_H\n+\n+#include \"cpt_device.h\"\n+#include \"cpt_vf_mbox.h\"\n+/*\n+ * CPT Registers map for 81xx\n+ */\n+\n+/* VF registers */\n+#define CPTX_VQX_CTL(a, b) (0x0000100ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_SADDR(a, b) (0x0000200ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_WAIT(a, b) (0x0000400ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_INPROG(a, b) (0x0000410ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE(a, b) (0x0000420ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_ACK(a, b) (0x0000440ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_INT_W1S(a, b) (0x0000460ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_INT_W1C(a, b) (0x0000468ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_ENA_W1S(a, b) (0x0000470ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_ENA_W1C(a, b) (0x0000478ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_INT(a, b) (0x0000500ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_INT_W1S(a, b) (0x0000508ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_ENA_W1S(a, b) (0x0000510ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_ENA_W1C(a, b) (0x0000518ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DOORBELL(a, b) (0x0000600ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VFX_PF_MBOXX(a, b, c) (0x0001000ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b) + \\\n+\t\t\t\t\t 8ll * ((c) & 0x1))\n+/* VF HAL functions */\n+void cptvf_send_msg_to_pf(struct cpt_vf *cptvf, cpt_mbox_t *mbx);\n+void cptvf_clear_mbox_intr(struct cpt_vf *cptvf);\n+void cptvf_clear_swerr_intr(struct cpt_vf *cptvf);\n+void cptvf_clear_dovf_intr(struct cpt_vf *cptvf);\n+void cptvf_clear_irde_intr(struct cpt_vf *cptvf);\n+void cptvf_clear_nwrp_intr(struct cpt_vf *cptvf);\n+void cptvf_clear_fault_intr(struct cpt_vf *cptvf);\n+void cptvf_clear_hwerr_intr(struct cpt_vf *cptvf);\n+void cptvf_write_vq_ctl(struct cpt_vf *cptvf, bool val);\n+void cptvf_write_vq_saddr(struct cpt_vf *cptvf, uint64_t val);\n+void cptvf_write_vq_done_timewait(struct cpt_vf *cptvf, uint16_t val);\n+void cptvf_write_vq_done_numwait(struct cpt_vf *cptvf, uint32_t val);\n+void cptvf_write_vq_inprog(struct cpt_vf *cptvf, uint8_t val);\n+uint64_t cptvf_read_vf_misc_intr_status(struct cpt_vf *cptvf);\n+\n+/* Write to VQX_DOORBELL register\n+ */\n+static inline void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)\n+{\n+\tcptx_vqx_doorbell_t vqx_dbell;\n+\n+\tvqx_dbell.u = 0;\n+\tvqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);\n+}\n+\n+static inline uint32_t cptvf_read_vq_doorbell(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_doorbell_t vqx_dbell;\n+\n+\tvqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_DOORBELL(0, 0));\n+\treturn vqx_dbell.s.dbell_cnt;\n+}\n+\n+#endif /* __CPT81XX_DEVICE_H */\ndiff --git a/drivers/crypto/cpt/base/cpt_debug.h b/drivers/crypto/cpt/base/cpt_debug.h\nnew file mode 100644\nindex 0000000..afa05df\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_debug.h\n@@ -0,0 +1,231 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __CPT_DEBUG_H\n+#define __CPT_DEBUG_H\n+#include <stdlib.h>\n+#include <assert.h>\n+#include \"cpt_request_mgr.h\"\n+#include <rte_eal_memconfig.h>\n+\n+#ifdef CPT_DEBUG\n+static inline void *\n+os_iova2va(phys_addr_t physaddr)\n+{\n+\treturn rte_mem_iova2virt(physaddr);\n+}\n+\n+static inline void __cpt_dump_buffer(const char *prefix_str,\n+\t\t\t\t void *buf, size_t len, int rowsize)\n+{\n+\tsize_t i = 0;\n+\tunsigned char *ptr = (unsigned char *)buf;\n+\n+\tPRINT(\"\\n%s[%p]\", prefix_str, buf);\n+\tPRINT(\"\\n%.8lx: \", i);\n+\n+\tif (buf == NULL) {\n+\t\tPRINT(\"\\n!!!NULL ptr\\n\");\n+\t\tabort();\n+\t}\n+\n+\tfor (i = 0; i < len; i++) {\n+\t\tif (i && !(i % rowsize))\n+\t\t\tPRINT(\"\\n%.8lx: \", i);\n+\t\tPRINT(\"%02x \", ptr[i]);\n+\t}\n+\tPRINT(\"\\n\\n\");\n+}\n+\n+static inline void cpt_dump_buffer(const char *prefix_str,\n+\t\t\t\t void *buf, size_t len)\n+{\n+\t__cpt_dump_buffer(prefix_str, buf, len, 8);\n+}\n+\n+#define cpt_fn_trace(fmt, ...)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\\\n+\t\tif (msg_req_trace(debug))\t\t\\\n+\t\t\tcpt_info(fmt, ##__VA_ARGS__);\t\\\n+\t} while (0)\n+\n+static inline void dump_cpt_request_info(struct cpt_request_info *req,\n+\t\t\t\t\t cpt_inst_s_t *inst)\n+{\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\tuint16_t opcode, param1, param2, dlen;\n+\n+\tvq_cmd_w0.u64 = be64toh(inst->s.ei0);\n+\topcode = be16toh(vq_cmd_w0.s.opcode);\n+\tparam1 = be16toh(vq_cmd_w0.s.param1);\n+\tparam2 = be16toh(vq_cmd_w0.s.param2);\n+\tdlen = be16toh(vq_cmd_w0.s.dlen);\n+\tvq_cmd_w3.u64 = inst->s.ei3;\n+\n+\tPRINT(\"\\ncpt Request Info...\\n\");\n+\tPRINT(\"\\tdma_mode: %u\\n\", req->dma_mode);\n+\tPRINT(\"\\tis_se : %u\\n\", req->se_req);\n+\tPRINT(\"\\tgrp : 0\\n\");\n+\n+\tPRINT(\"\\nRequest Info...\\n\");\n+\tPRINT(\"\\topcode: 0x%0x\\n\", opcode);\n+\tPRINT(\"\\tparam1: 0x%0x\\n\", param1);\n+\tPRINT(\"\\tparam2: 0x%0x\\n\", param2);\n+\tPRINT(\"\\tdlen: %u\\n\", dlen);\n+\tPRINT(\"\\tctx_handle vaddr %p, dma 0x%lx\\n\",\n+\t\t os_iova2va((uint64_t)vq_cmd_w3.s.cptr),\n+\t\t (uint64_t)vq_cmd_w3.s.cptr);\n+}\n+\n+static inline void\n+dump_cpt_request_sglist(cpt_inst_s_t *inst,\n+\t\t const char *header, bool data,\n+\t\t bool glist)\n+{\n+\tint i;\n+\tchar suffix[64];\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tuint16_t opcode, dlen;\n+\tconst char *list = glist ? \"glist\" : \"slist\";\n+\n+\tvq_cmd_w0.u64 = be64toh(inst->s.ei0);\n+\topcode = be16toh(vq_cmd_w0.s.opcode);\n+\tdlen = be16toh(vq_cmd_w0.s.dlen);\n+\n+\tif (opcode & DMA_MODE) {\n+\t\tuint8_t *in_buffer = os_iova2va(inst->s.ei1);\n+\t\tuint16_t list_cnt, components;\n+\t\tstruct sglist_comp *sg_ptr = NULL;\n+\t\tstruct {\n+\t\t\tvoid *vaddr;\n+\t\t\tphys_addr_t dma_addr;\n+\t\t\tuint32_t size;\n+\t\t} list_ptr[MAX_SG_CNT];\n+\n+\t\tPRINT(\"%s: DMA Mode\\n\", header);\n+\t\tsnprintf(suffix, sizeof(suffix),\n+\t\t\t \"DPTR: vaddr %p, dma 0x%lx len %u: \",\n+\t\t\t in_buffer, inst->s.ei1, dlen);\n+\n+\t\tcpt_dump_buffer(suffix,\n+\t\t\t\tin_buffer,\n+\t\t\t\tdlen);\n+\n+\t\tsg_ptr = (void *)(in_buffer + 8);\n+\t\tlist_cnt = be16toh((((uint16_t *)in_buffer)[2]));\n+\t\tif (!glist) {\n+\t\t\tcomponents = list_cnt / 4;\n+\t\t\tif (list_cnt % 4)\n+\t\t\t\tcomponents++;\n+\t\t\tsg_ptr += components;\n+\t\t\tlist_cnt = be16toh((((uint16_t *)in_buffer)[3]));\n+\t\t}\n+\t\tPRINT(\"current %s: %u\\n\", list, list_cnt);\n+\t\tif (!(list_cnt <= MAX_SG_CNT))\n+\t\t\tabort();\n+\n+\t\tcomponents = list_cnt / 4;\n+\n+\t\tfor (i = 0; i < components; i++) {\n+\t\t\tlist_ptr[i*4+0].size = be16toh(sg_ptr->u.s.len[0]);\n+\t\t\tlist_ptr[i*4+1].size = be16toh(sg_ptr->u.s.len[1]);\n+\t\t\tlist_ptr[i*4+2].size = be16toh(sg_ptr->u.s.len[2]);\n+\t\t\tlist_ptr[i*4+3].size = be16toh(sg_ptr->u.s.len[3]);\n+\t\t\tlist_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]);\n+\t\t\tlist_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]);\n+\t\t\tlist_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]);\n+\t\t\tlist_ptr[i*4+3].dma_addr = be64toh(sg_ptr->ptr[3]);\n+\n+\t\t\tlist_ptr[i*4+0].vaddr =\n+\t\t\t\tos_iova2va(list_ptr[i*4+0].dma_addr);\n+\t\t\tlist_ptr[i*4+1].vaddr =\n+\t\t\t\tos_iova2va(list_ptr[i*4+1].dma_addr);\n+\t\t\tlist_ptr[i*4+2].vaddr =\n+\t\t\t\tos_iova2va(list_ptr[i*4+2].dma_addr);\n+\t\t\tlist_ptr[i*4+3].vaddr =\n+\t\t\t\tos_iova2va(list_ptr[i*4+3].dma_addr);\n+\t\t\tsg_ptr++;\n+\t\t}\n+\t\tcomponents = list_cnt % 4;\n+\n+\t\tswitch (components) {\n+\t\tcase 3:\n+\t\t\tlist_ptr[i*4+2].size = be16toh(sg_ptr->u.s.len[2]);\n+\t\t\tlist_ptr[i*4+2].dma_addr = be64toh(sg_ptr->ptr[2]);\n+\t\t\tlist_ptr[i*4+2].vaddr =\n+\t\t\t\tos_iova2va(list_ptr[i*4+2].dma_addr);\n+\t\t\t/* fall through */\n+\t\tcase 2:\n+\t\t\tlist_ptr[i*4+1].size = be16toh(sg_ptr->u.s.len[1]);\n+\t\t\tlist_ptr[i*4+1].dma_addr = be64toh(sg_ptr->ptr[1]);\n+\t\t\tlist_ptr[i*4+1].vaddr =\n+\t\t\t\tos_iova2va(list_ptr[i*4+1].dma_addr);\n+\t\t\t/* fall through */\n+\t\tcase 1:\n+\t\t\tlist_ptr[i*4+0].size = be16toh(sg_ptr->u.s.len[0]);\n+\t\t\tlist_ptr[i*4+0].dma_addr = be64toh(sg_ptr->ptr[0]);\n+\t\t\tlist_ptr[i*4+0].vaddr =\n+\t\t\t\tos_iova2va(list_ptr[i*4+0].dma_addr);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tfor (i = 0; i < list_cnt; i++) {\n+\t\t\tsnprintf(suffix, sizeof(suffix),\n+\t\t\t\t \"%s[%d]: vaddr %p, dma 0x%lx len %u: \",\n+\t\t\t\t list, i, list_ptr[i].vaddr,\n+\t\t\t\t list_ptr[i].dma_addr,\n+\t\t\t\t list_ptr[i].size);\n+\t\t\tif (data)\n+\t\t\t\tcpt_dump_buffer(suffix,\n+\t\t\t\t\t\tlist_ptr[i].vaddr,\n+\t\t\t\t\t\tlist_ptr[i].size);\n+\t\t\telse\n+\t\t\t\tPRINT(\"%s\\n\", suffix);\n+\t\t}\n+\t} else {\n+\t\tPRINT(\"%s: Direct Mode\\n\", header);\n+\n+\t\tif (glist) {\n+\t\t\tsnprintf(suffix, sizeof(suffix),\n+\t\t\t\t \"DPTR: vaddr %p, dma 0x%lx len %u: \",\n+\t\t\t\t os_iova2va(inst->s.ei1),\n+\t\t\t\t inst->s.ei1, dlen);\n+\t\t\tif (data)\n+\t\t\t\tcpt_dump_buffer(suffix,\n+\t\t\t\t\t\tos_iova2va(inst->s.ei1),\n+\t\t\t\t\t\tdlen);\n+\t\t\telse\n+\t\t\t\tPRINT(\"%s\\n\", suffix);\n+\t\t} else {\n+\t\t\tsnprintf(suffix, sizeof(suffix),\n+\t\t\t\t \"RPTR: vaddr %p, dma 0x%lx len %u+..: \",\n+\t\t\t\t os_iova2va(inst->s.ei2),\n+\t\t\t\t inst->s.ei2, dlen);\n+\t\t\t/*\n+\t\t\t * In direct mode, we don't have rlen\n+\t\t\t * to dump exactly, so dump dlen + 32\n+\t\t\t */\n+\t\t\tif (data)\n+\t\t\t\tcpt_dump_buffer(suffix,\n+\t\t\t\t\t\tos_iova2va(inst->s.ei2),\n+\t\t\t\t\t\tdlen + 32);\n+\t\t\telse\n+\t\t\t\tPRINT(\"%s\\n\", suffix);\n+\t\t}\n+\t}\n+}\n+\n+\n+#else\n+\n+#define cpt_dump_buffer(__str, __buf, __len)\n+#define cpt_fn_trace(fmt, ...)\n+#define dump_cpt_request_info(req, ist)\n+#define dump_cpt_request_sglist(ist, header, data, flag)\n+#endif /* CPT_DEBUG */\n+\n+#endif /* __CPT_DEBUG_H */\ndiff --git a/drivers/crypto/cpt/base/cpt_device.c b/drivers/crypto/cpt/base/cpt_device.c\nnew file mode 100644\nindex 0000000..b7cd5b5\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_device.c\n@@ -0,0 +1,383 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#include \"cpt_device.h\"\n+#include \"cpt_debug.h\"\n+#include \"cpt8xxx_device.h\"\n+#include \"cpt_vf_mbox.h\"\n+#include \"cpt_request_mgr.h\"\n+\n+#include <rte_memzone.h>\n+\n+static void cptvf_vfvq_init(struct cpt_vf *cptvf)\n+{\n+\tuint64_t base_addr = 0;\n+\n+\t/* Disable the VQ */\n+\tcptvf_write_vq_ctl(cptvf, 0);\n+\n+\t/* Reset the doorbell */\n+\tcptvf_write_vq_doorbell(cptvf, 0);\n+\t/* Clear inflight */\n+\tcptvf_write_vq_inprog(cptvf, 0);\n+\n+\t/* Write VQ SADDR */\n+\tbase_addr = (uint64_t)(cptvf->cqueue.chead[0].dma_addr);\n+\tcptvf_write_vq_saddr(cptvf, base_addr);\n+\n+\t/* Configure timerhold / coalescence */\n+\tcptvf_write_vq_done_timewait(cptvf, CPT_TIMER_THOLD);\n+\tcptvf_write_vq_done_numwait(cptvf, CPT_COUNT_THOLD);\n+\n+\t/* Enable the VQ */\n+\tcptvf_write_vq_ctl(cptvf, 1);\n+\n+\t/* Flag the VF ready */\n+\tcptvf->flags |= CPT_FLAG_DEVICE_READY;\n+}\n+\n+static int cpt_vf_init(struct cpt_vf *cptvf)\n+{\n+\tint err = -1;\n+\n+\t/* Mark as VF driver */\n+\tcptvf->flags |= CPT_FLAG_VF_DRIVER;\n+\n+\t/* Check ready with PF */\n+\t/* Gets chip ID / device Id from PF if ready */\n+\terr = cptvf_check_pf_ready(cptvf);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF not responding to READY msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\terr = -EBUSY;\n+\t\tgoto cptvf_err;\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"%s: cpt_vf_init() done\\n\", cptvf->dev_name);\n+\treturn 0;\n+\n+cptvf_err:\n+\treturn err;\n+}\n+\n+static int cpt_vq_init(struct cpt_vf *cptvf, uint8_t group)\n+{\n+\tint err;\n+\n+\t/* Convey VQ LEN to PF */\n+\terr = cptvf_send_vq_size_msg(cptvf);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF not responding to QLEN msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\terr = -EBUSY;\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* CPT VF device initialization */\n+\tcptvf_vfvq_init(cptvf);\n+\n+\t/* Send msg to PF to assign currnet Q to required group */\n+\tcptvf->vfgrp = group;\n+\terr = cptvf_send_vf_to_grp_msg(cptvf, group);\n+\tif (err) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF not responding to VF_GRP msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\terr = -EBUSY;\n+\t\tgoto cleanup;\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"%s: cpt_vq_init() done\\n\", cptvf->dev_name);\n+\treturn 0;\n+\n+cleanup:\n+\treturn err;\n+}\n+\n+void cptvf_poll_misc(void *dev)\n+{\n+\tuint64_t intr;\n+\tstruct cpt_vf *cptvf = dev;\n+\n+\tintr = cptvf_read_vf_misc_intr_status(cptvf);\n+\n+\tif (!intr)\n+\t\treturn;\n+\n+\t/*Check for MISC interrupt types*/\n+\tif (likely(intr & CPT_VF_INTR_MBOX_MASK)) {\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: Mailbox interrupt 0x%lx on CPT VF %d\\n\",\n+\t\t\t cptvf->dev_name, intr, cptvf->vfid);\n+\t\tcptvf_handle_mbox_intr(cptvf);\n+\t\tcptvf_clear_mbox_intr(cptvf);\n+\t} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {\n+\t\tcptvf_clear_irde_intr(cptvf);\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: Instruction NCB read error interrupt\"\n+\t\t\t \" 0x%lx on CPT VF %d\\n\", cptvf->dev_name, intr,\n+\t\t\t cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {\n+\t\tcptvf_clear_nwrp_intr(cptvf);\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: NCB response write error interrupt\"\n+\t\t\" 0x%lx on CPT VF %d\\n\", cptvf->dev_name, intr, cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {\n+\t\tcptvf_clear_swerr_intr(cptvf);\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: Software error interrupt 0x%lx on\"\n+\t\t\" CPT VF %d\\n\", cptvf->dev_name, intr, cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {\n+\t\tcptvf_clear_hwerr_intr(cptvf);\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: Hardware error interrupt 0x%lx on\"\n+\t\t\" CPT VF %d\\n\", cptvf->dev_name, intr, cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {\n+\t\tcptvf_clear_fault_intr(cptvf);\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: Translation fault interrupt 0x%lx on\"\n+\t\t\" CPT VF %d\\n\", cptvf->dev_name, intr, cptvf->vfid);\n+\t} else\n+\t\tPMD_DRV_LOG(ERR, \"%s: Unhandled interrupt 0x%lx in CPT VF %d\\n\",\n+\t\t\t cptvf->dev_name, intr, cptvf->vfid);\n+}\n+\n+int cptvf_deinit_device(struct cpt_vf *dev)\n+{\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)dev;\n+\n+\t/* Do misc work one last time */\n+\tcptvf_poll_misc(cptvf);\n+\n+\t/* TODO anything else ?? */\n+\n+\treturn 0;\n+}\n+\n+int cptvf_init_device(struct cpt_vf *cptvf,\n+\t\t void *pdev,\n+\t\t void *reg_base,\n+\t\t char *name,\n+\t\t uint32_t flags)\n+{\n+\t(void) flags;\n+\n+\tmemset(cptvf, 0, sizeof(struct cpt_vf));\n+\n+\t/* Bar0 base address */\n+\tcptvf->reg_base = reg_base;\n+\tstrncpy(cptvf->dev_name, name, 32);\n+\n+\tcptvf->nr_queues = 1;\n+\tcptvf->max_queues = 1;\n+\tcptvf->pdev = pdev;\n+\n+\t/* To clear if there are any pending mbox msgs */\n+\tcptvf_poll_misc(cptvf);\n+\n+\tif (cpt_vf_init(cptvf)) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to initialize CPT VF device\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+int cptvf_get_resource(struct cpt_vf *dev,\n+\t\t uint8_t group, cpt_instance_t **instance)\n+{\n+\tint ret = -ENOENT, len, qlen, i;\n+\tint chunk_len, chunks, chunk_size;\n+\tstruct cpt_vf *cptvf = dev;\n+\tcpt_instance_t *cpt_instance;\n+\tstruct command_chunk *chunk_head = NULL, *chunk_prev = NULL;\n+\tstruct command_chunk *chunk = NULL;\n+\tuint8_t *mem;\n+\tconst struct rte_memzone *rz;\n+\tuint64_t dma_addr = 0, alloc_len, used_len;\n+\tuint64_t *next_ptr;\n+\tuint64_t pg_sz = sysconf(_SC_PAGESIZE);\n+\n+\tPMD_DRV_LOG(DEBUG, \"Initializing csp resource %s\\n\", cptvf->dev_name);\n+\n+\tcpt_instance = &cptvf->instance;\n+\n+\tmemset(&cptvf->cqueue, 0, sizeof(cptvf->cqueue));\n+\tmemset(&cptvf->pqueue, 0, sizeof(cptvf->pqueue));\n+\n+\t/* Chunks are of fixed size buffers */\n+\tchunks = DEFAULT_CMD_QCHUNKS;\n+\tchunk_len = DEFAULT_CMD_QCHUNK_SIZE;\n+\n+\tqlen = chunks * chunk_len;\n+\t/* Chunk size includes 8 bytes of next chunk ptr */\n+\tchunk_size = chunk_len * CPT_INST_SIZE + CPT_NEXT_CHUNK_PTR_SIZE;\n+\n+\t/* For command chunk structures */\n+\tlen = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8);\n+\n+\t/* For pending queue */\n+\tlen += qlen * RTE_ALIGN(sizeof(rid_t), 8);\n+\n+\t/* So that instruction queues start as pg size aligned */\n+\tlen = RTE_ALIGN(len, pg_sz);\n+\n+\t/* For Instruction queues */\n+\tlen += chunks * RTE_ALIGN(chunk_size, 128);\n+\n+\t/* Wastage after instruction queues */\n+\tlen = RTE_ALIGN(len, pg_sz);\n+\n+\trz = rte_memzone_reserve_aligned(cptvf->dev_name, len, cptvf->node,\n+\t\t\t\t\t RTE_MEMZONE_SIZE_HINT_ONLY |\n+\t\t\t\t\t RTE_MEMZONE_256MB,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!rz) {\n+\t\tret = rte_errno;\n+\t\tgoto cleanup;\n+\t}\n+\n+\tmem = rz->addr;\n+\tdma_addr = rz->phys_addr;\n+\talloc_len = len;\n+\n+\tmemset(mem, 0, len);\n+\n+\tcpt_instance->rsvd = (uint64_t)rz;\n+\n+\t/* Pending queue setup */\n+\tcptvf->pqueue.rid_queue = (rid_t *)mem;\n+\tcptvf->pqueue.soft_qlen = qlen;\n+\tcptvf->pqueue.enq_tail = 0;\n+\tcptvf->pqueue.deq_head = 0;\n+\tcptvf->pqueue.pending_count = 0;\n+\n+\tmem += qlen * RTE_ALIGN(sizeof(rid_t), 8);\n+\tlen -= qlen * RTE_ALIGN(sizeof(rid_t), 8);\n+\tdma_addr += qlen * RTE_ALIGN(sizeof(rid_t), 8);\n+\n+\t/* Alignement wastage */\n+\tused_len = alloc_len - len;\n+\tmem += RTE_ALIGN(used_len, pg_sz) - used_len;\n+\tlen -= RTE_ALIGN(used_len, pg_sz) - used_len;\n+\tdma_addr += RTE_ALIGN(used_len, pg_sz) - used_len;\n+\n+\t/* Init instruction queues */\n+\tchunk_head = &cptvf->cqueue.chead[0];\n+\ti = qlen;\n+\n+\tchunk_prev = NULL;\n+\tfor (i = 0; i < DEFAULT_CMD_QCHUNKS; i++) {\n+\t\tint csize;\n+\n+\t\tchunk = &cptvf->cqueue.chead[i];\n+\t\tchunk->head = mem;\n+\t\tchunk->dma_addr = dma_addr;\n+\n+\t\tcsize = RTE_ALIGN(chunk_size, 128);\n+\t\tmem += csize;\n+\t\tdma_addr += csize;\n+\t\tlen -= csize;\n+\n+\t\tif (chunk_prev) {\n+\t\t\tnext_ptr = (uint64_t *)(chunk_prev->head +\n+\t\t\t\t\t\tchunk_size - 8);\n+\t\t\t*next_ptr = (uint64_t)chunk->dma_addr;\n+\t\t}\n+\t\tchunk_prev = chunk;\n+\t}\n+\t/* Circular loop */\n+\tnext_ptr = (uint64_t *)(chunk_prev->head + chunk_size - 8);\n+\t*next_ptr = (uint64_t)chunk_head->dma_addr;\n+\n+\tassert(!len);\n+\n+\tcptvf->qlen = qlen;\n+\t/* This is used for CPT(0)_PF_Q(0..15)_CTL.size config */\n+\tcptvf->qsize = chunk_size / 8;\n+\tcptvf->cqueue.qhead = chunk_head->head;\n+\tcptvf->cqueue.idx = 0;\n+\tcptvf->cqueue.cchunk = 0;\n+\n+\tif (cpt_vq_init(cptvf, group)) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to initialize CPT VQ of device %s\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\tret = -EBUSY;\n+\t\tgoto cleanup;\n+\t}\n+\n+\t*instance = cpt_instance;\n+\n+\tPMD_DRV_LOG(DEBUG, \"Crypto device (%s) initialized\\n\",\n+\t\t cptvf->dev_name);\n+\n+\treturn 0;\n+cleanup:\n+\trte_memzone_free(rz);\n+\t*instance = NULL;\n+\treturn ret;\n+}\n+\n+int cptvf_put_resource(cpt_instance_t *instance)\n+{\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n+\tstruct rte_memzone *rz;\n+\n+\tif (!cptvf) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid CPTVF handle\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"Releasing csp device %s\\n\", cptvf->dev_name);\n+\n+\trz = (struct rte_memzone *)instance->rsvd;\n+\trte_memzone_free(rz);\n+\treturn 0;\n+}\n+\n+int cptvf_start_device(struct cpt_vf *cptvf)\n+{\n+\tint rc;\n+\n+\trc = cptvf_send_vf_up(cptvf);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to mark CPT VF device %s UP, rc = %d\\n\"\n+\t\t\t , cptvf->dev_name, rc);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif ((cptvf->vftype != SE_TYPE) &&\n+\t (cptvf->vftype != AE_TYPE)) {\n+\t\tPMD_DRV_LOG(ERR, \"Fatal error, unexpected vf type %u, for CPT\"\n+\t\t\" VF device %s\\n\", cptvf->vftype, cptvf->dev_name);\n+\t\treturn -ENOENT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void cptvf_stop_device(struct cpt_vf *cptvf)\n+{\n+\tint rc;\n+\tuint32_t pending, retries = 5;\n+\n+\t/* Wait for pending entries to complete */\n+\tpending = cptvf_read_vq_doorbell(cptvf);\n+\twhile (pending) {\n+\t\tPRINT(\"%s: Waiting for pending %u cmds to complete\\n\",\n+\t\t cptvf->dev_name, pending);\n+\t\tsleep(1);\n+\t\tpending = cptvf_read_vq_doorbell(cptvf);\n+\t\tretries--;\n+\t\tif (!retries)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (!retries && pending) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: Timeout waiting for commands(%u)\\n\",\n+\t\t\t cptvf->dev_name, pending);\n+\t\treturn;\n+\t}\n+\n+\trc = cptvf_send_vf_down(cptvf);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to bring down vf %s, rc %d\\n\",\n+\t\t\t cptvf->dev_name, rc);\n+\t\treturn;\n+\t}\n+}\ndiff --git a/drivers/crypto/cpt/base/cpt_device.h b/drivers/crypto/cpt/base/cpt_device.h\nnew file mode 100644\nindex 0000000..951c7ae\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_device.h\n@@ -0,0 +1,162 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __CPT_DEVICE_H\n+#define __CPT_DEVICE_H\n+\n+#include \"cpt.h\"\n+#include \"cpt_hw_types.h\"\n+#include <rte_io.h>\n+#include <rte_atomic.h>\n+#include <rte_cycles.h>\n+#include <rte_pci.h>\n+\n+/* Device ID */\n+#define PCI_VENDOR_ID_CAVIUM\t\t 0x177d\n+#define CPT_81XX_PCI_VF_DEVICE_ID\t 0xa041\n+\n+#define CPT_NUM_QS_PER_VF (1)\n+\n+#define CPT_MBOX_MSG_TIMEOUT 2000 /* In Milli Seconds */\n+\n+/**< flags to indicate the features supported */\n+#define CPT_FLAG_VF_DRIVER\t\t(uint16_t)(1 << 3)\n+#define CPT_FLAG_DEVICE_READY\t(uint16_t)(1 << 4)\n+\n+#ifndef ROUNDUP4\n+#define ROUNDUP4(val)\t(((val) + 3) & 0xfffffffc)\n+#endif\n+\n+#ifndef ROUNDUP8\n+#define ROUNDUP8(val)\t(((val) + 7) & 0xfffffff8)\n+#endif\n+\n+#ifndef ROUNDUP16\n+#define ROUNDUP16(val)\t(((val) + 15) & 0xfffffff0)\n+#endif\n+\n+/* Default command queue length */\n+#define DEFAULT_CMD_QCHUNKS\t2\n+#define DEFAULT_CMD_QCHUNK_SIZE 1023\n+#define DEFAULT_CMD_QLEN (DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS)\n+\n+/* Default command timeout in seconds */\n+#define DEFAULT_COMMAND_TIMEOUT\t 4\n+\n+#define CPT_COUNT_THOLD\t\t32\n+#define CPT_TIMER_THOLD\t\t0x3F\n+\n+\n+#define AE_TYPE 1\n+#define SE_TYPE 2\n+\n+typedef enum {\n+\tCPT_81XX = 1,\n+\tCPT_AE_83XX,\n+\tCPT_SE_83XX,\n+\tINVALID_CPT\n+} cpt_pf_type_t;\n+\n+typedef struct rid {\n+\tuint64_t\trid; /* Request id of a crypto operation */\n+/*\tvoid\t\t*op; */ /* Opaque operation handle returned */\n+} rid_t; /* Array of pending request's */\n+\n+typedef struct pending_queue {\n+\tuint16_t enq_tail;\n+\tuint16_t deq_head;\n+\tuint16_t soft_qlen; /* Software expected queue length */\n+\tuint16_t p_doorbell;\n+\trid_t *rid_queue; /* Array of pending request's */\n+\tuint64_t pending_count; /* Pending requests count */\n+} pending_queue_t;\n+\n+struct command_chunk {\n+\tuint8_t *head;\t\t /**< 128-byte aligned real_vaddr */\n+\tphys_addr_t dma_addr;\t\t/**< 128-byte aligned real_dma_addr */\n+};\n+\n+/**\n+ * comamnd queue structure\n+ */\n+struct command_queue {\n+\tuint32_t idx;\n+\t/**< Command queue host write idx */\n+\tuint32_t cchunk;\n+\tuint8_t *qhead;\n+\t/**< Command queue head, instructions are inserted here */\n+\tstruct command_chunk chead[DEFAULT_CMD_QCHUNKS];\n+\t/**< Command chunk list head */\n+};\n+\n+/**\n+ * CPT VF device structure\n+ */\n+struct cpt_vf {\n+\tcpt_instance_t instance;\n+\n+\t/* base address where BAR is mapped */\n+\tuint8_t *reg_base; /**< Register start address */\n+\n+\t/* Command and Pending queues */\n+\tstruct command_queue cqueue;/**< Command queue information */\n+\tstruct pending_queue pqueue;/**< Pending queue information */\n+\n+\t/* Below fields are accessed only in control path */\n+\n+\t/*\n+\t * This points to environment specific pdev that\n+\t * represents the pci dev\n+\t */\n+\tvoid *pdev;\n+\tuint32_t qlen;\n+\t/*\n+\t * Qsize * CPT_INST_SIZE +\n+\t * alignment size(CPT_INST_SIZE +\n+\t * next chunk pointer size (8)\n+\t */\n+\tuint32_t qsize;\n+\t/**< Calculated queue size */\n+\tuint32_t nr_queues;\n+\tuint32_t max_queues;\n+\n+\tuint32_t chip_id;\n+\t/**< CPT Device ID */\n+\tuint16_t flags;\n+\t/**< Flags to hold device status bits */\n+\tuint8_t vfid;\n+\t/**< Device Index (0...CPT_MAX_VQ_NUM */\n+\tuint8_t vftype;\n+\t/**< VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */\n+\tuint8_t vfgrp;\n+\t/**< VF group (0 - 8) */\n+\tuint8_t node;\n+\t/**< Operating node: Bits (46:44) in BAR0 address */\n+\n+\t/* VF-PF mailbox communication */\n+\tbool pf_acked;\n+\tbool pf_nacked;\n+\tchar dev_name[32];\n+} ____cacheline_aligned_in_smp;\n+\n+#define CPT_CSR_REG_BASE(cpt) ((cpt)->reg_base)\n+\n+#define CPT_READ_CSR(__hw_addr, __offset) \\\n+\trte_read64_relaxed((uint8_t *)__hw_addr + __offset)\n+#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \\\n+\trte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))\n+\n+void cptvf_poll_misc(void *dev);\n+int cptvf_deinit_device(struct cpt_vf *dev);\n+int cptvf_init_device(struct cpt_vf *cptvf,\n+\t\t void *pdev,\n+\t\t void *reg_base,\n+\t\t char *name,\n+\t\t uint32_t flags);\n+int cptvf_get_resource(struct cpt_vf *dev,\n+\t\t uint8_t group, cpt_instance_t **instance);\n+int cptvf_put_resource(cpt_instance_t *instance);\n+int cptvf_start_device(struct cpt_vf *cptvf);\n+void cptvf_stop_device(struct cpt_vf *cptvf);\n+#endif /* __CPT_DEVICE_H */\ndiff --git a/drivers/crypto/cpt/base/cpt_vf_mbox.c b/drivers/crypto/cpt/base/cpt_vf_mbox.c\nnew file mode 100644\nindex 0000000..00d98bb\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_vf_mbox.c\n@@ -0,0 +1,176 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#include \"cpt8xxx_device.h\"\n+#include \"cpt_vf_mbox.h\"\n+#include <unistd.h>\n+\n+/* Poll handler to handle mailbox messages from VFs */\n+void cptvf_handle_mbox_intr(struct cpt_vf *cptvf)\n+{\n+\tcpt_mbox_t mbx = {0, 0};\n+\n+\t/*\n+\t * MBOX[0] contains msg\n+\t * MBOX[1] contains data\n+\t */\n+\tmbx.msg = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\tCPTX_VFX_PF_MBOXX(0, 0, 0));\n+\tmbx.data = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\tCPTX_VFX_PF_MBOXX(0, 0, 1));\n+\n+\tPMD_DRV_LOG(DEBUG, \"%s: Mailbox msg 0x%lx from PF\\n\",\n+\t\t cptvf->dev_name, mbx.msg);\n+\tswitch (mbx.msg) {\n+\tcase CPT_MSG_READY:\n+\t\t{\n+\t\t\tcpt_chipid_vfid_t cid;\n+\n+\t\t\tcid.u64 = mbx.data;\n+\t\t\tcptvf->pf_acked = true;\n+\t\t\tcptvf->vfid = cid.s.vfid;\n+\t\t\tcptvf->chip_id = cid.s.chip_id;\n+\t\t\tPMD_DRV_LOG(DEBUG, \"%s: Received VFID %d chip_id %d\\n\",\n+\t\t\t\t cptvf->dev_name,\n+\t\t\t\t cptvf->vfid, cid.s.chip_id);\n+\t\t}\n+\t\tbreak;\n+\tcase CPT_MSG_QBIND_GRP:\n+\t\tcptvf->pf_acked = true;\n+\t\tcptvf->vftype = mbx.data;\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: VF %d type %s group %d\\n\",\n+\t\t\t cptvf->dev_name, cptvf->vfid,\n+\t\t\t ((mbx.data == SE_TYPE) ? \"SE\" : \"AE\"),\n+\t\t\t cptvf->vfgrp);\n+\t\tbreak;\n+\tcase CPT_MBOX_MSG_TYPE_ACK:\n+\t\tcptvf->pf_acked = true;\n+\t\tbreak;\n+\tcase CPT_MBOX_MSG_TYPE_NACK:\n+\t\tcptvf->pf_nacked = true;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(DEBUG, \"%s: Invalid msg from PF, msg 0x%lx\\n\",\n+\t\t\t cptvf->dev_name, mbx.msg);\n+\t\tbreak;\n+\t}\n+}\n+\n+static int32_t\n+cptvf_send_msg_to_pf_timeout(struct cpt_vf *cptvf, cpt_mbox_t *mbx)\n+{\n+\tint timeout = CPT_MBOX_MSG_TIMEOUT;\n+\tint sleep_ms = 10;\n+\n+\tcptvf->pf_acked = false;\n+\tcptvf->pf_nacked = false;\n+\n+\tcptvf_send_msg_to_pf(cptvf, mbx);\n+\n+\t/* Wait for previous message to be acked, timeout 2sec */\n+\twhile (!cptvf->pf_acked) {\n+\t\tif (cptvf->pf_nacked)\n+\t\t\treturn -EINVAL;\n+\t\tusleep(sleep_ms * 1000);\n+\t\tcptvf_poll_misc(cptvf);\n+\t\tif (cptvf->pf_acked)\n+\t\t\tbreak;\n+\t\ttimeout -= sleep_ms;\n+\t\tif (!timeout) {\n+\t\t\tPMD_DRV_LOG(ERR, \"%s: PF didn't ack mbox msg %lx(vfid \"\n+\t\t\t\t \"%u)\\n\",\n+\t\t\t\t cptvf->dev_name,\n+\t\t\t\t (mbx->msg & 0xFF), cptvf->vfid);\n+\t\t\treturn -EBUSY;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * Checks if VF is able to comminicate with PF\n+ * and also gets the CPT number this VF is associated to.\n+ */\n+int cptvf_check_pf_ready(struct cpt_vf *cptvf)\n+{\n+\tcpt_mbox_t mbx = {0, 0};\n+\n+\tmbx.msg = CPT_MSG_READY;\n+\tif (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF didn't respond to READY msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * Communicate VQs size to PF to program CPT(0)_PF_Q(0-15)_CTL of the VF.\n+ * Must be ACKed.\n+ */\n+int cptvf_send_vq_size_msg(struct cpt_vf *cptvf)\n+{\n+\tcpt_mbox_t mbx = {0, 0};\n+\n+\tmbx.msg = CPT_MSG_QLEN;\n+\n+\tmbx.data = cptvf->qsize;\n+\tif (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF didn't respond to vq_size msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * Communicate VF group required to PF and get the VQ binded to that group\n+ */\n+int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf, uint32_t group)\n+{\n+\tcpt_mbox_t mbx = {0, 0};\n+\n+\tmbx.msg = CPT_MSG_QBIND_GRP;\n+\n+\t/* Convey group of the VF */\n+\tmbx.data = group;\n+\tif (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF didn't respond to vf_type msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * Communicate to PF that VF is UP and running\n+ */\n+int cptvf_send_vf_up(struct cpt_vf *cptvf)\n+{\n+\tcpt_mbox_t mbx = {0, 0};\n+\n+\tmbx.msg = CPT_MSG_VF_UP;\n+\tif (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF didn't respond to UP msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * Communicate to PF that VF is DOWN and running\n+ */\n+int cptvf_send_vf_down(struct cpt_vf *cptvf)\n+{\n+\tcpt_mbox_t mbx = {0, 0};\n+\n+\tmbx.msg = CPT_MSG_VF_DOWN;\n+\tif (cptvf_send_msg_to_pf_timeout(cptvf, &mbx)) {\n+\t\tPMD_DRV_LOG(ERR, \"%s: PF didn't respond to DOWN msg\\n\",\n+\t\t\t cptvf->dev_name);\n+\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/cpt/base/cpt_vf_mbox.h b/drivers/crypto/cpt/base/cpt_vf_mbox.h\nnew file mode 100644\nindex 0000000..8e7a05f\n--- /dev/null\n+++ b/drivers/crypto/cpt/base/cpt_vf_mbox.h\n@@ -0,0 +1,60 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Cavium, Inc\n+ */\n+\n+#ifndef __CPTVF_MBOX_H\n+#define __CPTVF_MBOX_H\n+\n+#include \"cpt.h\"\n+#include \"cpt_device.h\"\n+\n+#define CPT_MBOX_MSG_TYPE_REQ\t0\n+#define CPT_MBOX_MSG_TYPE_ACK\t1\n+#define CPT_MBOX_MSG_TYPE_NACK\t2\n+#define CPT_MBOX_MSG_TYPE_NOP\t3\n+\n+typedef enum {\n+\tCPT_MSG_VF_UP = 1,\n+\tCPT_MSG_VF_DOWN,\n+\tCPT_MSG_READY,\n+\tCPT_MSG_QLEN,\n+\tCPT_MSG_QBIND_GRP,\n+\tCPT_MSG_VQ_PRIORITY,\n+\tCPT_MSG_PF_TYPE,\n+} cpt_mbox_opcode_t;\n+\n+/* CPT mailbox structure */\n+typedef struct {\n+\tuint64_t msg; /* Message type MBOX[0] */\n+\tuint64_t data;/* Data MBOX[1] */\n+} cpt_mbox_t;\n+\n+typedef union {\n+\tuint64_t u64;\n+\tstruct {\n+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n+\t\tuint32_t chip_id;\n+\t\tuint8_t vfid;\n+\t\tuint8_t reserved[3];\n+#else\n+\t\tuint8_t reserved[3];\n+\t\tuint8_t vfid;\n+\t\tuint32_t chip_id;\n+#endif\n+\t} s;\n+} cpt_chipid_vfid_t;\n+\n+\n+void cptvf_mbox_send_ack(struct cpt_vf *cptvf, cpt_mbox_t *mbx);\n+void cptvf_mbox_send_nack(struct cpt_vf *cptvf, cpt_mbox_t *mbx);\n+int cptvf_check_pf_ready(struct cpt_vf *cptvf);\n+int cptvf_send_vq_size_msg(struct cpt_vf *cptvf);\n+int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf, uint32_t group);\n+int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf, uint32_t priority);\n+int cptvf_send_vf_down(struct cpt_vf *cptvf);\n+int cptvf_send_vf_up(struct cpt_vf *cptvf);\n+void cptvf_handle_mbox_intr(struct cpt_vf *cptvf);\n+/* Synchronous raw operation to get vf cfg */\n+int cptvf_get_pf_type_raw(char *dev_name, void *reg_base,\n+\t\t\t cpt_pf_type_t *pf_type);\n+#endif /* __CPTVF_MBOX_H */\n", "prefixes": [ "dpdk-dev", "03/16" ] }