Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/35248/?format=api
{ "id": 35248, "url": "http://patches.dpdk.org/api/patches/35248/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-62-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1519112078-20113-62-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1519112078-20113-62-git-send-email-arybchenko@solarflare.com", "date": "2018-02-20T07:34:19", "name": "[dpdk-dev,61/80] net/sfc/base: support FEC mode settings", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d2f6101ae7e046891609dd54a678f09231cae5fb", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1519112078-20113-62-git-send-email-arybchenko@solarflare.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/35248/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/35248/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5665A1B31A;\n\tTue, 20 Feb 2018 08:35:45 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id B468A1B1BD\n\tfor <dev@dpdk.org>; Tue, 20 Feb 2018 08:35:22 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\tB12286C0053 for <dev@dpdk.org>; Tue, 20 Feb 2018 07:35:21 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 19 Feb 2018 23:35:16 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 19 Feb 2018 23:35:15 -0800", "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZEE5025181; Tue, 20 Feb 2018 07:35:14 GMT", "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tw1K7ZBuD020529; Tue, 20 Feb 2018 07:35:14 GMT" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Andy Moreton <amoreton@solarflare.com>", "Date": "Tue, 20 Feb 2018 07:34:19 +0000", "Message-ID": "<1519112078-20113-62-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.2.3", "In-Reply-To": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "References": "<1519112078-20113-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MDID": "1519112122-N0xmOcPr-p48", "Subject": "[dpdk-dev] [PATCH 61/80] net/sfc/base: support FEC mode settings", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Andy Moreton <amoreton@solarflare.com>\n\nMedford2 controllers support control and reporting of\nFEC modes for 25G and higher links. See SF-109306-TC\nfor suggested usage in client code.\n\nSigned-off-by: Andy Moreton <amoreton@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_phy.c | 41 +++++++++++++++++++++++++++++++++++++++++\n drivers/net/sfc/base/efx.h | 6 ++++++\n 2 files changed, 47 insertions(+)", "diff": "diff --git a/drivers/net/sfc/base/ef10_phy.c b/drivers/net/sfc/base/ef10_phy.c\nindex 035099f..84acb70 100644\n--- a/drivers/net/sfc/base/ef10_phy.c\n+++ b/drivers/net/sfc/base/ef10_phy.c\n@@ -34,6 +34,12 @@ mcdi_phy_decode_cap(\n \tCHECK_CAP(ASYM);\n \tCHECK_CAP(AN);\n \tCHECK_CAP(DDM);\n+\tCHECK_CAP(BASER_FEC);\n+\tCHECK_CAP(BASER_FEC_REQUESTED);\n+\tCHECK_CAP(RS_FEC);\n+\tCHECK_CAP(RS_FEC_REQUESTED);\n+\tCHECK_CAP(25G_BASER_FEC);\n+\tCHECK_CAP(25G_BASER_FEC_REQUESTED);\n #undef CHECK_CAP\n \n \tmask = 0;\n@@ -67,6 +73,22 @@ mcdi_phy_decode_cap(\n \tif (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))\n \t\tmask |= (1 << EFX_PHY_CAP_AN);\n \n+\t/* FEC caps (supported on Medford2 and later) */\n+\tif (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN))\n+\t\tmask |= (1 << EFX_PHY_CAP_BASER_FEC);\n+\tif (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN))\n+\t\tmask |= (1 << EFX_PHY_CAP_BASER_FEC_REQUESTED);\n+\n+\tif (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN))\n+\t\tmask |= (1 << EFX_PHY_CAP_RS_FEC);\n+\tif (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN))\n+\t\tmask |= (1 << EFX_PHY_CAP_RS_FEC_REQUESTED);\n+\n+\tif (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN))\n+\t\tmask |= (1 << EFX_PHY_CAP_25G_BASER_FEC);\n+\tif (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN))\n+\t\tmask |= (1 << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);\n+\n \t*maskp = mask;\n }\n \n@@ -323,6 +345,25 @@ ef10_phy_reconfigure(\n \tMCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,\n \t PHY_CAP_100000FDX, (cap_mask >> EFX_PHY_CAP_100000FDX) & 0x1);\n \n+\tMCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,\n+\t PHY_CAP_BASER_FEC, (cap_mask >> EFX_PHY_CAP_BASER_FEC) & 0x1);\n+\tMCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,\n+\t PHY_CAP_BASER_FEC_REQUESTED,\n+\t (cap_mask >> EFX_PHY_CAP_BASER_FEC_REQUESTED) & 0x1);\n+\n+\tMCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,\n+\t PHY_CAP_RS_FEC, (cap_mask >> EFX_PHY_CAP_RS_FEC) & 0x1);\n+\tMCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,\n+\t PHY_CAP_RS_FEC_REQUESTED,\n+\t (cap_mask >> EFX_PHY_CAP_RS_FEC_REQUESTED) & 0x1);\n+\n+\tMCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,\n+\t PHY_CAP_25G_BASER_FEC,\n+\t (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC) & 0x1);\n+\tMCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,\n+\t PHY_CAP_25G_BASER_FEC_REQUESTED,\n+\t (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) & 0x1);\n+\n #if EFSYS_OPT_LOOPBACK\n \tMCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,\n \t\t epp->ep_loopback_type);\ndiff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex 5cb3fd0..33e7875 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -876,6 +876,12 @@ typedef enum efx_phy_cap_type_e {\n \tEFX_PHY_CAP_100000FDX,\n \tEFX_PHY_CAP_25000FDX,\n \tEFX_PHY_CAP_50000FDX,\n+\tEFX_PHY_CAP_BASER_FEC,\n+\tEFX_PHY_CAP_BASER_FEC_REQUESTED,\n+\tEFX_PHY_CAP_RS_FEC,\n+\tEFX_PHY_CAP_RS_FEC_REQUESTED,\n+\tEFX_PHY_CAP_25G_BASER_FEC,\n+\tEFX_PHY_CAP_25G_BASER_FEC_REQUESTED,\n \tEFX_PHY_CAP_NTYPES\n } efx_phy_cap_type_t;\n \n", "prefixes": [ "dpdk-dev", "61/80" ] }