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[
    {
        "id": 960,
        "web_url": "http://patches.dpdk.org/comment/960/",
        "msgid": "<1855491.X6obi8qxOV@xps13>",
        "date": "2014-09-24T15:18:09",
        "subject": "Re: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier",
        "submitter": {
            "id": 1,
            "url": "http://patches.dpdk.org/api/people/1/",
            "name": "Thomas Monjalon",
            "email": "thomas.monjalon@6wind.com"
        },
        "content": "2014-09-11 07:48, Hiroshi Shimamoto:\n> x86 can keep store ordering with standard operations.\n\nAre we sure it's always the case (including old 32-bit CPU)?\nI would prefer to have a reference here. I know we already discussed\nthis kind of things but having a reference in commit log could help\nfor future discussions.\n\n> Using memory barrier is much expensive in main packet processing loop.\n> Removing this improves xmit/recv packet performance.\n> \n> We can see performance improvements with memnic-tester.\n> Using Xeon E5-2697 v2 @ 2.70GHz, 4 vCPU.\n>  size |  before  |  after\n>    64 | 4.18Mpps | 4.59Mpps\n>   128 | 3.85Mpps | 4.87Mpps\n>   256 | 4.01Mpps | 4.72Mpps\n>   512 | 3.52Mpps | 4.41Mpps\n>  1024 | 3.18Mpps | 3.64Mpps\n>  1280 | 2.86Mpps | 3.15Mpps\n>  1518 | 2.59Mpps | 2.87Mpps\n> \n> Note: we have to take care if we use temporal cache.\n\nPlease, could you explain this last sentence?\n\nThanks",
        "headers": {
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            "References": "<7F861DC0615E0C47A872E6F3C5FCDDBD011A9934@BPXM14GP.gisp.nec.co.jp>",
            "X-Mailman-Version": "2.1.15",
            "Date": "Wed, 24 Sep 2014 17:18:09 +0200",
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            "To": "dev@dpdk.org, Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com>",
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                "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 2D4ABAFCA;\n\tWed, 24 Sep 2014 17:12:06 +0200 (CEST)",
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                "from xps13.localnet (136-92-190-109.dsl.ovh.fr. [109.190.92.136])\n\tby mx.google.com with ESMTPSA id\n\tec18sm57685wic.0.2014.09.24.08.18.16 for <multiple recipients>\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 24 Sep 2014 08:18:17 -0700 (PDT)"
            ],
            "Subject": "Re: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier",
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            "From": "Thomas Monjalon <thomas.monjalon@6wind.com>",
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            "Cc": "Hayato Momma <h-momma@ce.jp.nec.com>",
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    },
    {
        "id": 978,
        "web_url": "http://patches.dpdk.org/comment/978/",
        "msgid": "<7F861DC0615E0C47A872E6F3C5FCDDBD02AD9F40@BPXM14GP.gisp.nec.co.jp>",
        "date": "2014-09-25T00:35:51",
        "subject": "Re: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier",
        "submitter": {
            "id": 38,
            "url": "http://patches.dpdk.org/api/people/38/",
            "name": "Hiroshi Shimamoto",
            "email": "h-shimamoto@ct.jp.nec.com"
        },
        "content": "> Subject: Re: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier\n> \n> 2014-09-11 07:48, Hiroshi Shimamoto:\n> > x86 can keep store ordering with standard operations.\n> \n> Are we sure it's always the case (including old 32-bit CPU)?\n> I would prefer to have a reference here. I know we already discussed\n> this kind of things but having a reference in commit log could help\n> for future discussions.\n> \n> > Using memory barrier is much expensive in main packet processing loop.\n> > Removing this improves xmit/recv packet performance.\n> >\n> > We can see performance improvements with memnic-tester.\n> > Using Xeon E5-2697 v2 @ 2.70GHz, 4 vCPU.\n> >  size |  before  |  after\n> >    64 | 4.18Mpps | 4.59Mpps\n> >   128 | 3.85Mpps | 4.87Mpps\n> >   256 | 4.01Mpps | 4.72Mpps\n> >   512 | 3.52Mpps | 4.41Mpps\n> >  1024 | 3.18Mpps | 3.64Mpps\n> >  1280 | 2.86Mpps | 3.15Mpps\n> >  1518 | 2.59Mpps | 2.87Mpps\n> >\n> > Note: we have to take care if we use temporal cache.\n> \n> Please, could you explain this last sentence?\n\nOops, I have mistaken the word, \"temporal\" should be \"non-temporal\".\n\nBy the way, there are some instructions which use non-temporal\ncache liek MOVNTx series.\nThe store ordering of these instructions is not kept.\n\nRef. Intel Software Developer Manual\n Vol.1 10.4.6.2 Caching of Temporal vs. Non-Temporal Data\n Vol.3 8.2 Memory Ordering\n\nthanks,\nHiroshi\n\n> \n> Thanks\n> --\n> Thomas",
        "headers": {
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            "References": "<7F861DC0615E0C47A872E6F3C5FCDDBD011A9934@BPXM14GP.gisp.nec.co.jp>\n\t<1855491.X6obi8qxOV@xps13>",
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            "Date": "Thu, 25 Sep 2014 00:35:51 +0000",
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            ],
            "Subject": "Re: [dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier",
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            "From": "Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com>",
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            "Thread-Topic": "[dpdk-dev] [memnic PATCH 4/7] pmd: use compiler barrier",
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