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GET /api/patches/29618/?format=api
{ "id": 29618, "url": "http://patches.dpdk.org/api/patches/29618/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/b9d099ed6b799be69e4b3a8e164a5eb7e2b2526e.1507141616.git.adrien.mazarguil@6wind.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<b9d099ed6b799be69e4b3a8e164a5eb7e2b2526e.1507141616.git.adrien.mazarguil@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/b9d099ed6b799be69e4b3a8e164a5eb7e2b2526e.1507141616.git.adrien.mazarguil@6wind.com", "date": "2017-10-04T18:48:57", "name": "[dpdk-dev,v3,5/6] net/mlx4: restore Rx offloads", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5617a34c6d04bf42e07d3e976b382feb035a48f8", "submitter": { "id": 165, "url": "http://patches.dpdk.org/api/people/165/?format=api", "name": "Adrien Mazarguil", "email": "adrien.mazarguil@6wind.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/b9d099ed6b799be69e4b3a8e164a5eb7e2b2526e.1507141616.git.adrien.mazarguil@6wind.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/29618/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/29618/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C2A0D1B6F8;\n\tWed, 4 Oct 2017 20:49:28 +0200 (CEST)", "from mail-wm0-f54.google.com (mail-wm0-f54.google.com\n\t[74.125.82.54]) by dpdk.org (Postfix) with ESMTP id B1AC01B6DD\n\tfor <dev@dpdk.org>; Wed, 4 Oct 2017 20:49:22 +0200 (CEST)", "by mail-wm0-f54.google.com with SMTP id u138so25010555wmu.4\n\tfor <dev@dpdk.org>; Wed, 04 Oct 2017 11:49:22 -0700 (PDT)", "from 6wind.com (host.78.145.23.62.rev.coltfrance.com.\n\t[62.23.145.78]) by smtp.gmail.com with ESMTPSA id\n\tg30sm16124189edb.63.2017.10.04.11.49.20\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 04 Oct 2017 11:49:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=ykzKBHglMH/LuP7sdp+5F7QbMZshvBoKVxkQDusPwHo=;\n\tb=XHvbHU9CxlQSqg82hdTOGvjyKP5FpnDFlz5kQ73QzYmtw3WB30wdjrLFVtPXpRMg6j\n\teJzoEUOt2m0lpo1DIskI6zdtjCD2OHvzl7Z0KYGhYN6QeoD0CcmajyFKc4v10LtsfNzu\n\tj7hOY+dgsZ9hh40a0xYj6mlmGG7pKUQrOWX8Il/IGWmyONNq8xY3IpcYgE5z8wHLOe+d\n\teazq5cs4K1NfgMAfZhliVFKsv9fiOc/SCJL+4Qi2Y9/qPWvM7OaDrxaoHT0jfOzxR05Y\n\tDFxWN9o6enuSIIC6+qXBhCaCu+CwB5jzn10UAiwRXk+MFAIHxa7Hjd3LM/gQOHhNfN4O\n\tjScg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=ykzKBHglMH/LuP7sdp+5F7QbMZshvBoKVxkQDusPwHo=;\n\tb=N0Mx0oxFRJjKsm5JBZu1SZpwyWYkF2HjGdSbhPkojo4LFLX9wpbDUVfYH1a2ziHQBh\n\t3lsyM5W9abmNl9bMmcCwvS9F+J8mUNV+yhDapIKWqnJKwilnKDYpdPAFNUbt3ov9C0WI\n\tKw13B1c5lyCusHjj9QArMhtkL8jj1WVgEhWlTU34mBQUt8tmwKgoRv/UjtCr9Vuca7D9\n\tem8C6oix11QX+iy1aBxLvuVDuhzUmcUdPyUbx8I8kMAGNzS70xKLzlDNBUnvwfRzbxg5\n\tSAYwDYXpzQKBADwEG1JbKqNSbCKBj8jFwsArJDRw7o3QLPBmkZNdu/rcr/XmWimeZDKR\n\txjVw==", "X-Gm-Message-State": "AHPjjUiqwK3x9bgsdwGOt9TfiSAUMQljz0GI+c/Q+40FkNjNMSIweUbd\n\t0ifjDpfpCUDzwZ81CuHY9FHvs6zn", "X-Google-Smtp-Source": "AOwi7QCJaQPf7w26MPSCKe/4XAtU3c9t0BqG/eE1KzP7xFILA5OKujXfEBCNO3MjieaFKEM0rKLNUg==", "X-Received": "by 10.80.191.65 with SMTP id g1mr29480475edk.243.1507142962033; \n\tWed, 04 Oct 2017 11:49:22 -0700 (PDT)", "From": "Adrien Mazarguil <adrien.mazarguil@6wind.com>", "To": "dev@dpdk.org", "Cc": "Moti Haimovsky <motih@mellanox.com>, Matan Azrad <matan@mellanox.com>,\n\tVasily Philipov <vasilyf@mellanox.com>", "Date": "Wed, 4 Oct 2017 20:48:57 +0200", "Message-Id": "<b9d099ed6b799be69e4b3a8e164a5eb7e2b2526e.1507141616.git.adrien.mazarguil@6wind.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<cover.1507141616.git.adrien.mazarguil@6wind.com>", "References": "<1507027711-879-1-git-send-email-matan@mellanox.com>\n\t<cover.1507141616.git.adrien.mazarguil@6wind.com>", "Subject": "[dpdk-dev] [PATCH v3 5/6] net/mlx4: restore Rx offloads", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Moti Haimovsky <motih@mellanox.com>\n\nThis patch adds hardware offloading support for IPV4, UDP and TCP checksum\nverification, including inner/outer checksums on supported tunnel types.\n\nIt also restores packet type recognition support.\n\nSigned-off-by: Vasily Philipov <vasilyf@mellanox.com>\nSigned-off-by: Moti Haimovsky <motih@mellanox.com>\nAcked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n---\n drivers/net/mlx4/mlx4_ethdev.c | 6 +-\n drivers/net/mlx4/mlx4_prm.h | 30 +++++++++\n drivers/net/mlx4/mlx4_rxq.c | 5 ++\n drivers/net/mlx4/mlx4_rxtx.c | 118 +++++++++++++++++++++++++++++++++++-\n drivers/net/mlx4/mlx4_rxtx.h | 2 +\n 5 files changed, 158 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx4/mlx4_ethdev.c b/drivers/net/mlx4/mlx4_ethdev.c\nindex bec1787..6dbf273 100644\n--- a/drivers/net/mlx4/mlx4_ethdev.c\n+++ b/drivers/net/mlx4/mlx4_ethdev.c\n@@ -553,10 +553,14 @@ mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n \tinfo->max_mac_addrs = 1;\n \tinfo->rx_offload_capa = 0;\n \tinfo->tx_offload_capa = 0;\n-\tif (priv->hw_csum)\n+\tif (priv->hw_csum) {\n \t\tinfo->tx_offload_capa |= (DEV_TX_OFFLOAD_IPV4_CKSUM |\n \t\t\t\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n \t\t\t\t\t DEV_TX_OFFLOAD_TCP_CKSUM);\n+\t\tinfo->rx_offload_capa |= (DEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\t\t DEV_RX_OFFLOAD_TCP_CKSUM);\n+\t}\n \tif (priv->hw_csum_l2tun)\n \t\tinfo->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;\n \tif (mlx4_get_ifname(priv, &ifname) == 0)\ndiff --git a/drivers/net/mlx4/mlx4_prm.h b/drivers/net/mlx4/mlx4_prm.h\nindex df5a6b4..0d76a73 100644\n--- a/drivers/net/mlx4/mlx4_prm.h\n+++ b/drivers/net/mlx4/mlx4_prm.h\n@@ -70,6 +70,14 @@\n #define MLX4_SIZE_TO_TXBBS(size) \\\n \t(RTE_ALIGN((size), (MLX4_TXBB_SIZE)) >> (MLX4_TXBB_SHIFT))\n \n+/* CQE checksum flags. */\n+enum {\n+\tMLX4_CQE_L2_TUNNEL_IPV4 = (int)(1u << 25),\n+\tMLX4_CQE_L2_TUNNEL_L4_CSUM = (int)(1u << 26),\n+\tMLX4_CQE_L2_TUNNEL = (int)(1u << 27),\n+\tMLX4_CQE_L2_TUNNEL_IPOK = (int)(1u << 31),\n+};\n+\n /* Send queue information. */\n struct mlx4_sq {\n \tuint8_t *buf; /**< SQ buffer. */\n@@ -119,4 +127,26 @@ mlx4_get_cqe(struct mlx4_cq *cq, uint32_t index)\n \t\t\t\t (cq->cqe_64 << 5));\n }\n \n+/**\n+ * Transpose a flag in a value.\n+ *\n+ * @param val\n+ * Input value.\n+ * @param from\n+ * Flag to retrieve from input value.\n+ * @param to\n+ * Flag to set in output value.\n+ *\n+ * @return\n+ * Output value with transposed flag enabled if present on input.\n+ */\n+static inline uint64_t\n+mlx4_transpose(uint64_t val, uint64_t from, uint64_t to)\n+{\n+\treturn (from >= to ?\n+\t\t(val & from) / (from / to) :\n+\t\t(val & from) * (to / from));\n+}\n+\n+\n #endif /* MLX4_PRM_H_ */\ndiff --git a/drivers/net/mlx4/mlx4_rxq.c b/drivers/net/mlx4/mlx4_rxq.c\nindex 44d095d..a021a32 100644\n--- a/drivers/net/mlx4/mlx4_rxq.c\n+++ b/drivers/net/mlx4/mlx4_rxq.c\n@@ -260,6 +260,11 @@ mlx4_rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,\n \tint ret;\n \n \t(void)conf; /* Thresholds configuration (ignored). */\n+\t/* Toggle Rx checksum offload if hardware supports it. */\n+\tif (priv->hw_csum)\n+\t\ttmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n+\tif (priv->hw_csum_l2tun)\n+\t\ttmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n \tmb_len = rte_pktmbuf_data_room_size(mp);\n \tif (desc == 0) {\n \t\trte_errno = EINVAL;\ndiff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c\nindex fe7d5d0..87c5261 100644\n--- a/drivers/net/mlx4/mlx4_rxtx.c\n+++ b/drivers/net/mlx4/mlx4_rxtx.c\n@@ -557,6 +557,107 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n }\n \n /**\n+ * Translate Rx completion flags to packet type.\n+ *\n+ * @param flags\n+ * Rx completion flags returned by mlx4_cqe_flags().\n+ *\n+ * @return\n+ * Packet type in mbuf format.\n+ */\n+static inline uint32_t\n+rxq_cq_to_pkt_type(uint32_t flags)\n+{\n+\tuint32_t pkt_type;\n+\n+\tif (flags & MLX4_CQE_L2_TUNNEL)\n+\t\tpkt_type =\n+\t\t\tmlx4_transpose(flags,\n+\t\t\t\t MLX4_CQE_L2_TUNNEL_IPV4,\n+\t\t\t\t RTE_PTYPE_L3_IPV4_EXT_UNKNOWN) |\n+\t\t\tmlx4_transpose(flags,\n+\t\t\t\t MLX4_CQE_STATUS_IPV4_PKT,\n+\t\t\t\t RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN);\n+\telse\n+\t\tpkt_type = mlx4_transpose(flags,\n+\t\t\t\t\t MLX4_CQE_STATUS_IPV4_PKT,\n+\t\t\t\t\t RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);\n+\treturn pkt_type;\n+}\n+\n+/**\n+ * Translate Rx completion flags to offload flags.\n+ *\n+ * @param flags\n+ * Rx completion flags returned by mlx4_cqe_flags().\n+ * @param csum\n+ * Whether Rx checksums are enabled.\n+ * @param csum_l2tun\n+ * Whether Rx L2 tunnel checksums are enabled.\n+ *\n+ * @return\n+ * Offload flags (ol_flags) in mbuf format.\n+ */\n+static inline uint32_t\n+rxq_cq_to_ol_flags(uint32_t flags, int csum, int csum_l2tun)\n+{\n+\tuint32_t ol_flags = 0;\n+\n+\tif (csum)\n+\t\tol_flags |=\n+\t\t\tmlx4_transpose(flags,\n+\t\t\t\t MLX4_CQE_STATUS_IP_HDR_CSUM_OK,\n+\t\t\t\t PKT_RX_IP_CKSUM_GOOD) |\n+\t\t\tmlx4_transpose(flags,\n+\t\t\t\t MLX4_CQE_STATUS_TCP_UDP_CSUM_OK,\n+\t\t\t\t PKT_RX_L4_CKSUM_GOOD);\n+\tif ((flags & MLX4_CQE_L2_TUNNEL) && csum_l2tun)\n+\t\tol_flags |=\n+\t\t\tmlx4_transpose(flags,\n+\t\t\t\t MLX4_CQE_L2_TUNNEL_IPOK,\n+\t\t\t\t PKT_RX_IP_CKSUM_GOOD) |\n+\t\t\tmlx4_transpose(flags,\n+\t\t\t\t MLX4_CQE_L2_TUNNEL_L4_CSUM,\n+\t\t\t\t PKT_RX_L4_CKSUM_GOOD);\n+\treturn ol_flags;\n+}\n+\n+/**\n+ * Extract checksum information from CQE flags.\n+ *\n+ * @param cqe\n+ * Pointer to CQE structure.\n+ * @param csum\n+ * Whether Rx checksums are enabled.\n+ * @param csum_l2tun\n+ * Whether Rx L2 tunnel checksums are enabled.\n+ *\n+ * @return\n+ * CQE checksum information.\n+ */\n+static inline uint32_t\n+mlx4_cqe_flags(struct mlx4_cqe *cqe, int csum, int csum_l2tun)\n+{\n+\tuint32_t flags = 0;\n+\n+\t/*\n+\t * The relevant bits are in different locations on their\n+\t * CQE fields therefore we can join them in one 32bit\n+\t * variable.\n+\t */\n+\tif (csum)\n+\t\tflags = (rte_be_to_cpu_32(cqe->status) &\n+\t\t\t MLX4_CQE_STATUS_IPV4_CSUM_OK);\n+\tif (csum_l2tun)\n+\t\tflags |= (rte_be_to_cpu_32(cqe->vlan_my_qpn) &\n+\t\t\t (MLX4_CQE_L2_TUNNEL |\n+\t\t\t MLX4_CQE_L2_TUNNEL_IPOK |\n+\t\t\t MLX4_CQE_L2_TUNNEL_L4_CSUM |\n+\t\t\t MLX4_CQE_L2_TUNNEL_IPV4));\n+\treturn flags;\n+}\n+\n+/**\n * Poll one CQE from CQ.\n *\n * @param rxq\n@@ -664,8 +765,21 @@ mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t\t\tgoto skip;\n \t\t\t}\n \t\t\tpkt = seg;\n-\t\t\tpkt->packet_type = 0;\n-\t\t\tpkt->ol_flags = 0;\n+\t\t\tif (rxq->csum | rxq->csum_l2tun) {\n+\t\t\t\tuint32_t flags =\n+\t\t\t\t\tmlx4_cqe_flags(cqe,\n+\t\t\t\t\t\t rxq->csum,\n+\t\t\t\t\t\t rxq->csum_l2tun);\n+\n+\t\t\t\tpkt->ol_flags =\n+\t\t\t\t\trxq_cq_to_ol_flags(flags,\n+\t\t\t\t\t\t\t rxq->csum,\n+\t\t\t\t\t\t\t rxq->csum_l2tun);\n+\t\t\t\tpkt->packet_type = rxq_cq_to_pkt_type(flags);\n+\t\t\t} else {\n+\t\t\t\tpkt->packet_type = 0;\n+\t\t\t\tpkt->ol_flags = 0;\n+\t\t\t}\n \t\t\tpkt->pkt_len = len;\n \t\t}\n \t\trep->nb_segs = 1;\ndiff --git a/drivers/net/mlx4/mlx4_rxtx.h b/drivers/net/mlx4/mlx4_rxtx.h\nindex a742f61..6aad41a 100644\n--- a/drivers/net/mlx4/mlx4_rxtx.h\n+++ b/drivers/net/mlx4/mlx4_rxtx.h\n@@ -77,6 +77,8 @@ struct rxq {\n \tstruct rte_mbuf *(*elts)[]; /**< Rx elements. */\n \tvolatile struct mlx4_wqe_data_seg (*wqes)[]; /**< HW queue entries. */\n \tvolatile uint32_t *rq_db; /**< RQ doorbell record. */\n+\tuint32_t csum:1; /**< Enable checksum offloading. */\n+\tuint32_t csum_l2tun:1; /**< Same for L2 tunnels. */\n \tstruct mlx4_cq mcq; /**< Info for directly manipulating the CQ. */\n \tstruct mlx4_rxq_stats stats; /**< Rx queue counters. */\n \tunsigned int socket; /**< CPU socket ID for allocations. */\n", "prefixes": [ "dpdk-dev", "v3", "5/6" ] }