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GET /api/patches/29251/?format=api
{ "id": 29251, "url": "http://patches.dpdk.org/api/patches/29251/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20170928113344.12248-8-shreyansh.jain@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20170928113344.12248-8-shreyansh.jain@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20170928113344.12248-8-shreyansh.jain@nxp.com", "date": "2017-09-28T11:33:11", "name": "[dpdk-dev,v5,07/40] bus/dpaa: enable DPAA IOCTL portal driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ef50a025c3c645f77f8218353f604f43a5b53835", "submitter": { "id": 497, "url": "http://patches.dpdk.org/api/people/497/?format=api", "name": "Shreyansh Jain", "email": "shreyansh.jain@nxp.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20170928113344.12248-8-shreyansh.jain@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/29251/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/29251/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 23B461B1B8;\n\tThu, 28 Sep 2017 13:23:18 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0070.outbound.protection.outlook.com [104.47.41.70])\n\tby dpdk.org (Postfix) with ESMTP id 9BAE03977\n\tfor <dev@dpdk.org>; Thu, 28 Sep 2017 13:23:10 +0200 (CEST)", "from BLUPR0301CA0037.namprd03.prod.outlook.com (10.162.113.175) by\n\tDM5PR03MB2698.namprd03.prod.outlook.com (10.168.197.136) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Thu, 28 Sep 2017 11:23:09 +0000", "from BL2FFO11FD028.protection.gbl (2a01:111:f400:7c09::158) by\n\tBLUPR0301CA0037.outlook.office365.com (2a01:111:e400:5259::47) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.56.11 via\n\tFrontend Transport; Thu, 28 Sep 2017 11:23:09 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBL2FFO11FD028.mail.protection.outlook.com (10.173.161.107) with\n\tMicrosoft\n\tSMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id\n\t15.20.56.11 via Frontend Transport; Thu, 28 Sep 2017 11:23:08 +0000", "from Tophie.ap.freescale.net ([10.232.14.39])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv8SBMpFh016035; Thu, 28 Sep 2017 04:23:06 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Shreyansh Jain <shreyansh.jain@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <hemant.agrawal@nxp.com>", "Date": "Thu, 28 Sep 2017 17:03:11 +0530", "Message-ID": "<20170928113344.12248-8-shreyansh.jain@nxp.com>", "X-Mailer": "git-send-email 2.9.3", "In-Reply-To": "<20170928113344.12248-1-shreyansh.jain@nxp.com>", "References": "<20170909112132.13936-1-shreyansh.jain@nxp.com>\n\t<20170928113344.12248-1-shreyansh.jain@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131510713892323611;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(22001)(2017052603199)(201703131430075)(201703131517081);\n\tSRVR:DM5PR03MB2698; ", "X-MS-TrafficTypeDiagnostic": "DM5PR03MB2698:", "X-Exchange-Antispam-Report-Test": "UriScan:(278428928389397)(35073007944872)(185117386973197)(227817650892897)(275809806118684);", "X-Microsoft-Antispam-PRVS": "<DM5PR03MB26989DDEC4EA6FFD95F9480F90790@DM5PR03MB2698.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(8121501046)(5005006)(10201501046)(93006095)(93001095)(100000703101)(100105400095)(3002001)(6055026)(6096035)(20161123565025)(20161123559100)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123556025)(20161123563025)(20161123561025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:DM5PR03MB2698; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:DM5PR03MB2698; ", "X-Forefront-PRVS": "0444EB1997", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Sep 2017 11:23:08.9359\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR03MB2698", "Subject": "[dpdk-dev] [PATCH v5 07/40] bus/dpaa: enable DPAA IOCTL portal\n\tdriver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Userspace applications interact with DPAA blocks using this IOCTL driver.\n\nSigned-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\nSigned-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>\n---\n drivers/bus/dpaa/Makefile | 4 +-\n drivers/bus/dpaa/base/qbman/process.c | 331 ++++++++++++++++++++++++++++++++++\n drivers/bus/dpaa/include/fsl_usd.h | 88 +++++++++\n drivers/bus/dpaa/include/process.h | 107 +++++++++++\n 4 files changed, 529 insertions(+), 1 deletion(-)\n create mode 100644 drivers/bus/dpaa/base/qbman/process.c\n create mode 100644 drivers/bus/dpaa/include/fsl_usd.h\n create mode 100644 drivers/bus/dpaa/include/process.h", "diff": "diff --git a/drivers/bus/dpaa/Makefile b/drivers/bus/dpaa/Makefile\nindex fe65276..f06521c 100644\n--- a/drivers/bus/dpaa/Makefile\n+++ b/drivers/bus/dpaa/Makefile\n@@ -43,6 +43,7 @@ CFLAGS += -Wno-cast-qual\n CFLAGS += -D _GNU_SOURCE\n CFLAGS += -I$(RTE_BUS_DPAA)/\n CFLAGS += -I$(RTE_BUS_DPAA)/include\n+CFLAGS += -I$(RTE_BUS_DPAA)/base/qbman\n CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal\n CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common/include\n \n@@ -60,7 +61,8 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA_BUS) += \\\n \tbase/fman/fman.c \\\n \tbase/fman/fman_hw.c \\\n \tbase/fman/of.c \\\n-\tbase/fman/netcfg_layer.c\n+\tbase/fman/netcfg_layer.c \\\n+\tbase/qbman/process.c\n \n # Link Pthread\n LDLIBS += -lpthread\ndiff --git a/drivers/bus/dpaa/base/qbman/process.c b/drivers/bus/dpaa/base/qbman/process.c\nnew file mode 100644\nindex 0000000..b8ec539\n--- /dev/null\n+++ b/drivers/bus/dpaa/base/qbman/process.c\n@@ -0,0 +1,331 @@\n+/*-\n+ * This file is provided under a dual BSD/GPLv2 license. When using or\n+ * redistributing this file, you may do so under either license.\n+ *\n+ * BSD LICENSE\n+ *\n+ * Copyright 2011-2016 Freescale Semiconductor Inc.\n+ * Copyright 2017 NXP.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ * GPL LICENSE SUMMARY\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+#include <assert.h>\n+#include <fcntl.h>\n+#include <unistd.h>\n+#include <sys/ioctl.h>\n+\n+#include \"process.h\"\n+\n+#include <fsl_usd.h>\n+\n+/* As higher-level drivers will be built on top of this (dma_mem, qbman, ...),\n+ * it's preferable that the process driver itself not provide any exported API.\n+ * As such, combined with the fact that none of these operations are\n+ * performance critical, it is justified to use lazy initialisation, so that's\n+ * what the lock is for.\n+ */\n+static int fd = -1;\n+static pthread_mutex_t fd_init_lock = PTHREAD_MUTEX_INITIALIZER;\n+\n+static int check_fd(void)\n+{\n+\tint ret;\n+\n+\tif (fd >= 0)\n+\t\treturn 0;\n+\tret = pthread_mutex_lock(&fd_init_lock);\n+\tassert(!ret);\n+\t/* check again with the lock held */\n+\tif (fd < 0)\n+\t\tfd = open(PROCESS_PATH, O_RDWR);\n+\tret = pthread_mutex_unlock(&fd_init_lock);\n+\tassert(!ret);\n+\treturn (fd >= 0) ? 0 : -ENODEV;\n+}\n+\n+#define DPAA_IOCTL_MAGIC 'u'\n+struct dpaa_ioctl_id_alloc {\n+\tuint32_t base; /* Return value, the start of the allocated range */\n+\tenum dpaa_id_type id_type; /* what kind of resource(s) to allocate */\n+\tuint32_t num; /* how many IDs to allocate (and return value) */\n+\tuint32_t align; /* must be a power of 2, 0 is treated like 1 */\n+\tint partial; /* whether to allow less than 'num' */\n+};\n+\n+struct dpaa_ioctl_id_release {\n+\t/* Input; */\n+\tenum dpaa_id_type id_type;\n+\tuint32_t base;\n+\tuint32_t num;\n+};\n+\n+struct dpaa_ioctl_id_reserve {\n+\tenum dpaa_id_type id_type;\n+\tuint32_t base;\n+\tuint32_t num;\n+};\n+\n+#define DPAA_IOCTL_ID_ALLOC \\\n+\t_IOWR(DPAA_IOCTL_MAGIC, 0x01, struct dpaa_ioctl_id_alloc)\n+#define DPAA_IOCTL_ID_RELEASE \\\n+\t_IOW(DPAA_IOCTL_MAGIC, 0x02, struct dpaa_ioctl_id_release)\n+#define DPAA_IOCTL_ID_RESERVE \\\n+\t_IOW(DPAA_IOCTL_MAGIC, 0x0A, struct dpaa_ioctl_id_reserve)\n+\n+int process_alloc(enum dpaa_id_type id_type, uint32_t *base, uint32_t num,\n+\t\t uint32_t align, int partial)\n+{\n+\tstruct dpaa_ioctl_id_alloc id = {\n+\t\t.id_type = id_type,\n+\t\t.num = num,\n+\t\t.align = align,\n+\t\t.partial = partial\n+\t};\n+\tint ret = check_fd();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\tret = ioctl(fd, DPAA_IOCTL_ID_ALLOC, &id);\n+\tif (ret)\n+\t\treturn ret;\n+\tfor (ret = 0; ret < (int)id.num; ret++)\n+\t\tbase[ret] = id.base + ret;\n+\treturn id.num;\n+}\n+\n+void process_release(enum dpaa_id_type id_type, uint32_t base, uint32_t num)\n+{\n+\tstruct dpaa_ioctl_id_release id = {\n+\t\t.id_type = id_type,\n+\t\t.base = base,\n+\t\t.num = num\n+\t};\n+\tint ret = check_fd();\n+\n+\tif (ret) {\n+\t\tfprintf(stderr, \"Process FD failure\\n\");\n+\t\treturn;\n+\t}\n+\tret = ioctl(fd, DPAA_IOCTL_ID_RELEASE, &id);\n+\tif (ret)\n+\t\tfprintf(stderr, \"Process FD ioctl failure type %d base 0x%x num %d\\n\",\n+\t\t\tid_type, base, num);\n+}\n+\n+int process_reserve(enum dpaa_id_type id_type, uint32_t base, uint32_t num)\n+{\n+\tstruct dpaa_ioctl_id_reserve id = {\n+\t\t.id_type = id_type,\n+\t\t.base = base,\n+\t\t.num = num\n+\t};\n+\tint ret = check_fd();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\treturn ioctl(fd, DPAA_IOCTL_ID_RESERVE, &id);\n+}\n+\n+/***************************************/\n+/* Mapping and using QMan/BMan portals */\n+/***************************************/\n+\n+#define DPAA_IOCTL_PORTAL_MAP \\\n+\t_IOWR(DPAA_IOCTL_MAGIC, 0x07, struct dpaa_ioctl_portal_map)\n+#define DPAA_IOCTL_PORTAL_UNMAP \\\n+\t_IOW(DPAA_IOCTL_MAGIC, 0x08, struct dpaa_portal_map)\n+\n+int process_portal_map(struct dpaa_ioctl_portal_map *params)\n+{\n+\tint ret = check_fd();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ioctl(fd, DPAA_IOCTL_PORTAL_MAP, params);\n+\tif (ret) {\n+\t\tperror(\"ioctl(DPAA_IOCTL_PORTAL_MAP)\");\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+int process_portal_unmap(struct dpaa_portal_map *map)\n+{\n+\tint ret = check_fd();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ioctl(fd, DPAA_IOCTL_PORTAL_UNMAP, map);\n+\tif (ret) {\n+\t\tperror(\"ioctl(DPAA_IOCTL_PORTAL_UNMAP)\");\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+#define DPAA_IOCTL_PORTAL_IRQ_MAP \\\n+\t_IOW(DPAA_IOCTL_MAGIC, 0x09, struct dpaa_ioctl_irq_map)\n+\n+int process_portal_irq_map(int ifd, struct dpaa_ioctl_irq_map *map)\n+{\n+\tmap->fd = fd;\n+\treturn ioctl(ifd, DPAA_IOCTL_PORTAL_IRQ_MAP, map);\n+}\n+\n+int process_portal_irq_unmap(int ifd)\n+{\n+\treturn close(ifd);\n+}\n+\n+struct dpaa_ioctl_raw_portal {\n+\t/* inputs */\n+\tenum dpaa_portal_type type; /* Type of portal to allocate */\n+\n+\tuint8_t enable_stash; /* set to non zero to turn on stashing */\n+\t/* Stashing attributes for the portal */\n+\tuint32_t cpu;\n+\tuint32_t cache;\n+\tuint32_t window;\n+\t/* Specifies the stash request queue this portal should use */\n+\tuint8_t sdest;\n+\n+\t/* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX\n+\t * for don't care. The portal index will be populated by the\n+\t * driver when the ioctl() successfully completes.\n+\t */\n+\tuint32_t index;\n+\n+\t/* outputs */\n+\tuint64_t cinh;\n+\tuint64_t cena;\n+};\n+\n+#define DPAA_IOCTL_ALLOC_RAW_PORTAL \\\n+\t_IOWR(DPAA_IOCTL_MAGIC, 0x0C, struct dpaa_ioctl_raw_portal)\n+\n+#define DPAA_IOCTL_FREE_RAW_PORTAL \\\n+\t_IOR(DPAA_IOCTL_MAGIC, 0x0D, struct dpaa_ioctl_raw_portal)\n+\n+static int process_portal_allocate(struct dpaa_ioctl_raw_portal *portal)\n+{\n+\tint ret = check_fd();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ioctl(fd, DPAA_IOCTL_ALLOC_RAW_PORTAL, portal);\n+\tif (ret) {\n+\t\tperror(\"ioctl(DPAA_IOCTL_ALLOC_RAW_PORTAL)\");\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+static int process_portal_free(struct dpaa_ioctl_raw_portal *portal)\n+{\n+\tint ret = check_fd();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ioctl(fd, DPAA_IOCTL_FREE_RAW_PORTAL, portal);\n+\tif (ret) {\n+\t\tperror(\"ioctl(DPAA_IOCTL_FREE_RAW_PORTAL)\");\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+int qman_allocate_raw_portal(struct dpaa_raw_portal *portal)\n+{\n+\tstruct dpaa_ioctl_raw_portal input;\n+\tint ret;\n+\n+\tinput.type = dpaa_portal_qman;\n+\tinput.index = portal->index;\n+\tinput.enable_stash = portal->enable_stash;\n+\tinput.cpu = portal->cpu;\n+\tinput.cache = portal->cache;\n+\tinput.window = portal->window;\n+\tinput.sdest = portal->sdest;\n+\n+\tret = process_portal_allocate(&input);\n+\tif (ret)\n+\t\treturn ret;\n+\tportal->index = input.index;\n+\tportal->cinh = input.cinh;\n+\tportal->cena = input.cena;\n+\treturn 0;\n+}\n+\n+int qman_free_raw_portal(struct dpaa_raw_portal *portal)\n+{\n+\tstruct dpaa_ioctl_raw_portal input;\n+\n+\tinput.type = dpaa_portal_qman;\n+\tinput.index = portal->index;\n+\tinput.cinh = portal->cinh;\n+\tinput.cena = portal->cena;\n+\n+\treturn process_portal_free(&input);\n+}\n+\n+int bman_allocate_raw_portal(struct dpaa_raw_portal *portal)\n+{\n+\tstruct dpaa_ioctl_raw_portal input;\n+\tint ret;\n+\n+\tinput.type = dpaa_portal_bman;\n+\tinput.index = portal->index;\n+\tinput.enable_stash = 0;\n+\n+\tret = process_portal_allocate(&input);\n+\tif (ret)\n+\t\treturn ret;\n+\tportal->index = input.index;\n+\tportal->cinh = input.cinh;\n+\tportal->cena = input.cena;\n+\treturn 0;\n+}\n+\n+int bman_free_raw_portal(struct dpaa_raw_portal *portal)\n+{\n+\tstruct dpaa_ioctl_raw_portal input;\n+\n+\tinput.type = dpaa_portal_bman;\n+\tinput.index = portal->index;\n+\tinput.cinh = portal->cinh;\n+\tinput.cena = portal->cena;\n+\n+\treturn process_portal_free(&input);\n+}\ndiff --git a/drivers/bus/dpaa/include/fsl_usd.h b/drivers/bus/dpaa/include/fsl_usd.h\nnew file mode 100644\nindex 0000000..4ff48c6\n--- /dev/null\n+++ b/drivers/bus/dpaa/include/fsl_usd.h\n@@ -0,0 +1,88 @@\n+/*-\n+ * This file is provided under a dual BSD/GPLv2 license. When using or\n+ * redistributing this file, you may do so under either license.\n+ *\n+ * BSD LICENSE\n+ *\n+ * Copyright 2010-2011 Freescale Semiconductor, Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ * GPL LICENSE SUMMARY\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __FSL_USD_H\n+#define __FSL_USD_H\n+\n+#include <compat.h>\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define QBMAN_ANY_PORTAL_IDX 0xffffffff\n+\n+/* Obtain and free raw (unitialized) portals */\n+\n+struct dpaa_raw_portal {\n+\t/* inputs */\n+\n+\t/* set to non zero to turn on stashing */\n+\tuint8_t enable_stash;\n+\t/* Stashing attributes for the portal */\n+\tuint32_t cpu;\n+\tuint32_t cache;\n+\tuint32_t window;\n+\n+\t/* Specifies the stash request queue this portal should use */\n+\tuint8_t sdest;\n+\n+\t/* Specifes a specific portal index to map or QBMAN_ANY_PORTAL_IDX\n+\t * for don't care. The portal index will be populated by the\n+\t * driver when the ioctl() successfully completes.\n+\t */\n+\tuint32_t index;\n+\n+\t/* outputs */\n+\tuint64_t cinh;\n+\tuint64_t cena;\n+};\n+\n+int qman_allocate_raw_portal(struct dpaa_raw_portal *portal);\n+int qman_free_raw_portal(struct dpaa_raw_portal *portal);\n+\n+int bman_allocate_raw_portal(struct dpaa_raw_portal *portal);\n+int bman_free_raw_portal(struct dpaa_raw_portal *portal);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* __FSL_USD_H */\ndiff --git a/drivers/bus/dpaa/include/process.h b/drivers/bus/dpaa/include/process.h\nnew file mode 100644\nindex 0000000..989ddcd\n--- /dev/null\n+++ b/drivers/bus/dpaa/include/process.h\n@@ -0,0 +1,107 @@\n+/*-\n+ * This file is provided under a dual BSD/GPLv2 license. When using or\n+ * redistributing this file, you may do so under either license.\n+ *\n+ * BSD LICENSE\n+ *\n+ * Copyright 2010-2011 Freescale Semiconductor, Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in the\n+ * documentation and/or other materials provided with the distribution.\n+ * * Neither the name of the above-listed copyright holders nor the\n+ * names of any contributors may be used to endorse or promote products\n+ * derived from this software without specific prior written permission.\n+ *\n+ * GPL LICENSE SUMMARY\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef __PROCESS_H\n+#define\t__PROCESS_H\n+\n+#include <compat.h>\n+\n+/* The process device underlies process-wide user/kernel interactions, such as\n+ * mapping dma_mem memory and providing accompanying ioctl()s. (This isn't used\n+ * for portals, which use one UIO device each.).\n+ */\n+#define PROCESS_PATH\t\t\"/dev/fsl-usdpaa\"\n+\n+/* Allocation of resource IDs uses a generic interface. This enum is used to\n+ * distinguish between the type of underlying object being manipulated.\n+ */\n+enum dpaa_id_type {\n+\tdpaa_id_fqid,\n+\tdpaa_id_bpid,\n+\tdpaa_id_qpool,\n+\tdpaa_id_cgrid,\n+\tdpaa_id_max /* <-- not a valid type, represents the number of types */\n+};\n+\n+int process_alloc(enum dpaa_id_type id_type, uint32_t *base, uint32_t num,\n+\t\t uint32_t align, int partial);\n+void process_release(enum dpaa_id_type id_type, uint32_t base, uint32_t num);\n+\n+int process_reserve(enum dpaa_id_type id_type, uint32_t base, uint32_t num);\n+\n+/* Mapping and using QMan/BMan portals */\n+enum dpaa_portal_type {\n+\tdpaa_portal_qman,\n+\tdpaa_portal_bman,\n+};\n+\n+struct dpaa_ioctl_portal_map {\n+\t/* Input parameter, is a qman or bman portal required. */\n+\tenum dpaa_portal_type type;\n+\t/* Specifes a specific portal index to map or 0xffffffff\n+\t * for don't care.\n+\t */\n+\tuint32_t index;\n+\n+\t/* Return value if the map succeeds, this gives the mapped\n+\t * cache-inhibited (cinh) and cache-enabled (cena) addresses.\n+\t */\n+\tstruct dpaa_portal_map {\n+\t\tvoid *cinh;\n+\t\tvoid *cena;\n+\t} addr;\n+\t/* Qman-specific return values */\n+\tu16 channel;\n+\tuint32_t pools;\n+};\n+\n+int process_portal_map(struct dpaa_ioctl_portal_map *params);\n+int process_portal_unmap(struct dpaa_portal_map *map);\n+\n+struct dpaa_ioctl_irq_map {\n+\tenum dpaa_portal_type type; /* Type of portal to map */\n+\tint fd; /* File descriptor that contains the portal */\n+\tvoid *portal_cinh; /* Cache inhibited area to identify the portal */\n+};\n+\n+int process_portal_irq_map(int fd, struct dpaa_ioctl_irq_map *irq);\n+int process_portal_irq_unmap(int fd);\n+\n+#endif\t/* __PROCESS_H */\n", "prefixes": [ "dpdk-dev", "v5", "07/40" ] }