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GET /api/patches/27919/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 27919,
    "url": "http://patches.dpdk.org/api/patches/27919/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1503647430-93905-6-git-send-email-beilei.xing@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1503647430-93905-6-git-send-email-beilei.xing@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1503647430-93905-6-git-send-email-beilei.xing@intel.com",
    "date": "2017-08-25T07:50:28",
    "name": "[dpdk-dev,5/7] net/i40e: add FDIR support for GTP-C and GTP-U",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "32fa2f2bcfefabbbd3d18a3bd4c7333903ced549",
    "submitter": {
        "id": 410,
        "url": "http://patches.dpdk.org/api/people/410/?format=api",
        "name": "Xing, Beilei",
        "email": "beilei.xing@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1503647430-93905-6-git-send-email-beilei.xing@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/27919/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/27919/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id D42D07D8B;\n\tFri, 25 Aug 2017 09:51:27 +0200 (CEST)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 64B477D56\n\tfor <dev@dpdk.org>; Fri, 25 Aug 2017 09:51:20 +0200 (CEST)",
            "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Aug 2017 00:51:19 -0700",
            "from unknown (HELO dpdk9.sh.intel.com) ([10.67.119.137])\n\tby fmsmga006.fm.intel.com with ESMTP; 25 Aug 2017 00:51:18 -0700"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.41,424,1498546800\"; d=\"scan'208\";a=\"144422398\"",
        "From": "Beilei Xing <beilei.xing@intel.com>",
        "To": "jingjing.wu@intel.com",
        "Cc": "dev@dpdk.org",
        "Date": "Fri, 25 Aug 2017 15:50:28 +0800",
        "Message-Id": "<1503647430-93905-6-git-send-email-beilei.xing@intel.com>",
        "X-Mailer": "git-send-email 2.5.5",
        "In-Reply-To": "<1503647430-93905-1-git-send-email-beilei.xing@intel.com>",
        "References": "<1503647430-93905-1-git-send-email-beilei.xing@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 5/7] net/i40e: add FDIR support for GTP-C and\n\tGTP-U",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch adds FDIR support for GTP-C and GTP-U.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c |  2 ++\n drivers/net/i40e/i40e_ethdev.h |  9 ++++++++\n drivers/net/i40e/i40e_fdir.c   | 42 ++++++++++++++++++++++++++++++++++--\n drivers/net/i40e/i40e_flow.c   | 48 +++++++++++++++++++++++++++++++++++++++++-\n 4 files changed, 98 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 7c9e5af..d7ef782 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -8228,6 +8228,8 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype,\n \t\t[I40E_FILTER_PCTYPE_L2_PAYLOAD] =\n \t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n \t\tI40E_INSET_LAST_ETHER_TYPE,\n+\t\t[I40E_FILTER_PCTYPE_GTPC] = I40E_INSET_GTP_TEID,\n+\t\t[I40E_FILTER_PCTYPE_GTPU] = I40E_INSET_GTP_TEID,\n \t};\n \n \tif (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 6d871e4..1681bad 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -467,6 +467,14 @@ struct i40e_vmdq_info {\n #define I40E_FDIR_IPv6_TC_OFFSET\t20\n \n /**\n+ * A structure used to define the input for IPV4 GTP flow\n+ */\n+struct i40e_gtpv4_flow {\n+\tstruct rte_eth_udpv4_flow udp; /**< IPv4 UDP fields to match. */\n+\tuint32_t teid;                 /**< TEID in big endian. */\n+};\n+\n+/**\n  * A union contains the inputs for all types of flow\n  * Items in flows need to be in big endian\n  */\n@@ -480,6 +488,7 @@ union i40e_fdir_flow {\n \tstruct rte_eth_tcpv6_flow  tcp6_flow;\n \tstruct rte_eth_sctpv6_flow sctp6_flow;\n \tstruct rte_eth_ipv6_flow   ipv6_flow;\n+\tstruct i40e_gtpv4_flow     gtpv4_flow;\n };\n \n /**\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex b0ba819..707ab4d 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -71,6 +71,7 @@\n #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF\n #define I40E_FDIR_IPv6_PAYLOAD_LEN          380\n #define I40E_FDIR_UDP_DEFAULT_LEN           400\n+#define I40E_FDIR_GTP_DEFAULT_LEN           384\n \n /* Wait time for fdir filter programming */\n #define I40E_FDIR_MAX_WAIT_US 10000\n@@ -949,6 +950,7 @@ i40e_flow_fdir_fill_eth_ip_head(const struct i40e_fdir_input *fdir_input,\n \tuint8_t len = 2 * sizeof(struct ether_addr);\n \tstruct ipv4_hdr *ip;\n \tstruct ipv6_hdr *ip6;\n+\tuint8_t pctype = fdir_input->pctype;\n \tstatic const uint8_t next_proto[] = {\n \t\t[I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,\n \t\t[I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,\n@@ -960,6 +962,8 @@ i40e_flow_fdir_fill_eth_ip_head(const struct i40e_fdir_input *fdir_input,\n \t\t[I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,\n \t\t[I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,\n \t\t[I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,\n+\t\t[I40E_FILTER_PCTYPE_GTPC] = IPPROTO_UDP,\n+\t\t[I40E_FILTER_PCTYPE_GTPU] = IPPROTO_UDP,\n \t};\n \n \traw_pkt += 2 * sizeof(struct ether_addr);\n@@ -975,7 +979,7 @@ i40e_flow_fdir_fill_eth_ip_head(const struct i40e_fdir_input *fdir_input,\n \traw_pkt += sizeof(uint16_t);\n \tlen += sizeof(uint16_t);\n \n-\tswitch (fdir_input->pctype) {\n+\tswitch (pctype) {\n \tcase I40E_FILTER_PCTYPE_L2_PAYLOAD:\n \t\t*ether_type = fdir_input->flow.l2_flow.ether_type;\n \t\tbreak;\n@@ -984,6 +988,8 @@ i40e_flow_fdir_fill_eth_ip_head(const struct i40e_fdir_input *fdir_input,\n \tcase I40E_FILTER_PCTYPE_NONF_IPV4_SCTP:\n \tcase I40E_FILTER_PCTYPE_NONF_IPV4_OTHER:\n \tcase I40E_FILTER_PCTYPE_FRAG_IPV4:\n+\tcase I40E_FILTER_PCTYPE_GTPC:\n+\tcase I40E_FILTER_PCTYPE_GTPU:\n \t\tip = (struct ipv4_hdr *)raw_pkt;\n \n \t\t*ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n@@ -1062,9 +1068,11 @@ i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,\n \tstruct udp_hdr *udp;\n \tstruct tcp_hdr *tcp;\n \tstruct sctp_hdr *sctp;\n+\tstruct rte_flow_item_gtp *gtp;\n \tuint8_t size, dst = 0;\n \tuint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/\n \tint len;\n+\tuint8_t pctype = fdir_input->pctype;\n \n \t/* fill the ethernet and IP head */\n \tlen = i40e_flow_fdir_fill_eth_ip_head(fdir_input, raw_pkt,\n@@ -1073,7 +1081,7 @@ i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,\n \t\treturn -EINVAL;\n \n \t/* fill the L4 head */\n-\tswitch (fdir_input->pctype) {\n+\tswitch (pctype) {\n \tcase I40E_FILTER_PCTYPE_NONF_IPV4_UDP:\n \t\tudp = (struct udp_hdr *)(raw_pkt + len);\n \t\tpayload = (unsigned char *)udp + sizeof(struct udp_hdr);\n@@ -1174,6 +1182,36 @@ i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,\n \t\t\tpayload += sizeof(struct arp_hdr);\n \t\tset_idx = I40E_FLXPLD_L2_IDX;\n \t\tbreak;\n+\tcase I40E_FILTER_PCTYPE_GTPC:\n+\t\tudp = (struct udp_hdr *)(raw_pkt + len);\n+\t\tudp->dst_port = rte_cpu_to_be_16(2123);\n+\t\tudp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);\n+\n+\t\tgtp = (struct rte_flow_item_gtp *)\n+\t\t\t((unsigned char *)udp + sizeof(struct udp_hdr));\n+\t\tgtp->v_pt_rsv_flags = 0x30;\n+\t\tgtp->msg_len = rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);\n+\t\tgtp->teid = fdir_input->flow.gtpv4_flow.teid;\n+\t\tgtp->msg_type = 0xff;\n+\n+\t\tpayload = (unsigned char *)gtp +\n+\t\t\t   sizeof(struct rte_flow_item_gtp);\n+\t\tbreak;\n+\tcase I40E_FILTER_PCTYPE_GTPU:\n+\t\tudp = (struct udp_hdr *)(raw_pkt + len);\n+\t\tudp->dst_port = rte_cpu_to_be_16(2152);\n+\t\tudp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);\n+\n+\t\tgtp = (struct rte_flow_item_gtp *)\n+\t\t\t((unsigned char *)udp + sizeof(struct udp_hdr));\n+\t\tgtp->v_pt_rsv_flags = 0x30;\n+\t\tgtp->msg_len = rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);\n+\t\tgtp->teid = fdir_input->flow.gtpv4_flow.teid;\n+\t\tgtp->msg_type = 0xff;\n+\n+\t\tpayload = (unsigned char *)gtp +\n+\t\t\t   sizeof(struct rte_flow_item_gtp);\n+\t\tbreak;\n \tdefault:\n \t\tPMD_DRV_LOG(ERR, \"unknown pctype %u.\", fdir_input->pctype);\n \t\treturn -EINVAL;\ndiff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c\nindex 73af7fd..698368e 100644\n--- a/drivers/net/i40e/i40e_flow.c\n+++ b/drivers/net/i40e/i40e_flow.c\n@@ -189,6 +189,14 @@ static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {\n \tRTE_FLOW_ITEM_TYPE_END,\n };\n \n+static enum rte_flow_item_type pattern_fdir_ipv4_gtp[] = {\n+\tRTE_FLOW_ITEM_TYPE_ETH,\n+\tRTE_FLOW_ITEM_TYPE_IPV4,\n+\tRTE_FLOW_ITEM_TYPE_UDP,\n+\tRTE_FLOW_ITEM_TYPE_GTP,\n+\tRTE_FLOW_ITEM_TYPE_END,\n+};\n+\n static enum rte_flow_item_type pattern_fdir_ipv6[] = {\n \tRTE_FLOW_ITEM_TYPE_ETH,\n \tRTE_FLOW_ITEM_TYPE_IPV6,\n@@ -1576,6 +1584,7 @@ static struct i40e_valid_pattern i40e_supported_patterns[] = {\n \t{ pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },\n \t{ pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },\n \t{ pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },\n+\t{ pattern_fdir_ipv4_gtp, i40e_flow_parse_fdir_filter },\n \t{ pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },\n \t{ pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },\n \t{ pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },\n@@ -2326,10 +2335,11 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \tconst struct rte_flow_item_tcp *tcp_spec, *tcp_mask;\n \tconst struct rte_flow_item_udp *udp_spec, *udp_mask;\n \tconst struct rte_flow_item_sctp *sctp_spec, *sctp_mask;\n+\tconst struct rte_flow_item_gtp *gtp_spec, *gtp_mask;\n \tconst struct rte_flow_item_raw *raw_spec, *raw_mask;\n \tconst struct rte_flow_item_vf *vf_spec;\n \n-\tenum i40e_filter_pctype pctype = 0;\n+\tuint8_t pctype = 0;\n \tuint64_t input_set = I40E_INSET_NONE;\n \tuint16_t frag_off;\n \tenum rte_flow_item_type item_type;\n@@ -2351,6 +2361,7 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \tuint16_t outer_tpid;\n \tuint16_t ether_type;\n \tuint32_t vtc_flow_cpu;\n+\tuint16_t udp_dst_port = 0;\n \tint ret;\n \n \tmemset(off_arr, 0, sizeof(off_arr));\n@@ -2631,11 +2642,46 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,\n \t\t\t\t\tfilter->input.flow.udp6_flow.dst_port =\n \t\t\t\t\t\tudp_spec->hdr.dst_port;\n \t\t\t\t}\n+\n+\t\t\t\tudp_dst_port = udp_spec->hdr.dst_port;\n \t\t\t}\n \n \t\t\tlayer_idx = I40E_FLXPLD_L4_IDX;\n \n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n+\t\t\tgtp_spec = (const struct rte_flow_item_gtp *)item->spec;\n+\t\t\tgtp_mask = (const struct rte_flow_item_gtp *)item->mask;\n+\n+\t\t\tif (gtp_spec && gtp_mask) {\n+\t\t\t\tif (gtp_mask->v_pt_rsv_flags ||\n+\t\t\t\t    gtp_mask->msg_type ||\n+\t\t\t\t    gtp_mask->msg_len ||\n+\t\t\t\t    gtp_mask->teid != UINT32_MAX) {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\t   item,\n+\t\t\t\t\t\t   \"Invalid GTP mask\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\n+\t\t\t\tinput_set |= I40E_INSET_GTP_TEID;\n+\t\t\t\tfilter->input.flow.gtpv4_flow.teid =\n+\t\t\t\t\tgtp_spec->teid;\n+\n+\t\t\t\tif (udp_dst_port == rte_cpu_to_be_16(2123))\n+\t\t\t\t\tpctype = I40E_FILTER_PCTYPE_GTPC;\n+\t\t\t\telse if (udp_dst_port == rte_cpu_to_be_16(2152))\n+\t\t\t\t\tpctype = I40E_FILTER_PCTYPE_GTPU;\n+\t\t\t\telse {\n+\t\t\t\t\trte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\t   item,\n+\t\t\t\t\t\t   \"Invalid GTP flow\");\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_SCTP:\n \t\t\tsctp_spec =\n \t\t\t\t(const struct rte_flow_item_sctp *)item->spec;\n",
    "prefixes": [
        "dpdk-dev",
        "5/7"
    ]
}