Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/18184/?format=api
{ "id": 18184, "url": "http://patches.dpdk.org/api/patches/18184/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-28-git-send-email-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1482180853-18823-28-git-send-email-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1482180853-18823-28-git-send-email-hemant.agrawal@nxp.com", "date": "2016-12-19T20:54:06", "name": "[dpdk-dev,PATCHv2,27/34] net/dpaa2: rx packet parsing and packet type support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2b3127d874fd700bac026ef9e25642049f13bee7", "submitter": { "id": 477, "url": "http://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1482180853-18823-28-git-send-email-hemant.agrawal@nxp.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/18184/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/18184/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 96532FB16;\n\tMon, 19 Dec 2016 16:22:35 +0100 (CET)", "from NAM02-BL2-obe.outbound.protection.outlook.com\n\t(mail-bl2nam02on0040.outbound.protection.outlook.com [104.47.38.40])\n\tby dpdk.org (Postfix) with ESMTP id A5AEAFAF3\n\tfor <dev@dpdk.org>; Mon, 19 Dec 2016 16:22:07 +0100 (CET)", "from DM5PR03CA0018.namprd03.prod.outlook.com (10.175.104.28) by\n\tBN1PR0301MB0737.namprd03.prod.outlook.com (10.160.78.144) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.789.14; Mon, 19 Dec 2016 15:22:06 +0000", "from BN1BFFO11FD032.protection.gbl (2a01:111:f400:7c10::1:178) by\n\tDM5PR03CA0018.outlook.office365.com (2603:10b6:3:118::28) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id\n\t15.1.789.14 via Frontend Transport; Mon, 19 Dec 2016 15:22:06 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBN1BFFO11FD032.mail.protection.outlook.com (10.58.144.95) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.789.10\n\tvia Frontend Transport; Mon, 19 Dec 2016 15:22:05 +0000", "from bf-netperf1.idc ([10.232.134.28])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tuBJFKMhq029110; Mon, 19 Dec 2016 08:22:02 -0700" ], "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com;\n\tnxp.com; \n\tdkim=none (message not signed) header.d=none;", "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "<dev@dpdk.org>", "CC": "<thomas.monjalon@6wind.com>, <bruce.richardson@intel.com>,\n\t<shreyansh.jain@nxp.com>, <john.mcnamara@intel.com>,\n\t<ferruh.yigit@intel.com>, <jerin.jacob@caviumnetworks.com>,\n\tHemant Agrawal <hemant.agrawal@nxp.com>", "Date": "Tue, 20 Dec 2016 02:24:06 +0530", "Message-ID": "<1482180853-18823-28-git-send-email-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "References": "<1480875447-23680-1-git-send-email-hemant.agrawal@nxp.com>\n\t<1482180853-18823-1-git-send-email-hemant.agrawal@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131266345259336788;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0; RULEID:(22001);\n\tSRVR:BN1PR0301MB0737; ", "X-Microsoft-Antispam-PRVS": "<BN1PR0301MB0737F714390677BF6D041FE789910@BN1PR0301MB0737.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:(185117386973197);", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(6095060)(601004)(2401047)(8121501046)(13018025)(13015025)(5005006)(13024025)(13023025)(13017025)(3002001)(10201501046)(6055026)(6096035)(20161123561025)(20161123559025)(20161123565025)(20161123556025)(20161123563025);\n\tSRVR:BN1PR0301MB0737; BCL:0; PCL:0; RULEID:(400006);\n\tSRVR:BN1PR0301MB0737; ", "X-Forefront-PRVS": "01613DFDC8", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Dec 2016 15:22:05.6840\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN1PR0301MB0737", "Subject": "[dpdk-dev] [PATCHv2 27/34] net/dpaa2: rx packet parsing and packet\n\ttype support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n doc/guides/nics/features/dpaa2.ini | 1 +\n drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h | 257 +++++++++++++++++++++++++++\n drivers/net/dpaa2/dpaa2_ethdev.c | 23 +++\n drivers/net/dpaa2/dpaa2_rxtx.c | 91 +++++++++-\n 4 files changed, 371 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h", "diff": "diff --git a/doc/guides/nics/features/dpaa2.ini b/doc/guides/nics/features/dpaa2.ini\nindex a6b7964..0746d4b 100644\n--- a/doc/guides/nics/features/dpaa2.ini\n+++ b/doc/guides/nics/features/dpaa2.ini\n@@ -10,6 +10,7 @@ Promiscuous mode = Y\n RSS hash = Y\n L3 checksum offload = Y\n L4 checksum offload = Y\n+Packet type parsing = Y\n Linux VFIO = Y\n ARMv8 = Y\n Usage doc = Y\ndiff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h\nnew file mode 100644\nindex 0000000..9324c6a\n--- /dev/null\n+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h\n@@ -0,0 +1,257 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (c) 2016 NXP. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Freescale Semiconductor, Inc nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/**\n+ * @file\n+ *\n+ * DPNI packet parse results - implementation internal\n+ */\n+\n+#ifndef _DPAA2_HW_DPNI_ANNOT_H_\n+#define _DPAA2_HW_DPNI_ANNOT_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/* Annotation valid bits in FD FRC */\n+#define DPAA2_FD_FRC_FASV\t0x8000\n+#define DPAA2_FD_FRC_FAEADV\t0x4000\n+#define DPAA2_FD_FRC_FAPRV\t0x2000\n+#define DPAA2_FD_FRC_FAIADV\t0x1000\n+#define DPAA2_FD_FRC_FASWOV\t0x0800\n+#define DPAA2_FD_FRC_FAICFDV\t0x0400\n+\n+/* Annotation bits in FD CTRL */\n+#define DPAA2_FD_CTRL_ASAL\t0x00020000 /* ASAL = 128 */\n+#define DPAA2_FD_CTRL_PTA\t0x00800000\n+#define DPAA2_FD_CTRL_PTV1\t0x00400000\n+\n+/* Frame annotation status */\n+struct dpaa2_fas {\n+\tuint8_t reserved;\n+\tuint8_t ppid;\n+\t__le16 ifpid;\n+\t__le32 status;\n+} __packed;\n+\n+/**\n+ * HW Packet Annotation Register structures\n+ */\n+struct dpaa2_annot_hdr {\n+\t/**<\tword1: Frame Annotation Status (8 bytes)*/\n+\tuint64_t word1;\n+\n+\t/**<\tword2: Time Stamp (8 bytes)*/\n+\tuint64_t word2;\n+\n+\t/**<\tword3: Next Hdr + FAF Extension + FAF (2 + 2 + 4 bytes)*/\n+\tuint64_t word3;\n+\n+\t/**<\tword4: Frame Annotation Flags-FAF (8 bytes) */\n+\tuint64_t word4;\n+\n+\t/**<\tword5:\n+\t *\tShimOffset_1 + ShimOffset_2 + IPPIDOffset + EthOffset +\n+\t *\tLLC+SNAPOffset + VLANTCIOffset_1 + VLANTCIOffset_n +\n+\t *\tLastETypeOffset (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 bytes)\n+\t */\n+\tuint64_t word5;\n+\n+\t/**<\tword6:\n+\t *\tPPPoEOffset + MPLSOffset_1 + MPLSOffset_n + ARPorIPOffset_1\n+\t *\t+ IPOffset_norMInEncapO + GREOffset + L4Offset +\n+\t *\tGTPorESPorIPSecOffset(1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 bytes)\n+\t */\n+\tuint64_t word6;\n+\n+\t/**<\tword7:\n+\t *\tRoutingHdrOfset1 + RoutingHdrOfset2 + NxtHdrOffset\n+\t *\t+ IPv6FragOffset + GrossRunningSum\n+\t *\t+ RunningSum(1 + 1 + 1 + 1 + 2 + 2 bytes)\n+\t */\n+\tuint64_t word7;\n+\n+\t/**<\tword8:\n+\t *\tParseErrorcode + Soft Parsing Context (1 + 7 bytes)\n+\t */\n+\tuint64_t word8;\n+};\n+\n+/**\n+ * Internal Macros to get/set Packet annotation header\n+ */\n+\n+/** General Macro to define a particular bit position*/\n+#define BIT_POS(x)\t\t\t((uint64_t)1 << ((x)))\n+/** Set a bit in the variable */\n+#define BIT_SET_AT_POS(var, pos)\t((var) |= (pos))\n+/** Reset the bit in the variable */\n+#define BIT_RESET_AT_POS(var, pos)\t((var) &= ~(pos))\n+/** Check the bit is set in the variable */\n+#define BIT_ISSET_AT_POS(var, pos)\t(((var) & (pos)) ? 1 : 0)\n+/**\n+ * Macrso to define bit position in word3\n+ */\n+#define NEXT_HDR(var)\t\t\t((uint64_t)(var) & 0xFFFF000000000000)\n+#define FAF_EXTN_IPV6_ROUTE_HDR_PRESENT(var)\tBIT_POS(16)\n+#define FAF_EXTN_RESERVED(var)\t\t((uint64_t)(var) & 0x00007FFF00000000)\n+#define FAF_USER_DEFINED_RESERVED(var)\t((uint64_t)(var) & 0x00000000FF000000)\n+#define SHIM_SHELL_SOFT_PARSING_ERRROR\t\tBIT_POS(23)\n+#define PARSING_ERROR\t\t\t\tBIT_POS(22)\n+#define L2_ETH_MAC_PRESENT\t\t\tBIT_POS(21)\n+#define L2_ETH_MAC_UNICAST\t\t\tBIT_POS(20)\n+#define L2_ETH_MAC_MULTICAST\t\t\tBIT_POS(19)\n+#define L2_ETH_MAC_BROADCAST\t\t\tBIT_POS(18)\n+#define L2_ETH_FRAME_IS_BPDU\t\t\tBIT_POS(17)\n+#define L2_ETH_FCOE_PRESENT\t\t\tBIT_POS(16)\n+#define L2_ETH_FIP_PRESENT\t\t\tBIT_POS(15)\n+#define L2_ETH_PARSING_ERROR\t\t\tBIT_POS(14)\n+#define L2_LLC_SNAP_PRESENT\t\t\tBIT_POS(13)\n+#define L2_UNKNOWN_LLC_OUI\t\t\tBIT_POS(12)\n+#define L2_LLC_SNAP_ERROR\t\t\tBIT_POS(11)\n+#define L2_VLAN_1_PRESENT\t\t\tBIT_POS(10)\n+#define L2_VLAN_N_PRESENT\t\t\tBIT_POS(9)\n+#define L2_VLAN_CFI_BIT_PRESENT\t\t\tBIT_POS(8)\n+#define L2_VLAN_PARSING_ERROR\t\t\tBIT_POS(7)\n+#define L2_PPPOE_PPP_PRESENT\t\t\tBIT_POS(6)\n+#define L2_PPPOE_PPP_PARSING_ERROR\t\tBIT_POS(5)\n+#define L2_MPLS_1_PRESENT\t\t\tBIT_POS(4)\n+#define L2_MPLS_N_PRESENT\t\t\tBIT_POS(3)\n+#define L2_MPLS_PARSING_ERROR\t\t\tBIT_POS(2)\n+#define L2_ARP_PRESENT\t\t\t\tBIT_POS(1)\n+#define L2_ARP_PARSING_ERROR\t\t\tBIT_POS(0)\n+/**\n+ * Macrso to define bit position in word4\n+ */\n+#define L2_UNKNOWN_PROTOCOL\t\t\tBIT_POS(63)\n+#define L2_SOFT_PARSING_ERROR\t\t\tBIT_POS(62)\n+#define L3_IPV4_1_PRESENT\t\t\tBIT_POS(61)\n+#define L3_IPV4_1_UNICAST\t\t\tBIT_POS(60)\n+#define L3_IPV4_1_MULTICAST\t\t\tBIT_POS(59)\n+#define L3_IPV4_1_BROADCAST\t\t\tBIT_POS(58)\n+#define L3_IPV4_N_PRESENT\t\t\tBIT_POS(57)\n+#define L3_IPV4_N_UNICAST\t\t\tBIT_POS(56)\n+#define L3_IPV4_N_MULTICAST\t\t\tBIT_POS(55)\n+#define L3_IPV4_N_BROADCAST\t\t\tBIT_POS(54)\n+#define L3_IPV6_1_PRESENT\t\t\tBIT_POS(53)\n+#define L3_IPV6_1_UNICAST\t\t\tBIT_POS(52)\n+#define L3_IPV6_1_MULTICAST\t\t\tBIT_POS(51)\n+#define L3_IPV6_N_PRESENT\t\t\tBIT_POS(50)\n+#define L3_IPV6_N_UNICAST\t\t\tBIT_POS(49)\n+#define L3_IPV6_N_MULTICAST\t\t\tBIT_POS(48)\n+#define L3_IP_1_OPT_PRESENT\t\t\tBIT_POS(47)\n+#define L3_IP_1_UNKNOWN_PROTOCOL\t\tBIT_POS(46)\n+#define L3_IP_1_MORE_FRAGMENT\t\t\tBIT_POS(45)\n+#define L3_IP_1_FIRST_FRAGMENT\t\t\tBIT_POS(44)\n+#define L3_IP_1_PARSING_ERROR\t\t\tBIT_POS(43)\n+#define L3_IP_N_OPT_PRESENT\t\t\tBIT_POS(42)\n+#define L3_IP_N_UNKNOWN_PROTOCOL\t\tBIT_POS(41)\n+#define L3_IP_N_MORE_FRAGMENT\t\t\tBIT_POS(40)\n+#define L3_IP_N_FIRST_FRAGMENT\t\t\tBIT_POS(39)\n+#define L3_PROTO_ICMP_PRESENT\t\t\tBIT_POS(38)\n+#define L3_PROTO_IGMP_PRESENT\t\t\tBIT_POS(37)\n+#define L3_PROTO_ICMPV6_PRESENT\t\t\tBIT_POS(36)\n+#define L3_PROTO_UDP_LIGHT_PRESENT\t\tBIT_POS(35)\n+#define L3_IP_N_PARSING_ERROR\t\t\tBIT_POS(34)\n+#define L3_MIN_ENCAP_PRESENT\t\t\tBIT_POS(33)\n+#define L3_MIN_ENCAP_SBIT_PRESENT\t\tBIT_POS(32)\n+#define L3_MIN_ENCAP_PARSING_ERROR\t\tBIT_POS(31)\n+#define L3_PROTO_GRE_PRESENT\t\t\tBIT_POS(30)\n+#define L3_PROTO_GRE_RBIT_PRESENT\t\tBIT_POS(29)\n+#define L3_PROTO_GRE_PARSING_ERROR\t\tBIT_POS(28)\n+#define L3_IP_UNKNOWN_PROTOCOL\t\t\tBIT_POS(27)\n+#define L3_SOFT_PARSING_ERROR\t\t\tBIT_POS(26)\n+#define L3_PROTO_UDP_PRESENT\t\t\tBIT_POS(25)\n+#define L3_PROTO_UDP_PARSING_ERROR\t\tBIT_POS(24)\n+#define L3_PROTO_TCP_PRESENT\t\t\tBIT_POS(23)\n+#define L3_PROTO_TCP_OPT_PRESENT\t\tBIT_POS(22)\n+#define L3_PROTO_TCP_CTRL_BIT_6_TO_11_PRESENT\tBIT_POS(21)\n+#define L3_PROTO_TCP_CTRL_BIT_3_TO_5_PRESENT\tBIT_POS(20)\n+#define L3_PROTO_TCP_PARSING_ERROR\t\tBIT_POS(19)\n+#define L3_PROTO_IPSEC_PRESENT\t\t\tBIT_POS(18)\n+#define L3_PROTO_IPSEC_ESP_PRESENT\t\tBIT_POS(17)\n+#define L3_PROTO_IPSEC_AH_PRESENT\t\tBIT_POS(16)\n+#define L3_PROTO_IPSEC_PARSING_ERROR\t\tBIT_POS(15)\n+#define L3_PROTO_SCTP_PRESENT\t\t\tBIT_POS(14)\n+#define L3_PROTO_SCTP_PARSING_ERROR\t\tBIT_POS(13)\n+#define L3_PROTO_DCCP_PRESENT\t\t\tBIT_POS(12)\n+#define L3_PROTO_DCCP_PARSING_ERROR\t\tBIT_POS(11)\n+#define L4_UNKNOWN_PROTOCOL\t\t\tBIT_POS(10)\n+#define L4_SOFT_PARSING_ERROR\t\t\tBIT_POS(9)\n+#define L3_PROTO_GTP_PRESENT\t\t\tBIT_POS(8)\n+#define L3_PROTO_GTP_PARSING_ERROR\t\tBIT_POS(7)\n+#define L3_PROTO_ESP_PRESENT\t\t\tBIT_POS(6)\n+#define L3_PROTO_ESP_PARSING_ERROR\t\tBIT_POS(5)\n+#define L3_PROTO_ISCSI_PRESENT\t\t\tBIT_POS(4)\n+#define L3_PROTO_CAPWAN__CTRL_PRESENT\t\tBIT_POS(3)\n+#define L3_PROTO_CAPWAN__DATA_PRESENT\t\tBIT_POS(2)\n+#define L5_SOFT_PARSING_ERROR\t\t\tBIT_POS(1)\n+#define L3_IPV6_ROUTE_HDR_PRESENT\t\tBIT_POS(0)\n+\n+/* Debug frame, otherwise supposed to be discarded */\n+#define DPAA2_ETH_FAS_DISC\t 0x80000000\n+/* MACSEC frame */\n+#define DPAA2_ETH_FAS_MS\t\t0x40000000\n+#define DPAA2_ETH_FAS_PTP\t 0x08000000\n+/* Ethernet multicast frame */\n+#define DPAA2_ETH_FAS_MC\t\t0x04000000\n+/* Ethernet broadcast frame */\n+#define DPAA2_ETH_FAS_BC\t\t0x02000000\n+#define DPAA2_ETH_FAS_KSE\t 0x00040000\n+#define DPAA2_ETH_FAS_EOFHE\t 0x00020000\n+#define DPAA2_ETH_FAS_MNLE\t 0x00010000\n+#define DPAA2_ETH_FAS_TIDE\t 0x00008000\n+#define DPAA2_ETH_FAS_PIEE\t 0x00004000\n+/* Frame length error */\n+#define DPAA2_ETH_FAS_FLE\t 0x00002000\n+/* Frame physical error; our favourite pastime */\n+#define DPAA2_ETH_FAS_FPE\t 0x00001000\n+#define DPAA2_ETH_FAS_PTE\t 0x00000080\n+#define DPAA2_ETH_FAS_ISP\t 0x00000040\n+#define DPAA2_ETH_FAS_PHE\t 0x00000020\n+#define DPAA2_ETH_FAS_BLE\t 0x00000010\n+/* L3 csum validation performed */\n+#define DPAA2_ETH_FAS_L3CV\t 0x00000008\n+/* L3 csum error */\n+#define DPAA2_ETH_FAS_L3CE\t 0x00000004\n+/* L4 csum validation performed */\n+#define DPAA2_ETH_FAS_L4CV\t 0x00000002\n+/* L4 csum error */\n+#define DPAA2_ETH_FAS_L4CE\t 0x00000001\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c\nindex 3c4ca28..c705014 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.c\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.c\n@@ -311,6 +311,28 @@\n \tPMD_INIT_FUNC_TRACE();\n }\n \n+static const uint32_t *\n+dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)\n+{\n+\tstatic const uint32_t ptypes[] = {\n+\t\t/*todo -= add more types */\n+\t\tRTE_PTYPE_L2_ETHER,\n+\t\tRTE_PTYPE_L3_IPV4,\n+\t\tRTE_PTYPE_L3_IPV4_EXT,\n+\t\tRTE_PTYPE_L3_IPV6,\n+\t\tRTE_PTYPE_L3_IPV6_EXT,\n+\t\tRTE_PTYPE_L4_TCP,\n+\t\tRTE_PTYPE_L4_UDP,\n+\t\tRTE_PTYPE_L4_SCTP,\n+\t\tRTE_PTYPE_L4_ICMP,\n+\t\tRTE_PTYPE_UNKNOWN\n+\t};\n+\n+\tif (dev->rx_pkt_burst == dpaa2_dev_rx)\n+\t\treturn ptypes;\n+\treturn NULL;\n+}\n+\n static int\n dpaa2_dev_start(struct rte_eth_dev *dev)\n {\n@@ -518,6 +540,7 @@\n \t.promiscuous_enable = dpaa2_dev_promiscuous_enable,\n \t.promiscuous_disable = dpaa2_dev_promiscuous_disable,\n \t.dev_infos_get\t = dpaa2_dev_info_get,\n+\t.dev_supported_ptypes_get = dpaa2_supported_ptypes_get,\n \t.mtu_set = dpaa2_dev_mtu_set,\n \t.rx_queue_setup = dpaa2_dev_rx_queue_setup,\n \t.rx_queue_release = dpaa2_dev_rx_queue_release,\ndiff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c\nindex 4b76be5..7d73bde 100644\n--- a/drivers/net/dpaa2/dpaa2_rxtx.c\n+++ b/drivers/net/dpaa2/dpaa2_rxtx.c\n@@ -49,6 +49,88 @@\n #include <dpaa2_hw_mempool.h>\n \n #include \"dpaa2_ethdev.h\"\n+#include \"base/dpaa2_hw_dpni_annot.h\"\n+\n+static inline uint32_t __attribute__((hot))\n+dpaa2_dev_rx_parse(uint64_t hw_annot_addr)\n+{\n+\tuint32_t pkt_type = RTE_PTYPE_UNKNOWN;\n+\tstruct dpaa2_annot_hdr *annotation =\n+\t\t\t(struct dpaa2_annot_hdr *)hw_annot_addr;\n+\n+\tPMD_RX_LOG(DEBUG, \"annotation = 0x%lx \", annotation->word4);\n+\n+\tif (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {\n+\t\tpkt_type = RTE_PTYPE_L2_ETHER_ARP;\n+\t\tgoto parse_done;\n+\t} else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {\n+\t\tpkt_type = RTE_PTYPE_L2_ETHER;\n+\t} else {\n+\t\tgoto parse_done;\n+\t}\n+\n+\tif (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |\n+\t\t\t L3_IPV4_N_PRESENT)) {\n+\t\tpkt_type |= RTE_PTYPE_L3_IPV4;\n+\t\tif (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |\n+\t\t\tL3_IP_N_OPT_PRESENT))\n+\t\t\tpkt_type |= RTE_PTYPE_L3_IPV4_EXT;\n+\n+\t} else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |\n+\t\t L3_IPV6_N_PRESENT)) {\n+\t\tpkt_type |= RTE_PTYPE_L3_IPV6;\n+\t\tif (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |\n+\t\t L3_IP_N_OPT_PRESENT))\n+\t\t\tpkt_type |= RTE_PTYPE_L3_IPV6_EXT;\n+\t} else {\n+\t\tgoto parse_done;\n+\t}\n+\n+\tif (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |\n+\t L3_IP_1_MORE_FRAGMENT |\n+\t L3_IP_N_FIRST_FRAGMENT |\n+\t L3_IP_N_MORE_FRAGMENT)) {\n+\t\tpkt_type |= RTE_PTYPE_L4_FRAG;\n+\t\tgoto parse_done;\n+\t} else {\n+\t\tpkt_type |= RTE_PTYPE_L4_NONFRAG;\n+\t}\n+\n+\tif (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))\n+\t\tpkt_type |= RTE_PTYPE_L4_UDP;\n+\n+\telse if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))\n+\t\tpkt_type |= RTE_PTYPE_L4_TCP;\n+\n+\telse if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))\n+\t\tpkt_type |= RTE_PTYPE_L4_SCTP;\n+\n+\telse if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))\n+\t\tpkt_type |= RTE_PTYPE_L4_ICMP;\n+\n+\telse if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))\n+\t\tpkt_type |= RTE_PTYPE_UNKNOWN;\n+\n+parse_done:\n+\treturn pkt_type;\n+}\n+\n+static inline void __attribute__((hot))\n+dpaa2_dev_rx_offload(uint64_t hw_annot_addr, struct rte_mbuf *mbuf)\n+{\n+\tstruct dpaa2_annot_hdr *annotation =\n+\t\t(struct dpaa2_annot_hdr *)hw_annot_addr;\n+\n+\tif (BIT_ISSET_AT_POS(annotation->word3,\n+\t\t\t L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))\n+\t\tmbuf->ol_flags |= PKT_RX_VLAN_PKT;\n+\n+\tif (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))\n+\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n+\n+\tif (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))\n+\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n+}\n \n static inline struct rte_mbuf *__attribute__((hot))\n eth_fd_to_mbuf(const struct qbman_fd *fd)\n@@ -66,7 +148,14 @@ static inline struct rte_mbuf *__attribute__((hot))\n \tmbuf->data_len = DPAA2_GET_FD_LEN(fd);\n \tmbuf->pkt_len = mbuf->data_len;\n \n-\tmbuf->packet_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;\n+\t/* Parse the packet */\n+\t/* parse results are after the private - sw annotation area */\n+\tmbuf->packet_type = dpaa2_dev_rx_parse(\n+\t\t\t(uint64_t)(DPAA2_GET_FD_ADDR(fd))\n+\t\t\t + DPAA2_FD_PTA_SIZE);\n+\n+\tdpaa2_dev_rx_offload((uint64_t)(DPAA2_GET_FD_ADDR(fd)) +\n+\t\t\t DPAA2_FD_PTA_SIZE, mbuf);\n \n \tmbuf->next = NULL;\n \trte_mbuf_refcnt_set(mbuf, 1);\n", "prefixes": [ "dpdk-dev", "PATCHv2", "27/34" ] }