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{
    "id": 17128,
    "url": "http://patches.dpdk.org/api/patches/17128/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1479740470-6723-4-git-send-email-arybchenko@solarflare.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1479740470-6723-4-git-send-email-arybchenko@solarflare.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1479740470-6723-4-git-send-email-arybchenko@solarflare.com",
    "date": "2016-11-21T15:00:17",
    "name": "[dpdk-dev,03/56] net/sfc: import libefx register definitions",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "1009ba38f212a4eccdd5fe34b179d973047447c4",
    "submitter": {
        "id": 607,
        "url": "http://patches.dpdk.org/api/people/607/?format=api",
        "name": "Andrew Rybchenko",
        "email": "arybchenko@solarflare.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1479740470-6723-4-git-send-email-arybchenko@solarflare.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/17128/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/17128/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 4AB88D53C;\n\tMon, 21 Nov 2016 16:03:15 +0100 (CET)",
            "from nbfkord-smmo02.seg.att.com (nbfkord-smmo02.seg.att.com\n\t[209.65.160.78]) by dpdk.org (Postfix) with ESMTP id 5721E3977\n\tfor <dev@dpdk.org>; Mon, 21 Nov 2016 16:01:35 +0100 (CET)",
            "from unknown [12.187.104.26]\n\tby nbfkord-smmo02.seg.att.com(mxl_mta-7.2.4-7) with SMTP id\n\te4c03385.0.1541296.00-2307.3424216.nbfkord-smmo02.seg.att.com\n\t(envelope-from <arybchenko@solarflare.com>); \n\tMon, 21 Nov 2016 15:01:35 +0000 (UTC)",
            "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1044.25; Mon, 21 Nov 2016 07:01:21 -0800",
            "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1044.25 via Frontend Transport; Mon, 21 Nov 2016 07:01:20 -0800",
            "from uklogin.uk.solarflarecom.com (uklogin.uk.solarflarecom.com\n\t[10.17.10.10])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1JrJ007101 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:19 GMT",
            "from uklogin.uk.solarflarecom.com (localhost.localdomain\n\t[127.0.0.1])\n\tby uklogin.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tuALF1J2s006765 for <dev@dpdk.org>; Mon, 21 Nov 2016 15:01:19 GMT"
        ],
        "X-MXL-Hash": "58330c4f20560cac-b466af58fd0da0f8cc95131bec1a1f62167f8ec1",
        "From": "Andrew Rybchenko <arybchenko@solarflare.com>",
        "To": "<dev@dpdk.org>",
        "Date": "Mon, 21 Nov 2016 15:00:17 +0000",
        "Message-ID": "<1479740470-6723-4-git-send-email-arybchenko@solarflare.com>",
        "X-Mailer": "git-send-email 1.8.2.3",
        "In-Reply-To": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "References": "<1479740470-6723-1-git-send-email-arybchenko@solarflare.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-AnalysisOut": [
            "[v=2.1 cv=UI/baXry c=1 sm=1 tr=0 a=8BlWFWvVlq5taO8ncb8nKg==]",
            "[:17 a=L24OOQBejmoA:10 a=zRKbQ67AAAAA:8 a=e5HW62NM1AnPEwMv-]",
            "[UUA:9 a=S8i00vhjZExNoYhx:21 a=MTQ9Np52sIIizrW4:21 a=Yfhq0B]",
            "[w2zJhkqwCn:21 a=PA03WX8tBzeizutn5_OT:22]"
        ],
        "X-Spam": "[F=0.2000000000; CM=0.500; S=0.200(2015072901)]",
        "X-MAIL-FROM": "<arybchenko@solarflare.com>",
        "X-SOURCE-IP": "[12.187.104.26]",
        "Subject": "[dpdk-dev] [PATCH 03/56] net/sfc: import libefx register definitions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From Solarflare Communications Inc.\n\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/efx/base/efx_regs.h     | 3870 +++++++++++++++++++++++++++++++\n drivers/net/sfc/efx/base/efx_regs_pci.h | 2356 +++++++++++++++++++\n 2 files changed, 6226 insertions(+)\n create mode 100644 drivers/net/sfc/efx/base/efx_regs.h\n create mode 100644 drivers/net/sfc/efx/base/efx_regs_pci.h",
    "diff": "diff --git a/drivers/net/sfc/efx/base/efx_regs.h b/drivers/net/sfc/efx/base/efx_regs.h\nnew file mode 100644\nindex 0000000..a1a7f9d\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_regs.h\n@@ -0,0 +1,3870 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#ifndef\t_SYS_EFX_REGS_H\n+#define\t_SYS_EFX_REGS_H\n+\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+\n+/**************************************************************************\n+ *\n+ * Falcon/Siena registers and descriptors\n+ *\n+ **************************************************************************\n+ */\n+\n+/*\n+ * FR_AB_EE_VPD_CFG0_REG_SF(128bit):\n+ * SPI/VPD configuration register 0\n+ */\n+#define\tFR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AB_EE_VPD_CFG0_REG(128bit):\n+ * SPI/VPD configuration register 0\n+ */\n+#define\tFR_AB_EE_VPD_CFG0_REG_OFST 0x00000140\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EE_SF_FASTRD_EN_LBN 127\n+#define\tFRF_AB_EE_SF_FASTRD_EN_WIDTH 1\n+#define\tFRF_AB_EE_SF_CLOCK_DIV_LBN 120\n+#define\tFRF_AB_EE_SF_CLOCK_DIV_WIDTH 7\n+#define\tFRF_AB_EE_VPD_WIP_POLL_LBN 119\n+#define\tFRF_AB_EE_VPD_WIP_POLL_WIDTH 1\n+#define\tFRF_AB_EE_EE_CLOCK_DIV_LBN 112\n+#define\tFRF_AB_EE_EE_CLOCK_DIV_WIDTH 7\n+#define\tFRF_AB_EE_EE_WR_TMR_VALUE_LBN 96\n+#define\tFRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16\n+#define\tFRF_AB_EE_VPDW_LENGTH_LBN 80\n+#define\tFRF_AB_EE_VPDW_LENGTH_WIDTH 15\n+#define\tFRF_AB_EE_VPDW_BASE_LBN 64\n+#define\tFRF_AB_EE_VPDW_BASE_WIDTH 15\n+#define\tFRF_AB_EE_VPD_WR_CMD_EN_LBN 56\n+#define\tFRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8\n+#define\tFRF_AB_EE_VPD_BASE_LBN 32\n+#define\tFRF_AB_EE_VPD_BASE_WIDTH 24\n+#define\tFRF_AB_EE_VPD_LENGTH_LBN 16\n+#define\tFRF_AB_EE_VPD_LENGTH_WIDTH 15\n+#define\tFRF_AB_EE_VPD_AD_SIZE_LBN 8\n+#define\tFRF_AB_EE_VPD_AD_SIZE_WIDTH 5\n+#define\tFRF_AB_EE_VPD_ACCESS_ON_LBN 5\n+#define\tFRF_AB_EE_VPD_ACCESS_ON_WIDTH 1\n+#define\tFRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4\n+#define\tFRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1\n+#define\tFRF_AB_EE_VPD_DEV_SF_SEL_LBN 2\n+#define\tFRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1\n+#define\tFRF_AB_EE_VPD_EN_AD9_MODE_LBN 1\n+#define\tFRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1\n+#define\tFRF_AB_EE_VPD_EN_LBN 0\n+#define\tFRF_AB_EE_VPD_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):\n+ * PCIE SerDes control register 0 to 3\n+ */\n+#define\tFR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AB_PCIE_SD_CTL0123_REG(128bit):\n+ * PCIE SerDes control register 0 to 3\n+ */\n+#define\tFR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_PCIE_TESTSIG_H_LBN 96\n+#define\tFRF_AB_PCIE_TESTSIG_H_WIDTH 19\n+#define\tFRF_AB_PCIE_TESTSIG_L_LBN 64\n+#define\tFRF_AB_PCIE_TESTSIG_L_WIDTH 19\n+#define\tFRF_AB_PCIE_OFFSET_LBN 56\n+#define\tFRF_AB_PCIE_OFFSET_WIDTH 8\n+#define\tFRF_AB_PCIE_OFFSETEN_H_LBN 55\n+#define\tFRF_AB_PCIE_OFFSETEN_H_WIDTH 1\n+#define\tFRF_AB_PCIE_OFFSETEN_L_LBN 54\n+#define\tFRF_AB_PCIE_OFFSETEN_L_WIDTH 1\n+#define\tFRF_AB_PCIE_HIVMODE_H_LBN 53\n+#define\tFRF_AB_PCIE_HIVMODE_H_WIDTH 1\n+#define\tFRF_AB_PCIE_HIVMODE_L_LBN 52\n+#define\tFRF_AB_PCIE_HIVMODE_L_WIDTH 1\n+#define\tFRF_AB_PCIE_PARRESET_H_LBN 51\n+#define\tFRF_AB_PCIE_PARRESET_H_WIDTH 1\n+#define\tFRF_AB_PCIE_PARRESET_L_LBN 50\n+#define\tFRF_AB_PCIE_PARRESET_L_WIDTH 1\n+#define\tFRF_AB_PCIE_LPBKWDRV_H_LBN 49\n+#define\tFRF_AB_PCIE_LPBKWDRV_H_WIDTH 1\n+#define\tFRF_AB_PCIE_LPBKWDRV_L_LBN 48\n+#define\tFRF_AB_PCIE_LPBKWDRV_L_WIDTH 1\n+#define\tFRF_AB_PCIE_LPBK_LBN 40\n+#define\tFRF_AB_PCIE_LPBK_WIDTH 8\n+#define\tFRF_AB_PCIE_PARLPBK_LBN 32\n+#define\tFRF_AB_PCIE_PARLPBK_WIDTH 8\n+#define\tFRF_AB_PCIE_RXTERMADJ_H_LBN 30\n+#define\tFRF_AB_PCIE_RXTERMADJ_H_WIDTH 2\n+#define\tFRF_AB_PCIE_RXTERMADJ_L_LBN 28\n+#define\tFRF_AB_PCIE_RXTERMADJ_L_WIDTH 2\n+#define\tFFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3\n+#define\tFFE_AB_PCIE_RXTERMADJ_PL10PCNT 2\n+#define\tFFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1\n+#define\tFFE_AB_PCIE_RXTERMADJ_NOMNL 0\n+#define\tFRF_AB_PCIE_TXTERMADJ_H_LBN 26\n+#define\tFRF_AB_PCIE_TXTERMADJ_H_WIDTH 2\n+#define\tFRF_AB_PCIE_TXTERMADJ_L_LBN 24\n+#define\tFRF_AB_PCIE_TXTERMADJ_L_WIDTH 2\n+#define\tFFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3\n+#define\tFFE_AB_PCIE_TXTERMADJ_PL10PCNT 2\n+#define\tFFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1\n+#define\tFFE_AB_PCIE_TXTERMADJ_NOMNL 0\n+#define\tFRF_AB_PCIE_RXEQCTL_H_LBN 18\n+#define\tFRF_AB_PCIE_RXEQCTL_H_WIDTH 2\n+#define\tFRF_AB_PCIE_RXEQCTL_L_LBN 16\n+#define\tFRF_AB_PCIE_RXEQCTL_L_WIDTH 2\n+#define\tFFE_AB_PCIE_RXEQCTL_OFF_ALT 3\n+#define\tFFE_AB_PCIE_RXEQCTL_OFF 2\n+#define\tFFE_AB_PCIE_RXEQCTL_MIN 1\n+#define\tFFE_AB_PCIE_RXEQCTL_MAX 0\n+#define\tFRF_AB_PCIE_HIDRV_LBN 8\n+#define\tFRF_AB_PCIE_HIDRV_WIDTH 8\n+#define\tFRF_AB_PCIE_LODRV_LBN 0\n+#define\tFRF_AB_PCIE_LODRV_WIDTH 8\n+\n+\n+/*\n+ * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):\n+ * PCIE SerDes control register 4 and 5\n+ */\n+#define\tFR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AB_PCIE_SD_CTL45_REG(128bit):\n+ * PCIE SerDes control register 4 and 5\n+ */\n+#define\tFR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_PCIE_DTX7_LBN 60\n+#define\tFRF_AB_PCIE_DTX7_WIDTH 4\n+#define\tFRF_AB_PCIE_DTX6_LBN 56\n+#define\tFRF_AB_PCIE_DTX6_WIDTH 4\n+#define\tFRF_AB_PCIE_DTX5_LBN 52\n+#define\tFRF_AB_PCIE_DTX5_WIDTH 4\n+#define\tFRF_AB_PCIE_DTX4_LBN 48\n+#define\tFRF_AB_PCIE_DTX4_WIDTH 4\n+#define\tFRF_AB_PCIE_DTX3_LBN 44\n+#define\tFRF_AB_PCIE_DTX3_WIDTH 4\n+#define\tFRF_AB_PCIE_DTX2_LBN 40\n+#define\tFRF_AB_PCIE_DTX2_WIDTH 4\n+#define\tFRF_AB_PCIE_DTX1_LBN 36\n+#define\tFRF_AB_PCIE_DTX1_WIDTH 4\n+#define\tFRF_AB_PCIE_DTX0_LBN 32\n+#define\tFRF_AB_PCIE_DTX0_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ7_LBN 28\n+#define\tFRF_AB_PCIE_DEQ7_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ6_LBN 24\n+#define\tFRF_AB_PCIE_DEQ6_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ5_LBN 20\n+#define\tFRF_AB_PCIE_DEQ5_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ4_LBN 16\n+#define\tFRF_AB_PCIE_DEQ4_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ3_LBN 12\n+#define\tFRF_AB_PCIE_DEQ3_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ2_LBN 8\n+#define\tFRF_AB_PCIE_DEQ2_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ1_LBN 4\n+#define\tFRF_AB_PCIE_DEQ1_WIDTH 4\n+#define\tFRF_AB_PCIE_DEQ0_LBN 0\n+#define\tFRF_AB_PCIE_DEQ0_WIDTH 4\n+\n+\n+/*\n+ * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):\n+ * PCIE PCS control and status register\n+ */\n+#define\tFR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):\n+ * PCIE PCS control and status register\n+ */\n+#define\tFR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52\n+#define\tFRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4\n+#define\tFRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48\n+#define\tFRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4\n+#define\tFRF_AB_PCIE_PRBSERR_LBN 40\n+#define\tFRF_AB_PCIE_PRBSERR_WIDTH 8\n+#define\tFRF_AB_PCIE_PRBSERRH0_LBN 32\n+#define\tFRF_AB_PCIE_PRBSERRH0_WIDTH 8\n+#define\tFRF_AB_PCIE_FASTINIT_H_LBN 15\n+#define\tFRF_AB_PCIE_FASTINIT_H_WIDTH 1\n+#define\tFRF_AB_PCIE_FASTINIT_L_LBN 14\n+#define\tFRF_AB_PCIE_FASTINIT_L_WIDTH 1\n+#define\tFRF_AB_PCIE_CTCDISABLE_H_LBN 13\n+#define\tFRF_AB_PCIE_CTCDISABLE_H_WIDTH 1\n+#define\tFRF_AB_PCIE_CTCDISABLE_L_LBN 12\n+#define\tFRF_AB_PCIE_CTCDISABLE_L_WIDTH 1\n+#define\tFRF_AB_PCIE_PRBSSYNC_H_LBN 11\n+#define\tFRF_AB_PCIE_PRBSSYNC_H_WIDTH 1\n+#define\tFRF_AB_PCIE_PRBSSYNC_L_LBN 10\n+#define\tFRF_AB_PCIE_PRBSSYNC_L_WIDTH 1\n+#define\tFRF_AB_PCIE_PRBSERRACK_H_LBN 9\n+#define\tFRF_AB_PCIE_PRBSERRACK_H_WIDTH 1\n+#define\tFRF_AB_PCIE_PRBSERRACK_L_LBN 8\n+#define\tFRF_AB_PCIE_PRBSERRACK_L_WIDTH 1\n+#define\tFRF_AB_PCIE_PRBSSEL_LBN 0\n+#define\tFRF_AB_PCIE_PRBSSEL_WIDTH 8\n+\n+\n+/*\n+ * FR_AB_HW_INIT_REG_SF(128bit):\n+ * Hardware initialization register\n+ */\n+#define\tFR_AB_HW_INIT_REG_SF_OFST 0x00000350\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AZ_HW_INIT_REG(128bit):\n+ * Hardware initialization register\n+ */\n+#define\tFR_AZ_HW_INIT_REG_OFST 0x000000c0\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_BB_BDMRD_CPLF_FULL_LBN 124\n+#define\tFRF_BB_BDMRD_CPLF_FULL_WIDTH 1\n+#define\tFRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121\n+#define\tFRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3\n+#define\tFRF_CZ_TX_MRG_TAGS_LBN 120\n+#define\tFRF_CZ_TX_MRG_TAGS_WIDTH 1\n+#define\tFRF_AZ_TRGT_MASK_ALL_LBN 100\n+#define\tFRF_AZ_TRGT_MASK_ALL_WIDTH 1\n+#define\tFRF_AZ_DOORBELL_DROP_LBN 92\n+#define\tFRF_AZ_DOORBELL_DROP_WIDTH 8\n+#define\tFRF_AB_TX_RREQ_MASK_EN_LBN 76\n+#define\tFRF_AB_TX_RREQ_MASK_EN_WIDTH 1\n+#define\tFRF_AB_PE_EIDLE_DIS_LBN 75\n+#define\tFRF_AB_PE_EIDLE_DIS_WIDTH 1\n+#define\tFRF_AZ_FC_BLOCKING_EN_LBN 45\n+#define\tFRF_AZ_FC_BLOCKING_EN_WIDTH 1\n+#define\tFRF_AZ_B2B_REQ_EN_LBN 44\n+#define\tFRF_AZ_B2B_REQ_EN_WIDTH 1\n+#define\tFRF_AZ_POST_WR_MASK_LBN 40\n+#define\tFRF_AZ_POST_WR_MASK_WIDTH 4\n+#define\tFRF_AZ_TLP_TC_LBN 34\n+#define\tFRF_AZ_TLP_TC_WIDTH 3\n+#define\tFRF_AZ_TLP_ATTR_LBN 32\n+#define\tFRF_AZ_TLP_ATTR_WIDTH 2\n+#define\tFRF_AB_INTB_VEC_LBN 24\n+#define\tFRF_AB_INTB_VEC_WIDTH 5\n+#define\tFRF_AB_INTA_VEC_LBN 16\n+#define\tFRF_AB_INTA_VEC_WIDTH 5\n+#define\tFRF_AZ_WD_TIMER_LBN 8\n+#define\tFRF_AZ_WD_TIMER_WIDTH 8\n+#define\tFRF_AZ_US_DISABLE_LBN 5\n+#define\tFRF_AZ_US_DISABLE_WIDTH 1\n+#define\tFRF_AZ_TLP_EP_LBN 4\n+#define\tFRF_AZ_TLP_EP_WIDTH 1\n+#define\tFRF_AZ_ATTR_SEL_LBN 3\n+#define\tFRF_AZ_ATTR_SEL_WIDTH 1\n+#define\tFRF_AZ_TD_SEL_LBN 1\n+#define\tFRF_AZ_TD_SEL_WIDTH 1\n+#define\tFRF_AZ_TLP_TD_LBN 0\n+#define\tFRF_AZ_TLP_TD_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_NIC_STAT_REG_SF(128bit):\n+ * NIC status register\n+ */\n+#define\tFR_AB_NIC_STAT_REG_SF_OFST 0x00000360\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AB_NIC_STAT_REG(128bit):\n+ * NIC status register\n+ */\n+#define\tFR_AB_NIC_STAT_REG_OFST 0x00000200\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_BB_AER_DIS_LBN 34\n+#define\tFRF_BB_AER_DIS_WIDTH 1\n+#define\tFRF_BB_EE_STRAP_EN_LBN 31\n+#define\tFRF_BB_EE_STRAP_EN_WIDTH 1\n+#define\tFRF_BB_EE_STRAP_LBN 24\n+#define\tFRF_BB_EE_STRAP_WIDTH 4\n+#define\tFRF_BB_REVISION_ID_LBN 17\n+#define\tFRF_BB_REVISION_ID_WIDTH 7\n+#define\tFRF_AB_ONCHIP_SRAM_LBN 16\n+#define\tFRF_AB_ONCHIP_SRAM_WIDTH 1\n+#define\tFRF_AB_SF_PRST_LBN 9\n+#define\tFRF_AB_SF_PRST_WIDTH 1\n+#define\tFRF_AB_EE_PRST_LBN 8\n+#define\tFRF_AB_EE_PRST_WIDTH 1\n+#define\tFRF_AB_ATE_MODE_LBN 3\n+#define\tFRF_AB_ATE_MODE_WIDTH 1\n+#define\tFRF_AB_STRAP_PINS_LBN 0\n+#define\tFRF_AB_STRAP_PINS_WIDTH 3\n+\n+\n+/*\n+ * FR_AB_GLB_CTL_REG_SF(128bit):\n+ * Global control register\n+ */\n+#define\tFR_AB_GLB_CTL_REG_SF_OFST 0x00000370\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AB_GLB_CTL_REG(128bit):\n+ * Global control register\n+ */\n+#define\tFR_AB_GLB_CTL_REG_OFST 0x00000220\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EXT_PHY_RST_CTL_LBN 63\n+#define\tFRF_AB_EXT_PHY_RST_CTL_WIDTH 1\n+#define\tFRF_AB_XAUI_SD_RST_CTL_LBN 62\n+#define\tFRF_AB_XAUI_SD_RST_CTL_WIDTH 1\n+#define\tFRF_AB_PCIE_SD_RST_CTL_LBN 61\n+#define\tFRF_AB_PCIE_SD_RST_CTL_WIDTH 1\n+#define\tFRF_AA_PCIX_RST_CTL_LBN 60\n+#define\tFRF_AA_PCIX_RST_CTL_WIDTH 1\n+#define\tFRF_BB_BIU_RST_CTL_LBN 60\n+#define\tFRF_BB_BIU_RST_CTL_WIDTH 1\n+#define\tFRF_AB_PCIE_STKY_RST_CTL_LBN 59\n+#define\tFRF_AB_PCIE_STKY_RST_CTL_WIDTH 1\n+#define\tFRF_AB_PCIE_NSTKY_RST_CTL_LBN 58\n+#define\tFRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1\n+#define\tFRF_AB_PCIE_CORE_RST_CTL_LBN 57\n+#define\tFRF_AB_PCIE_CORE_RST_CTL_WIDTH 1\n+#define\tFRF_AB_XGRX_RST_CTL_LBN 56\n+#define\tFRF_AB_XGRX_RST_CTL_WIDTH 1\n+#define\tFRF_AB_XGTX_RST_CTL_LBN 55\n+#define\tFRF_AB_XGTX_RST_CTL_WIDTH 1\n+#define\tFRF_AB_EM_RST_CTL_LBN 54\n+#define\tFRF_AB_EM_RST_CTL_WIDTH 1\n+#define\tFRF_AB_EV_RST_CTL_LBN 53\n+#define\tFRF_AB_EV_RST_CTL_WIDTH 1\n+#define\tFRF_AB_SR_RST_CTL_LBN 52\n+#define\tFRF_AB_SR_RST_CTL_WIDTH 1\n+#define\tFRF_AB_RX_RST_CTL_LBN 51\n+#define\tFRF_AB_RX_RST_CTL_WIDTH 1\n+#define\tFRF_AB_TX_RST_CTL_LBN 50\n+#define\tFRF_AB_TX_RST_CTL_WIDTH 1\n+#define\tFRF_AB_EE_RST_CTL_LBN 49\n+#define\tFRF_AB_EE_RST_CTL_WIDTH 1\n+#define\tFRF_AB_CS_RST_CTL_LBN 48\n+#define\tFRF_AB_CS_RST_CTL_WIDTH 1\n+#define\tFRF_AB_HOT_RST_CTL_LBN 40\n+#define\tFRF_AB_HOT_RST_CTL_WIDTH 2\n+#define\tFRF_AB_RST_EXT_PHY_LBN 31\n+#define\tFRF_AB_RST_EXT_PHY_WIDTH 1\n+#define\tFRF_AB_RST_XAUI_SD_LBN 30\n+#define\tFRF_AB_RST_XAUI_SD_WIDTH 1\n+#define\tFRF_AB_RST_PCIE_SD_LBN 29\n+#define\tFRF_AB_RST_PCIE_SD_WIDTH 1\n+#define\tFRF_AA_RST_PCIX_LBN 28\n+#define\tFRF_AA_RST_PCIX_WIDTH 1\n+#define\tFRF_BB_RST_BIU_LBN 28\n+#define\tFRF_BB_RST_BIU_WIDTH 1\n+#define\tFRF_AB_RST_PCIE_STKY_LBN 27\n+#define\tFRF_AB_RST_PCIE_STKY_WIDTH 1\n+#define\tFRF_AB_RST_PCIE_NSTKY_LBN 26\n+#define\tFRF_AB_RST_PCIE_NSTKY_WIDTH 1\n+#define\tFRF_AB_RST_PCIE_CORE_LBN 25\n+#define\tFRF_AB_RST_PCIE_CORE_WIDTH 1\n+#define\tFRF_AB_RST_XGRX_LBN 24\n+#define\tFRF_AB_RST_XGRX_WIDTH 1\n+#define\tFRF_AB_RST_XGTX_LBN 23\n+#define\tFRF_AB_RST_XGTX_WIDTH 1\n+#define\tFRF_AB_RST_EM_LBN 22\n+#define\tFRF_AB_RST_EM_WIDTH 1\n+#define\tFRF_AB_RST_EV_LBN 21\n+#define\tFRF_AB_RST_EV_WIDTH 1\n+#define\tFRF_AB_RST_SR_LBN 20\n+#define\tFRF_AB_RST_SR_WIDTH 1\n+#define\tFRF_AB_RST_RX_LBN 19\n+#define\tFRF_AB_RST_RX_WIDTH 1\n+#define\tFRF_AB_RST_TX_LBN 18\n+#define\tFRF_AB_RST_TX_WIDTH 1\n+#define\tFRF_AB_RST_SF_LBN 17\n+#define\tFRF_AB_RST_SF_WIDTH 1\n+#define\tFRF_AB_RST_CS_LBN 16\n+#define\tFRF_AB_RST_CS_WIDTH 1\n+#define\tFRF_AB_INT_RST_DUR_LBN 4\n+#define\tFRF_AB_INT_RST_DUR_WIDTH 3\n+#define\tFRF_AB_EXT_PHY_RST_DUR_LBN 1\n+#define\tFRF_AB_EXT_PHY_RST_DUR_WIDTH 3\n+#define\tFFE_AB_EXT_PHY_RST_DUR_10240US 7\n+#define\tFFE_AB_EXT_PHY_RST_DUR_5120US 6\n+#define\tFFE_AB_EXT_PHY_RST_DUR_2560US 5\n+#define\tFFE_AB_EXT_PHY_RST_DUR_1280US 4\n+#define\tFFE_AB_EXT_PHY_RST_DUR_640US 3\n+#define\tFFE_AB_EXT_PHY_RST_DUR_320US 2\n+#define\tFFE_AB_EXT_PHY_RST_DUR_160US 1\n+#define\tFFE_AB_EXT_PHY_RST_DUR_80US 0\n+#define\tFRF_AB_SWRST_LBN 0\n+#define\tFRF_AB_SWRST_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_IOM_IND_ADR_REG(32bit):\n+ * IO-mapped indirect access address register\n+ */\n+#define\tFR_AZ_IOM_IND_ADR_REG_OFST 0x00000000\n+/* falcona0,falconb0,sienaa0=net_func_bar0 */\n+\n+#define\tFRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24\n+#define\tFRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1\n+#define\tFRF_AZ_IOM_IND_ADR_LBN 0\n+#define\tFRF_AZ_IOM_IND_ADR_WIDTH 24\n+\n+\n+/*\n+ * FR_AZ_IOM_IND_DAT_REG(32bit):\n+ * IO-mapped indirect access data register\n+ */\n+#define\tFR_AZ_IOM_IND_DAT_REG_OFST 0x00000004\n+/* falcona0,falconb0,sienaa0=net_func_bar0 */\n+\n+#define\tFRF_AZ_IOM_IND_DAT_LBN 0\n+#define\tFRF_AZ_IOM_IND_DAT_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_ADR_REGION_REG(128bit):\n+ * Address region register\n+ */\n+#define\tFR_AZ_ADR_REGION_REG_OFST 0x00000000\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_ADR_REGION3_LBN 96\n+#define\tFRF_AZ_ADR_REGION3_WIDTH 18\n+#define\tFRF_AZ_ADR_REGION2_LBN 64\n+#define\tFRF_AZ_ADR_REGION2_WIDTH 18\n+#define\tFRF_AZ_ADR_REGION1_LBN 32\n+#define\tFRF_AZ_ADR_REGION1_WIDTH 18\n+#define\tFRF_AZ_ADR_REGION0_LBN 0\n+#define\tFRF_AZ_ADR_REGION0_WIDTH 18\n+\n+\n+/*\n+ * FR_AZ_INT_EN_REG_KER(128bit):\n+ * Kernel driver Interrupt enable register\n+ */\n+#define\tFR_AZ_INT_EN_REG_KER_OFST 0x00000010\n+/* falcona0,falconb0,sienaa0=net_func_bar2 */\n+\n+#define\tFRF_AZ_KER_INT_LEVE_SEL_LBN 8\n+#define\tFRF_AZ_KER_INT_LEVE_SEL_WIDTH 6\n+#define\tFRF_AZ_KER_INT_CHAR_LBN 4\n+#define\tFRF_AZ_KER_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_KER_INT_KER_LBN 3\n+#define\tFRF_AZ_KER_INT_KER_WIDTH 1\n+#define\tFRF_AZ_DRV_INT_EN_KER_LBN 0\n+#define\tFRF_AZ_DRV_INT_EN_KER_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_INT_EN_REG_CHAR(128bit):\n+ * Char Driver interrupt enable register\n+ */\n+#define\tFR_AZ_INT_EN_REG_CHAR_OFST 0x00000020\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_CHAR_INT_LEVE_SEL_LBN 8\n+#define\tFRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6\n+#define\tFRF_AZ_CHAR_INT_CHAR_LBN 4\n+#define\tFRF_AZ_CHAR_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_CHAR_INT_KER_LBN 3\n+#define\tFRF_AZ_CHAR_INT_KER_WIDTH 1\n+#define\tFRF_AZ_DRV_INT_EN_CHAR_LBN 0\n+#define\tFRF_AZ_DRV_INT_EN_CHAR_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_INT_ADR_REG_KER(128bit):\n+ * Interrupt host address for Kernel driver\n+ */\n+#define\tFR_AZ_INT_ADR_REG_KER_OFST 0x00000030\n+/* falcona0,falconb0,sienaa0=net_func_bar2 */\n+\n+#define\tFRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64\n+#define\tFRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1\n+#define\tFRF_AZ_INT_ADR_KER_LBN 0\n+#define\tFRF_AZ_INT_ADR_KER_WIDTH 64\n+#define\tFRF_AZ_INT_ADR_KER_DW0_LBN 0\n+#define\tFRF_AZ_INT_ADR_KER_DW0_WIDTH 32\n+#define\tFRF_AZ_INT_ADR_KER_DW1_LBN 32\n+#define\tFRF_AZ_INT_ADR_KER_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_INT_ADR_REG_CHAR(128bit):\n+ * Interrupt host address for Char driver\n+ */\n+#define\tFR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64\n+#define\tFRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1\n+#define\tFRF_AZ_INT_ADR_CHAR_LBN 0\n+#define\tFRF_AZ_INT_ADR_CHAR_WIDTH 64\n+#define\tFRF_AZ_INT_ADR_CHAR_DW0_LBN 0\n+#define\tFRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32\n+#define\tFRF_AZ_INT_ADR_CHAR_DW1_LBN 32\n+#define\tFRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AA_INT_ACK_KER(32bit):\n+ * Kernel interrupt acknowledge register\n+ */\n+#define\tFR_AA_INT_ACK_KER_OFST 0x00000050\n+/* falcona0=net_func_bar2 */\n+\n+#define\tFRF_AA_INT_ACK_KER_FIELD_LBN 0\n+#define\tFRF_AA_INT_ACK_KER_FIELD_WIDTH 32\n+\n+\n+/*\n+ * FR_BZ_INT_ISR0_REG(128bit):\n+ * Function 0 Interrupt Acknowlege Status register\n+ */\n+#define\tFR_BZ_INT_ISR0_REG_OFST 0x00000090\n+/* falconb0,sienaa0=net_func_bar2 */\n+\n+#define\tFRF_BZ_INT_ISR_REG_LBN 0\n+#define\tFRF_BZ_INT_ISR_REG_WIDTH 64\n+#define\tFRF_BZ_INT_ISR_REG_DW0_LBN 0\n+#define\tFRF_BZ_INT_ISR_REG_DW0_WIDTH 32\n+#define\tFRF_BZ_INT_ISR_REG_DW1_LBN 32\n+#define\tFRF_BZ_INT_ISR_REG_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AB_EE_SPI_HCMD_REG(128bit):\n+ * SPI host command register\n+ */\n+#define\tFR_AB_EE_SPI_HCMD_REG_OFST 0x00000100\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31\n+#define\tFRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1\n+#define\tFRF_AB_EE_WR_TIMER_ACTIVE_LBN 28\n+#define\tFRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1\n+#define\tFRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24\n+#define\tFRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1\n+#define\tFRF_AB_EE_SPI_HCMD_DABCNT_LBN 16\n+#define\tFRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5\n+#define\tFRF_AB_EE_SPI_HCMD_READ_LBN 15\n+#define\tFRF_AB_EE_SPI_HCMD_READ_WIDTH 1\n+#define\tFRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12\n+#define\tFRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2\n+#define\tFRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8\n+#define\tFRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2\n+#define\tFRF_AB_EE_SPI_HCMD_ENC_LBN 0\n+#define\tFRF_AB_EE_SPI_HCMD_ENC_WIDTH 8\n+\n+\n+/*\n+ * FR_CZ_USR_EV_CFG(32bit):\n+ * User Level Event Configuration register\n+ */\n+#define\tFR_CZ_USR_EV_CFG_OFST 0x00000100\n+/* sienaa0=net_func_bar2 */\n+\n+#define\tFRF_CZ_USREV_DIS_LBN 16\n+#define\tFRF_CZ_USREV_DIS_WIDTH 1\n+#define\tFRF_CZ_DFLT_EVQ_LBN 0\n+#define\tFRF_CZ_DFLT_EVQ_WIDTH 10\n+\n+\n+/*\n+ * FR_AB_EE_SPI_HADR_REG(128bit):\n+ * SPI host address register\n+ */\n+#define\tFR_AB_EE_SPI_HADR_REG_OFST 0x00000110\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EE_SPI_HADR_DUBYTE_LBN 24\n+#define\tFRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8\n+#define\tFRF_AB_EE_SPI_HADR_ADR_LBN 0\n+#define\tFRF_AB_EE_SPI_HADR_ADR_WIDTH 24\n+\n+\n+/*\n+ * FR_AB_EE_SPI_HDATA_REG(128bit):\n+ * SPI host data register\n+ */\n+#define\tFR_AB_EE_SPI_HDATA_REG_OFST 0x00000120\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EE_SPI_HDATA3_LBN 96\n+#define\tFRF_AB_EE_SPI_HDATA3_WIDTH 32\n+#define\tFRF_AB_EE_SPI_HDATA2_LBN 64\n+#define\tFRF_AB_EE_SPI_HDATA2_WIDTH 32\n+#define\tFRF_AB_EE_SPI_HDATA1_LBN 32\n+#define\tFRF_AB_EE_SPI_HDATA1_WIDTH 32\n+#define\tFRF_AB_EE_SPI_HDATA0_LBN 0\n+#define\tFRF_AB_EE_SPI_HDATA0_WIDTH 32\n+\n+\n+/*\n+ * FR_AB_EE_BASE_PAGE_REG(128bit):\n+ * Expansion ROM base mirror register\n+ */\n+#define\tFR_AB_EE_BASE_PAGE_REG_OFST 0x00000130\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EE_EXPROM_MASK_LBN 16\n+#define\tFRF_AB_EE_EXPROM_MASK_WIDTH 13\n+#define\tFRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0\n+#define\tFRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13\n+\n+\n+/*\n+ * FR_AB_EE_VPD_SW_CNTL_REG(128bit):\n+ * VPD access SW control register\n+ */\n+#define\tFR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EE_VPD_CYCLE_PENDING_LBN 31\n+#define\tFRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1\n+#define\tFRF_AB_EE_VPD_CYC_WRITE_LBN 28\n+#define\tFRF_AB_EE_VPD_CYC_WRITE_WIDTH 1\n+#define\tFRF_AB_EE_VPD_CYC_ADR_LBN 0\n+#define\tFRF_AB_EE_VPD_CYC_ADR_WIDTH 15\n+\n+\n+/*\n+ * FR_AB_EE_VPD_SW_DATA_REG(128bit):\n+ * VPD access SW data register\n+ */\n+#define\tFR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_EE_VPD_CYC_DAT_LBN 0\n+#define\tFRF_AB_EE_VPD_CYC_DAT_WIDTH 32\n+\n+\n+/*\n+ * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):\n+ * Indirect Access to PCIE Core registers\n+ */\n+#define\tFR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0\n+/* falconb0=net_func_bar2 */\n+\n+#define\tFRF_BB_PCIE_CORE_TARGET_DATA_LBN 32\n+#define\tFRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32\n+#define\tFRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15\n+#define\tFRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1\n+#define\tFRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0\n+#define\tFRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12\n+\n+\n+/*\n+ * FR_AB_GPIO_CTL_REG(128bit):\n+ * GPIO control register\n+ */\n+#define\tFR_AB_GPIO_CTL_REG_OFST 0x00000210\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GPIO15_OEN_LBN 63\n+#define\tFRF_AB_GPIO15_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO14_OEN_LBN 62\n+#define\tFRF_AB_GPIO14_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO13_OEN_LBN 61\n+#define\tFRF_AB_GPIO13_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO12_OEN_LBN 60\n+#define\tFRF_AB_GPIO12_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO11_OEN_LBN 59\n+#define\tFRF_AB_GPIO11_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO10_OEN_LBN 58\n+#define\tFRF_AB_GPIO10_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO9_OEN_LBN 57\n+#define\tFRF_AB_GPIO9_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO8_OEN_LBN 56\n+#define\tFRF_AB_GPIO8_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO15_OUT_LBN 55\n+#define\tFRF_AB_GPIO15_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO14_OUT_LBN 54\n+#define\tFRF_AB_GPIO14_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO13_OUT_LBN 53\n+#define\tFRF_AB_GPIO13_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO12_OUT_LBN 52\n+#define\tFRF_AB_GPIO12_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO11_OUT_LBN 51\n+#define\tFRF_AB_GPIO11_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO10_OUT_LBN 50\n+#define\tFRF_AB_GPIO10_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO9_OUT_LBN 49\n+#define\tFRF_AB_GPIO9_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO8_OUT_LBN 48\n+#define\tFRF_AB_GPIO8_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO15_IN_LBN 47\n+#define\tFRF_AB_GPIO15_IN_WIDTH 1\n+#define\tFRF_AB_GPIO14_IN_LBN 46\n+#define\tFRF_AB_GPIO14_IN_WIDTH 1\n+#define\tFRF_AB_GPIO13_IN_LBN 45\n+#define\tFRF_AB_GPIO13_IN_WIDTH 1\n+#define\tFRF_AB_GPIO12_IN_LBN 44\n+#define\tFRF_AB_GPIO12_IN_WIDTH 1\n+#define\tFRF_AB_GPIO11_IN_LBN 43\n+#define\tFRF_AB_GPIO11_IN_WIDTH 1\n+#define\tFRF_AB_GPIO10_IN_LBN 42\n+#define\tFRF_AB_GPIO10_IN_WIDTH 1\n+#define\tFRF_AB_GPIO9_IN_LBN 41\n+#define\tFRF_AB_GPIO9_IN_WIDTH 1\n+#define\tFRF_AB_GPIO8_IN_LBN 40\n+#define\tFRF_AB_GPIO8_IN_WIDTH 1\n+#define\tFRF_AB_GPIO15_PWRUP_VALUE_LBN 39\n+#define\tFRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO14_PWRUP_VALUE_LBN 38\n+#define\tFRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO13_PWRUP_VALUE_LBN 37\n+#define\tFRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO12_PWRUP_VALUE_LBN 36\n+#define\tFRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO11_PWRUP_VALUE_LBN 35\n+#define\tFRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO10_PWRUP_VALUE_LBN 34\n+#define\tFRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO9_PWRUP_VALUE_LBN 33\n+#define\tFRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO8_PWRUP_VALUE_LBN 32\n+#define\tFRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_BB_CLK156_OUT_EN_LBN 31\n+#define\tFRF_BB_CLK156_OUT_EN_WIDTH 1\n+#define\tFRF_BB_USE_NIC_CLK_LBN 30\n+#define\tFRF_BB_USE_NIC_CLK_WIDTH 1\n+#define\tFRF_AB_GPIO5_OEN_LBN 29\n+#define\tFRF_AB_GPIO5_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO4_OEN_LBN 28\n+#define\tFRF_AB_GPIO4_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO3_OEN_LBN 27\n+#define\tFRF_AB_GPIO3_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO2_OEN_LBN 26\n+#define\tFRF_AB_GPIO2_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO1_OEN_LBN 25\n+#define\tFRF_AB_GPIO1_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO0_OEN_LBN 24\n+#define\tFRF_AB_GPIO0_OEN_WIDTH 1\n+#define\tFRF_AB_GPIO5_OUT_LBN 21\n+#define\tFRF_AB_GPIO5_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO4_OUT_LBN 20\n+#define\tFRF_AB_GPIO4_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO3_OUT_LBN 19\n+#define\tFRF_AB_GPIO3_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO2_OUT_LBN 18\n+#define\tFRF_AB_GPIO2_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO1_OUT_LBN 17\n+#define\tFRF_AB_GPIO1_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO0_OUT_LBN 16\n+#define\tFRF_AB_GPIO0_OUT_WIDTH 1\n+#define\tFRF_AB_GPIO5_IN_LBN 13\n+#define\tFRF_AB_GPIO5_IN_WIDTH 1\n+#define\tFRF_AB_GPIO4_IN_LBN 12\n+#define\tFRF_AB_GPIO4_IN_WIDTH 1\n+#define\tFRF_AB_GPIO3_IN_LBN 11\n+#define\tFRF_AB_GPIO3_IN_WIDTH 1\n+#define\tFRF_AB_GPIO2_IN_LBN 10\n+#define\tFRF_AB_GPIO2_IN_WIDTH 1\n+#define\tFRF_AB_GPIO1_IN_LBN 9\n+#define\tFRF_AB_GPIO1_IN_WIDTH 1\n+#define\tFRF_AB_GPIO0_IN_LBN 8\n+#define\tFRF_AB_GPIO0_IN_WIDTH 1\n+#define\tFRF_AB_GPIO5_PWRUP_VALUE_LBN 5\n+#define\tFRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO4_PWRUP_VALUE_LBN 4\n+#define\tFRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO3_PWRUP_VALUE_LBN 3\n+#define\tFRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO2_PWRUP_VALUE_LBN 2\n+#define\tFRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO1_PWRUP_VALUE_LBN 1\n+#define\tFRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1\n+#define\tFRF_AB_GPIO0_PWRUP_VALUE_LBN 0\n+#define\tFRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_FATAL_INTR_REG_KER(128bit):\n+ * Fatal interrupt register for Kernel\n+ */\n+#define\tFR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230\n+/* falcona0,falconb0,sienaa0=net_func_bar2 */\n+\n+#define\tFRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44\n+#define\tFRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1\n+#define\tFRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43\n+#define\tFRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1\n+#define\tFRF_CZ_MBU_PERR_INT_KER_EN_LBN 43\n+#define\tFRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42\n+#define\tFRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41\n+#define\tFRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_MEM_PERR_INT_KER_EN_LBN 40\n+#define\tFRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39\n+#define\tFRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38\n+#define\tFRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37\n+#define\tFRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36\n+#define\tFRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35\n+#define\tFRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34\n+#define\tFRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_ILL_ADR_INT_KER_EN_LBN 33\n+#define\tFRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1\n+#define\tFRF_AZ_SRM_PERR_INT_KER_EN_LBN 32\n+#define\tFRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1\n+#define\tFRF_CZ_SRAM_PERR_INT_P_KER_LBN 12\n+#define\tFRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1\n+#define\tFRF_AB_PCI_BUSERR_INT_KER_LBN 11\n+#define\tFRF_AB_PCI_BUSERR_INT_KER_WIDTH 1\n+#define\tFRF_CZ_MBU_PERR_INT_KER_LBN 11\n+#define\tFRF_CZ_MBU_PERR_INT_KER_WIDTH 1\n+#define\tFRF_AZ_SRAM_OOB_INT_KER_LBN 10\n+#define\tFRF_AZ_SRAM_OOB_INT_KER_WIDTH 1\n+#define\tFRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9\n+#define\tFRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1\n+#define\tFRF_AZ_MEM_PERR_INT_KER_LBN 8\n+#define\tFRF_AZ_MEM_PERR_INT_KER_WIDTH 1\n+#define\tFRF_AZ_RBUF_OWN_INT_KER_LBN 7\n+#define\tFRF_AZ_RBUF_OWN_INT_KER_WIDTH 1\n+#define\tFRF_AZ_TBUF_OWN_INT_KER_LBN 6\n+#define\tFRF_AZ_TBUF_OWN_INT_KER_WIDTH 1\n+#define\tFRF_AZ_RDESCQ_OWN_INT_KER_LBN 5\n+#define\tFRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1\n+#define\tFRF_AZ_TDESCQ_OWN_INT_KER_LBN 4\n+#define\tFRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1\n+#define\tFRF_AZ_EVQ_OWN_INT_KER_LBN 3\n+#define\tFRF_AZ_EVQ_OWN_INT_KER_WIDTH 1\n+#define\tFRF_AZ_EVF_OFLO_INT_KER_LBN 2\n+#define\tFRF_AZ_EVF_OFLO_INT_KER_WIDTH 1\n+#define\tFRF_AZ_ILL_ADR_INT_KER_LBN 1\n+#define\tFRF_AZ_ILL_ADR_INT_KER_WIDTH 1\n+#define\tFRF_AZ_SRM_PERR_INT_KER_LBN 0\n+#define\tFRF_AZ_SRM_PERR_INT_KER_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_FATAL_INTR_REG_CHAR(128bit):\n+ * Fatal interrupt register for Char\n+ */\n+#define\tFR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44\n+#define\tFRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1\n+#define\tFRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43\n+#define\tFRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43\n+#define\tFRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42\n+#define\tFRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41\n+#define\tFRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40\n+#define\tFRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39\n+#define\tFRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38\n+#define\tFRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37\n+#define\tFRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36\n+#define\tFRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35\n+#define\tFRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34\n+#define\tFRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33\n+#define\tFRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32\n+#define\tFRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1\n+#define\tFRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12\n+#define\tFRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1\n+#define\tFRF_AB_PCI_BUSERR_INT_CHAR_LBN 11\n+#define\tFRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1\n+#define\tFRF_CZ_MBU_PERR_INT_CHAR_LBN 11\n+#define\tFRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_SRAM_OOB_INT_CHAR_LBN 10\n+#define\tFRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9\n+#define\tFRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_MEM_PERR_INT_CHAR_LBN 8\n+#define\tFRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_RBUF_OWN_INT_CHAR_LBN 7\n+#define\tFRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_TBUF_OWN_INT_CHAR_LBN 6\n+#define\tFRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5\n+#define\tFRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4\n+#define\tFRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_EVQ_OWN_INT_CHAR_LBN 3\n+#define\tFRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_EVF_OFLO_INT_CHAR_LBN 2\n+#define\tFRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_ILL_ADR_INT_CHAR_LBN 1\n+#define\tFRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1\n+#define\tFRF_AZ_SRM_PERR_INT_CHAR_LBN 0\n+#define\tFRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_DP_CTRL_REG(128bit):\n+ * Datapath control register\n+ */\n+#define\tFR_AZ_DP_CTRL_REG_OFST 0x00000250\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_FLS_EVQ_ID_LBN 0\n+#define\tFRF_AZ_FLS_EVQ_ID_WIDTH 12\n+\n+\n+/*\n+ * FR_AZ_MEM_STAT_REG(128bit):\n+ * Memory status register\n+ */\n+#define\tFR_AZ_MEM_STAT_REG_OFST 0x00000260\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MEM_PERR_VEC_LBN 53\n+#define\tFRF_AB_MEM_PERR_VEC_WIDTH 40\n+#define\tFRF_AB_MEM_PERR_VEC_DW0_LBN 53\n+#define\tFRF_AB_MEM_PERR_VEC_DW0_WIDTH 32\n+#define\tFRF_AB_MEM_PERR_VEC_DW1_LBN 85\n+#define\tFRF_AB_MEM_PERR_VEC_DW1_WIDTH 6\n+#define\tFRF_AB_MBIST_CORR_LBN 38\n+#define\tFRF_AB_MBIST_CORR_WIDTH 15\n+#define\tFRF_AB_MBIST_ERR_LBN 0\n+#define\tFRF_AB_MBIST_ERR_WIDTH 40\n+#define\tFRF_AB_MBIST_ERR_DW0_LBN 0\n+#define\tFRF_AB_MBIST_ERR_DW0_WIDTH 32\n+#define\tFRF_AB_MBIST_ERR_DW1_LBN 32\n+#define\tFRF_AB_MBIST_ERR_DW1_WIDTH 6\n+#define\tFRF_CZ_MEM_PERR_VEC_LBN 0\n+#define\tFRF_CZ_MEM_PERR_VEC_WIDTH 35\n+#define\tFRF_CZ_MEM_PERR_VEC_DW0_LBN 0\n+#define\tFRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32\n+#define\tFRF_CZ_MEM_PERR_VEC_DW1_LBN 32\n+#define\tFRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3\n+\n+\n+/*\n+ * FR_PORT0_CS_DEBUG_REG(128bit):\n+ * Debug register\n+ */\n+\n+#define\tFR_AZ_CS_DEBUG_REG_OFST 0x00000270\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GLB_DEBUG2_SEL_LBN 50\n+#define\tFRF_AB_GLB_DEBUG2_SEL_WIDTH 3\n+#define\tFRF_AB_DEBUG_BLK_SEL2_LBN 47\n+#define\tFRF_AB_DEBUG_BLK_SEL2_WIDTH 3\n+#define\tFRF_AB_DEBUG_BLK_SEL1_LBN 44\n+#define\tFRF_AB_DEBUG_BLK_SEL1_WIDTH 3\n+#define\tFRF_AB_DEBUG_BLK_SEL0_LBN 41\n+#define\tFRF_AB_DEBUG_BLK_SEL0_WIDTH 3\n+#define\tFRF_CZ_CS_PORT_NUM_LBN 40\n+#define\tFRF_CZ_CS_PORT_NUM_WIDTH 2\n+#define\tFRF_AB_MISC_DEBUG_ADDR_LBN 36\n+#define\tFRF_AB_MISC_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_CZ_CS_RESERVED_LBN 36\n+#define\tFRF_CZ_CS_RESERVED_WIDTH 4\n+#define\tFRF_AB_SERDES_DEBUG_ADDR_LBN 31\n+#define\tFRF_AB_SERDES_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_CZ_CS_PORT_FPE_DW0_LBN 1\n+#define\tFRF_CZ_CS_PORT_FPE_DW0_WIDTH 32\n+#define\tFRF_CZ_CS_PORT_FPE_DW1_LBN 33\n+#define\tFRF_CZ_CS_PORT_FPE_DW1_WIDTH 3\n+#define\tFRF_CZ_CS_PORT_FPE_LBN 1\n+#define\tFRF_CZ_CS_PORT_FPE_WIDTH 35\n+#define\tFRF_AB_EM_DEBUG_ADDR_LBN 26\n+#define\tFRF_AB_EM_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_AB_SR_DEBUG_ADDR_LBN 21\n+#define\tFRF_AB_SR_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_AB_EV_DEBUG_ADDR_LBN 16\n+#define\tFRF_AB_EV_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_AB_RX_DEBUG_ADDR_LBN 11\n+#define\tFRF_AB_RX_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_AB_TX_DEBUG_ADDR_LBN 6\n+#define\tFRF_AB_TX_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_AB_CS_BIU_DEBUG_ADDR_LBN 1\n+#define\tFRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5\n+#define\tFRF_AZ_CS_DEBUG_EN_LBN 0\n+#define\tFRF_AZ_CS_DEBUG_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_DRIVER_REG(128bit):\n+ * Driver scratch register [0-7]\n+ */\n+#define\tFR_AZ_DRIVER_REG_OFST 0x00000280\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_DRIVER_REG_STEP 16\n+#define\tFR_AZ_DRIVER_REG_ROWS 8\n+\n+#define\tFRF_AZ_DRIVER_DW0_LBN 0\n+#define\tFRF_AZ_DRIVER_DW0_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_ALTERA_BUILD_REG(128bit):\n+ * Altera build register\n+ */\n+#define\tFR_AZ_ALTERA_BUILD_REG_OFST 0x00000300\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_ALTERA_BUILD_VER_LBN 0\n+#define\tFRF_AZ_ALTERA_BUILD_VER_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_CSR_SPARE_REG(128bit):\n+ * Spare register\n+ */\n+#define\tFR_AZ_CSR_SPARE_REG_OFST 0x00000310\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72\n+#define\tFRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2\n+#define\tFRF_AZ_MEM_PERR_EN_LBN 64\n+#define\tFRF_AZ_MEM_PERR_EN_WIDTH 38\n+#define\tFRF_AZ_MEM_PERR_EN_DW0_LBN 64\n+#define\tFRF_AZ_MEM_PERR_EN_DW0_WIDTH 32\n+#define\tFRF_AZ_MEM_PERR_EN_DW1_LBN 96\n+#define\tFRF_AZ_MEM_PERR_EN_DW1_WIDTH 6\n+#define\tFRF_AZ_CSR_SPARE_BITS_LBN 0\n+#define\tFRF_AZ_CSR_SPARE_BITS_WIDTH 32\n+\n+\n+/*\n+ * FR_BZ_DEBUG_DATA_OUT_REG(128bit):\n+ * Live Debug and Debug 2 out ports\n+ */\n+#define\tFR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350\n+/* falconb0,sienaa0=net_func_bar2 */\n+\n+#define\tFRF_BZ_DEBUG2_PORT_LBN 25\n+#define\tFRF_BZ_DEBUG2_PORT_WIDTH 15\n+#define\tFRF_BZ_DEBUG1_PORT_LBN 0\n+#define\tFRF_BZ_DEBUG1_PORT_WIDTH 25\n+\n+\n+/*\n+ * FR_BZ_EVQ_RPTR_REGP0(32bit):\n+ * Event queue read pointer register\n+ */\n+#define\tFR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400\n+/* falconb0,sienaa0=net_func_bar2 */\n+#define\tFR_BZ_EVQ_RPTR_REGP0_STEP 8192\n+#define\tFR_BZ_EVQ_RPTR_REGP0_ROWS 1024\n+/*\n+ * FR_AA_EVQ_RPTR_REG_KER(32bit):\n+ * Event queue read pointer register\n+ */\n+#define\tFR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_EVQ_RPTR_REG_KER_STEP 4\n+#define\tFR_AA_EVQ_RPTR_REG_KER_ROWS 4\n+/*\n+ * FR_AZ_EVQ_RPTR_REG(32bit):\n+ * Event queue read pointer register\n+ */\n+#define\tFR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000\n+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_EVQ_RPTR_REG_STEP 16\n+#define\tFR_AB_EVQ_RPTR_REG_ROWS 4096\n+#define\tFR_CZ_EVQ_RPTR_REG_ROWS 1024\n+/*\n+ * FR_BB_EVQ_RPTR_REGP123(32bit):\n+ * Event queue read pointer register\n+ */\n+#define\tFR_BB_EVQ_RPTR_REGP123_OFST 0x01000400\n+/* falconb0=net_func_bar2 */\n+#define\tFR_BB_EVQ_RPTR_REGP123_STEP 8192\n+#define\tFR_BB_EVQ_RPTR_REGP123_ROWS 3072\n+\n+#define\tFRF_AZ_EVQ_RPTR_VLD_LBN 15\n+#define\tFRF_AZ_EVQ_RPTR_VLD_WIDTH 1\n+#define\tFRF_AZ_EVQ_RPTR_LBN 0\n+#define\tFRF_AZ_EVQ_RPTR_WIDTH 15\n+\n+\n+/*\n+ * FR_BZ_TIMER_COMMAND_REGP0(128bit):\n+ * Timer Command Registers\n+ */\n+#define\tFR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420\n+/* falconb0,sienaa0=net_func_bar2 */\n+#define\tFR_BZ_TIMER_COMMAND_REGP0_STEP 8192\n+#define\tFR_BZ_TIMER_COMMAND_REGP0_ROWS 1024\n+/*\n+ * FR_AA_TIMER_COMMAND_REG_KER(128bit):\n+ * Timer Command Registers\n+ */\n+#define\tFR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_TIMER_COMMAND_REG_KER_STEP 8192\n+#define\tFR_AA_TIMER_COMMAND_REG_KER_ROWS 4\n+/*\n+ * FR_AB_TIMER_COMMAND_REGP123(128bit):\n+ * Timer Command Registers\n+ */\n+#define\tFR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420\n+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AB_TIMER_COMMAND_REGP123_STEP 8192\n+#define\tFR_AB_TIMER_COMMAND_REGP123_ROWS 3072\n+/*\n+ * FR_AA_TIMER_COMMAND_REGP0(128bit):\n+ * Timer Command Registers\n+ */\n+#define\tFR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420\n+/* falcona0=char_func_bar0 */\n+#define\tFR_AA_TIMER_COMMAND_REGP0_STEP 8192\n+#define\tFR_AA_TIMER_COMMAND_REGP0_ROWS 1020\n+\n+#define\tFRF_CZ_TC_TIMER_MODE_LBN 14\n+#define\tFRF_CZ_TC_TIMER_MODE_WIDTH 2\n+#define\tFRF_AB_TC_TIMER_MODE_LBN 12\n+#define\tFRF_AB_TC_TIMER_MODE_WIDTH 2\n+#define\tFRF_CZ_TC_TIMER_VAL_LBN 0\n+#define\tFRF_CZ_TC_TIMER_VAL_WIDTH 14\n+#define\tFRF_AB_TC_TIMER_VAL_LBN 0\n+#define\tFRF_AB_TC_TIMER_VAL_WIDTH 12\n+\n+\n+/*\n+ * FR_AZ_DRV_EV_REG(128bit):\n+ * Driver generated event register\n+ */\n+#define\tFR_AZ_DRV_EV_REG_OFST 0x00000440\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_DRV_EV_QID_LBN 64\n+#define\tFRF_AZ_DRV_EV_QID_WIDTH 12\n+#define\tFRF_AZ_DRV_EV_DATA_LBN 0\n+#define\tFRF_AZ_DRV_EV_DATA_WIDTH 64\n+#define\tFRF_AZ_DRV_EV_DATA_DW0_LBN 0\n+#define\tFRF_AZ_DRV_EV_DATA_DW0_WIDTH 32\n+#define\tFRF_AZ_DRV_EV_DATA_DW1_LBN 32\n+#define\tFRF_AZ_DRV_EV_DATA_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_EVQ_CTL_REG(128bit):\n+ * Event queue control register\n+ */\n+#define\tFR_AZ_EVQ_CTL_REG_OFST 0x00000450\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15\n+#define\tFRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10\n+#define\tFRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15\n+#define\tFRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6\n+#define\tFRF_AZ_EVQ_OWNERR_CTL_LBN 14\n+#define\tFRF_AZ_EVQ_OWNERR_CTL_WIDTH 1\n+#define\tFRF_AZ_EVQ_FIFO_AF_TH_LBN 7\n+#define\tFRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7\n+#define\tFRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0\n+#define\tFRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7\n+\n+\n+/*\n+ * FR_AZ_EVQ_CNT1_REG(128bit):\n+ * Event counter 1 register\n+ */\n+#define\tFR_AZ_EVQ_CNT1_REG_OFST 0x00000460\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120\n+#define\tFRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7\n+#define\tFRF_AZ_EVQ_CNT_TOBIU_LBN 100\n+#define\tFRF_AZ_EVQ_CNT_TOBIU_WIDTH 20\n+#define\tFRF_AZ_EVQ_TX_REQ_CNT_LBN 80\n+#define\tFRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_RX_REQ_CNT_LBN 60\n+#define\tFRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_EM_REQ_CNT_LBN 40\n+#define\tFRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_CSR_REQ_CNT_LBN 20\n+#define\tFRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_ERR_REQ_CNT_LBN 0\n+#define\tFRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20\n+\n+\n+/*\n+ * FR_AZ_EVQ_CNT2_REG(128bit):\n+ * Event counter 2 register\n+ */\n+#define\tFR_AZ_EVQ_CNT2_REG_OFST 0x00000470\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_EVQ_UPD_REQ_CNT_LBN 104\n+#define\tFRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_CLR_REQ_CNT_LBN 84\n+#define\tFRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_RDY_CNT_LBN 80\n+#define\tFRF_AZ_EVQ_RDY_CNT_WIDTH 4\n+#define\tFRF_AZ_EVQ_WU_REQ_CNT_LBN 60\n+#define\tFRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_WET_REQ_CNT_LBN 40\n+#define\tFRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_INIT_REQ_CNT_LBN 20\n+#define\tFRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20\n+#define\tFRF_AZ_EVQ_TM_REQ_CNT_LBN 0\n+#define\tFRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20\n+\n+\n+/*\n+ * FR_CZ_USR_EV_REG(32bit):\n+ * Event mailbox register\n+ */\n+#define\tFR_CZ_USR_EV_REG_OFST 0x00000540\n+/* sienaa0=net_func_bar2 */\n+#define\tFR_CZ_USR_EV_REG_STEP 8192\n+#define\tFR_CZ_USR_EV_REG_ROWS 1024\n+\n+#define\tFRF_CZ_USR_EV_DATA_LBN 0\n+#define\tFRF_CZ_USR_EV_DATA_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_BUF_TBL_CFG_REG(128bit):\n+ * Buffer table configuration register\n+ */\n+#define\tFR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_BUF_TBL_MODE_LBN 3\n+#define\tFRF_AZ_BUF_TBL_MODE_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_SRM_RX_DC_CFG_REG(128bit):\n+ * SRAM receive descriptor cache configuration register\n+ */\n+#define\tFR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_SRM_CLK_TMP_EN_LBN 21\n+#define\tFRF_AZ_SRM_CLK_TMP_EN_WIDTH 1\n+#define\tFRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0\n+#define\tFRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21\n+\n+\n+/*\n+ * FR_AZ_SRM_TX_DC_CFG_REG(128bit):\n+ * SRAM transmit descriptor cache configuration register\n+ */\n+#define\tFR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0\n+#define\tFRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21\n+\n+\n+/*\n+ * FR_AZ_SRM_CFG_REG(128bit):\n+ * SRAM configuration register\n+ */\n+#define\tFR_AZ_SRM_CFG_REG_SF_OFST 0x00000380\n+/* falcona0,falconb0=eeprom_flash */\n+/*\n+ * FR_AZ_SRM_CFG_REG(128bit):\n+ * SRAM configuration register\n+ */\n+#define\tFR_AZ_SRM_CFG_REG_OFST 0x00000630\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_SRM_OOB_ADR_INTEN_LBN 5\n+#define\tFRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1\n+#define\tFRF_AZ_SRM_OOB_BUF_INTEN_LBN 4\n+#define\tFRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1\n+#define\tFRF_AZ_SRM_INIT_EN_LBN 3\n+#define\tFRF_AZ_SRM_INIT_EN_WIDTH 1\n+#define\tFRF_AZ_SRM_NUM_BANK_LBN 2\n+#define\tFRF_AZ_SRM_NUM_BANK_WIDTH 1\n+#define\tFRF_AZ_SRM_BANK_SIZE_LBN 0\n+#define\tFRF_AZ_SRM_BANK_SIZE_WIDTH 2\n+\n+\n+/*\n+ * FR_AZ_BUF_TBL_UPD_REG(128bit):\n+ * Buffer table update register\n+ */\n+#define\tFR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_BUF_UPD_CMD_LBN 63\n+#define\tFRF_AZ_BUF_UPD_CMD_WIDTH 1\n+#define\tFRF_AZ_BUF_CLR_CMD_LBN 62\n+#define\tFRF_AZ_BUF_CLR_CMD_WIDTH 1\n+#define\tFRF_AZ_BUF_CLR_END_ID_LBN 32\n+#define\tFRF_AZ_BUF_CLR_END_ID_WIDTH 20\n+#define\tFRF_AZ_BUF_CLR_START_ID_LBN 0\n+#define\tFRF_AZ_BUF_CLR_START_ID_WIDTH 20\n+\n+\n+/*\n+ * FR_AZ_SRM_UPD_EVQ_REG(128bit):\n+ * Buffer table update register\n+ */\n+#define\tFR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_SRM_UPD_EVQ_ID_LBN 0\n+#define\tFRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12\n+\n+\n+/*\n+ * FR_AZ_SRAM_PARITY_REG(128bit):\n+ * SRAM parity register.\n+ */\n+#define\tFR_AZ_SRAM_PARITY_REG_OFST 0x00000670\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_CZ_BYPASS_ECC_LBN 3\n+#define\tFRF_CZ_BYPASS_ECC_WIDTH 1\n+#define\tFRF_CZ_SEC_INT_LBN 2\n+#define\tFRF_CZ_SEC_INT_WIDTH 1\n+#define\tFRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1\n+#define\tFRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1\n+#define\tFRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0\n+#define\tFRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1\n+#define\tFRF_AB_FORCE_SRAM_PERR_LBN 0\n+#define\tFRF_AB_FORCE_SRAM_PERR_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_RX_CFG_REG(128bit):\n+ * Receive configuration register\n+ */\n+#define\tFR_AZ_RX_CFG_REG_OFST 0x00000800\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_CZ_RX_HDR_SPLIT_EN_LBN 71\n+#define\tFRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1\n+#define\tFRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62\n+#define\tFRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9\n+#define\tFRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53\n+#define\tFRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9\n+#define\tFRF_CZ_RX_PRE_RFF_IPG_LBN 49\n+#define\tFRF_CZ_RX_PRE_RFF_IPG_WIDTH 4\n+#define\tFRF_BZ_RX_TCP_SUP_LBN 48\n+#define\tFRF_BZ_RX_TCP_SUP_WIDTH 1\n+#define\tFRF_BZ_RX_INGR_EN_LBN 47\n+#define\tFRF_BZ_RX_INGR_EN_WIDTH 1\n+#define\tFRF_BZ_RX_IP_HASH_LBN 46\n+#define\tFRF_BZ_RX_IP_HASH_WIDTH 1\n+#define\tFRF_BZ_RX_HASH_ALG_LBN 45\n+#define\tFRF_BZ_RX_HASH_ALG_WIDTH 1\n+#define\tFRF_BZ_RX_HASH_INSRT_HDR_LBN 44\n+#define\tFRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1\n+#define\tFRF_BZ_RX_DESC_PUSH_EN_LBN 43\n+#define\tFRF_BZ_RX_DESC_PUSH_EN_WIDTH 1\n+#define\tFRF_BZ_RX_RDW_PATCH_EN_LBN 42\n+#define\tFRF_BZ_RX_RDW_PATCH_EN_WIDTH 1\n+#define\tFRF_BB_RX_PCI_BURST_SIZE_LBN 39\n+#define\tFRF_BB_RX_PCI_BURST_SIZE_WIDTH 3\n+#define\tFRF_BZ_RX_OWNERR_CTL_LBN 38\n+#define\tFRF_BZ_RX_OWNERR_CTL_WIDTH 1\n+#define\tFRF_BZ_RX_XON_TX_TH_LBN 33\n+#define\tFRF_BZ_RX_XON_TX_TH_WIDTH 5\n+#define\tFRF_AA_RX_DESC_PUSH_EN_LBN 35\n+#define\tFRF_AA_RX_DESC_PUSH_EN_WIDTH 1\n+#define\tFRF_AA_RX_RDW_PATCH_EN_LBN 34\n+#define\tFRF_AA_RX_RDW_PATCH_EN_WIDTH 1\n+#define\tFRF_AA_RX_PCI_BURST_SIZE_LBN 31\n+#define\tFRF_AA_RX_PCI_BURST_SIZE_WIDTH 3\n+#define\tFRF_BZ_RX_XOFF_TX_TH_LBN 28\n+#define\tFRF_BZ_RX_XOFF_TX_TH_WIDTH 5\n+#define\tFRF_AA_RX_OWNERR_CTL_LBN 30\n+#define\tFRF_AA_RX_OWNERR_CTL_WIDTH 1\n+#define\tFRF_AA_RX_XON_TX_TH_LBN 25\n+#define\tFRF_AA_RX_XON_TX_TH_WIDTH 5\n+#define\tFRF_BZ_RX_USR_BUF_SIZE_LBN 19\n+#define\tFRF_BZ_RX_USR_BUF_SIZE_WIDTH 9\n+#define\tFRF_AA_RX_XOFF_TX_TH_LBN 20\n+#define\tFRF_AA_RX_XOFF_TX_TH_WIDTH 5\n+#define\tFRF_AA_RX_USR_BUF_SIZE_LBN 11\n+#define\tFRF_AA_RX_USR_BUF_SIZE_WIDTH 9\n+#define\tFRF_BZ_RX_XON_MAC_TH_LBN 10\n+#define\tFRF_BZ_RX_XON_MAC_TH_WIDTH 9\n+#define\tFRF_AA_RX_XON_MAC_TH_LBN 6\n+#define\tFRF_AA_RX_XON_MAC_TH_WIDTH 5\n+#define\tFRF_BZ_RX_XOFF_MAC_TH_LBN 1\n+#define\tFRF_BZ_RX_XOFF_MAC_TH_WIDTH 9\n+#define\tFRF_AA_RX_XOFF_MAC_TH_LBN 1\n+#define\tFRF_AA_RX_XOFF_MAC_TH_WIDTH 5\n+#define\tFRF_AZ_RX_XOFF_MAC_EN_LBN 0\n+#define\tFRF_AZ_RX_XOFF_MAC_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_RX_FILTER_CTL_REG(128bit):\n+ * Receive filter control registers\n+ */\n+#define\tFR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94\n+#define\tFRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8\n+#define\tFRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86\n+#define\tFRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8\n+#define\tFRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85\n+#define\tFRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1\n+#define\tFRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69\n+#define\tFRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16\n+#define\tFRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57\n+#define\tFRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12\n+#define\tFRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56\n+#define\tFRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1\n+#define\tFRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55\n+#define\tFRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1\n+#define\tFRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43\n+#define\tFRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12\n+#define\tFRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42\n+#define\tFRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1\n+#define\tFRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41\n+#define\tFRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1\n+#define\tFRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40\n+#define\tFRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1\n+#define\tFRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32\n+#define\tFRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8\n+#define\tFRF_AZ_NUM_KER_LBN 24\n+#define\tFRF_AZ_NUM_KER_WIDTH 2\n+#define\tFRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16\n+#define\tFRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8\n+#define\tFRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8\n+#define\tFRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8\n+#define\tFRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0\n+#define\tFRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8\n+\n+\n+/*\n+ * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):\n+ * Receive flush descriptor queue register\n+ */\n+#define\tFR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24\n+#define\tFRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1\n+#define\tFRF_AZ_RX_FLUSH_DESCQ_LBN 0\n+#define\tFRF_AZ_RX_FLUSH_DESCQ_WIDTH 12\n+\n+\n+/*\n+ * FR_BZ_RX_DESC_UPD_REGP0(128bit):\n+ * Receive descriptor update register.\n+ */\n+#define\tFR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830\n+/* falconb0,sienaa0=net_func_bar2 */\n+#define\tFR_BZ_RX_DESC_UPD_REGP0_STEP 8192\n+#define\tFR_BZ_RX_DESC_UPD_REGP0_ROWS 1024\n+/*\n+ * FR_AA_RX_DESC_UPD_REG_KER(128bit):\n+ * Receive descriptor update register.\n+ */\n+#define\tFR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_RX_DESC_UPD_REG_KER_STEP 8192\n+#define\tFR_AA_RX_DESC_UPD_REG_KER_ROWS 4\n+/*\n+ * FR_AB_RX_DESC_UPD_REGP123(128bit):\n+ * Receive descriptor update register.\n+ */\n+#define\tFR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830\n+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AB_RX_DESC_UPD_REGP123_STEP 8192\n+#define\tFR_AB_RX_DESC_UPD_REGP123_ROWS 3072\n+/*\n+ * FR_AA_RX_DESC_UPD_REGP0(128bit):\n+ * Receive descriptor update register.\n+ */\n+#define\tFR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830\n+/* falcona0=char_func_bar0 */\n+#define\tFR_AA_RX_DESC_UPD_REGP0_STEP 8192\n+#define\tFR_AA_RX_DESC_UPD_REGP0_ROWS 1020\n+\n+#define\tFRF_AZ_RX_DESC_WPTR_LBN 96\n+#define\tFRF_AZ_RX_DESC_WPTR_WIDTH 12\n+#define\tFRF_AZ_RX_DESC_PUSH_CMD_LBN 95\n+#define\tFRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1\n+#define\tFRF_AZ_RX_DESC_LBN 0\n+#define\tFRF_AZ_RX_DESC_WIDTH 64\n+#define\tFRF_AZ_RX_DESC_DW0_LBN 0\n+#define\tFRF_AZ_RX_DESC_DW0_WIDTH 32\n+#define\tFRF_AZ_RX_DESC_DW1_LBN 32\n+#define\tFRF_AZ_RX_DESC_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_RX_DC_CFG_REG(128bit):\n+ * Receive descriptor cache configuration register\n+ */\n+#define\tFR_AZ_RX_DC_CFG_REG_OFST 0x00000840\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_RX_MAX_PF_LBN 2\n+#define\tFRF_AZ_RX_MAX_PF_WIDTH 2\n+#define\tFRF_AZ_RX_DC_SIZE_LBN 0\n+#define\tFRF_AZ_RX_DC_SIZE_WIDTH 2\n+#define\tFFE_AZ_RX_DC_SIZE_64 3\n+#define\tFFE_AZ_RX_DC_SIZE_32 2\n+#define\tFFE_AZ_RX_DC_SIZE_16 1\n+#define\tFFE_AZ_RX_DC_SIZE_8 0\n+\n+\n+/*\n+ * FR_AZ_RX_DC_PF_WM_REG(128bit):\n+ * Receive descriptor cache pre-fetch watermark register\n+ */\n+#define\tFR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_RX_DC_PF_HWM_LBN 6\n+#define\tFRF_AZ_RX_DC_PF_HWM_WIDTH 6\n+#define\tFRF_AZ_RX_DC_PF_LWM_LBN 0\n+#define\tFRF_AZ_RX_DC_PF_LWM_WIDTH 6\n+\n+\n+/*\n+ * FR_BZ_RX_RSS_TKEY_REG(128bit):\n+ * RSS Toeplitz hash key\n+ */\n+#define\tFR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860\n+/* falconb0,sienaa0=net_func_bar2 */\n+\n+#define\tFRF_BZ_RX_RSS_TKEY_LBN 96\n+#define\tFRF_BZ_RX_RSS_TKEY_WIDTH 32\n+#define\tFRF_BZ_RX_RSS_TKEY_DW3_LBN 96\n+#define\tFRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32\n+#define\tFRF_BZ_RX_RSS_TKEY_DW2_LBN 64\n+#define\tFRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32\n+#define\tFRF_BZ_RX_RSS_TKEY_DW1_LBN 32\n+#define\tFRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32\n+#define\tFRF_BZ_RX_RSS_TKEY_DW0_LBN 0\n+#define\tFRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_RX_NODESC_DROP_REG(128bit):\n+ * Receive dropped packet counter register\n+ */\n+#define\tFR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_RX_NODESC_DROP_CNT_LBN 0\n+#define\tFRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16\n+\n+\n+/*\n+ * FR_AZ_RX_SELF_RST_REG(128bit):\n+ * Receive self reset register\n+ */\n+#define\tFR_AZ_RX_SELF_RST_REG_OFST 0x00000890\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_RX_ISCSI_DIS_LBN 17\n+#define\tFRF_AZ_RX_ISCSI_DIS_WIDTH 1\n+#define\tFRF_AB_RX_SW_RST_REG_LBN 16\n+#define\tFRF_AB_RX_SW_RST_REG_WIDTH 1\n+#define\tFRF_AB_RX_SELF_RST_EN_LBN 8\n+#define\tFRF_AB_RX_SELF_RST_EN_WIDTH 1\n+#define\tFRF_AZ_RX_MAX_PF_LAT_LBN 4\n+#define\tFRF_AZ_RX_MAX_PF_LAT_WIDTH 4\n+#define\tFRF_AZ_RX_MAX_LU_LAT_LBN 0\n+#define\tFRF_AZ_RX_MAX_LU_LAT_WIDTH 4\n+\n+\n+/*\n+ * FR_AZ_RX_DEBUG_REG(128bit):\n+ * undocumented register\n+ */\n+#define\tFR_AZ_RX_DEBUG_REG_OFST 0x000008a0\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_RX_DEBUG_LBN 0\n+#define\tFRF_AZ_RX_DEBUG_WIDTH 64\n+#define\tFRF_AZ_RX_DEBUG_DW0_LBN 0\n+#define\tFRF_AZ_RX_DEBUG_DW0_WIDTH 32\n+#define\tFRF_AZ_RX_DEBUG_DW1_LBN 32\n+#define\tFRF_AZ_RX_DEBUG_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_RX_PUSH_DROP_REG(128bit):\n+ * Receive descriptor push dropped counter register\n+ */\n+#define\tFR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_RX_PUSH_DROP_CNT_LBN 0\n+#define\tFRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32\n+\n+\n+/*\n+ * FR_CZ_RX_RSS_IPV6_REG1(128bit):\n+ * IPv6 RSS Toeplitz hash key low bytes\n+ */\n+#define\tFR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0\n+/* sienaa0=net_func_bar2 */\n+\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32\n+\n+\n+/*\n+ * FR_CZ_RX_RSS_IPV6_REG2(128bit):\n+ * IPv6 RSS Toeplitz hash key middle bytes\n+ */\n+#define\tFR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0\n+/* sienaa0=net_func_bar2 */\n+\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32\n+\n+\n+/*\n+ * FR_CZ_RX_RSS_IPV6_REG3(128bit):\n+ * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings\n+ */\n+#define\tFR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0\n+/* sienaa0=net_func_bar2 */\n+\n+#define\tFRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66\n+#define\tFRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1\n+#define\tFRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65\n+#define\tFRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1\n+#define\tFRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64\n+#define\tFRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32\n+#define\tFRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):\n+ * Transmit flush descriptor queue register\n+ */\n+#define\tFR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12\n+#define\tFRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1\n+#define\tFRF_AZ_TX_FLUSH_DESCQ_LBN 0\n+#define\tFRF_AZ_TX_FLUSH_DESCQ_WIDTH 12\n+\n+\n+/*\n+ * FR_BZ_TX_DESC_UPD_REGP0(128bit):\n+ * Transmit descriptor update register.\n+ */\n+#define\tFR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10\n+/* falconb0,sienaa0=net_func_bar2 */\n+#define\tFR_BZ_TX_DESC_UPD_REGP0_STEP 8192\n+#define\tFR_BZ_TX_DESC_UPD_REGP0_ROWS 1024\n+/*\n+ * FR_AA_TX_DESC_UPD_REG_KER(128bit):\n+ * Transmit descriptor update register.\n+ */\n+#define\tFR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_TX_DESC_UPD_REG_KER_STEP 8192\n+#define\tFR_AA_TX_DESC_UPD_REG_KER_ROWS 8\n+/*\n+ * FR_AB_TX_DESC_UPD_REGP123(128bit):\n+ * Transmit descriptor update register.\n+ */\n+#define\tFR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10\n+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AB_TX_DESC_UPD_REGP123_STEP 8192\n+#define\tFR_AB_TX_DESC_UPD_REGP123_ROWS 3072\n+/*\n+ * FR_AA_TX_DESC_UPD_REGP0(128bit):\n+ * Transmit descriptor update register.\n+ */\n+#define\tFR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10\n+/* falcona0=char_func_bar0 */\n+#define\tFR_AA_TX_DESC_UPD_REGP0_STEP 8192\n+#define\tFR_AA_TX_DESC_UPD_REGP0_ROWS 1020\n+\n+#define\tFRF_AZ_TX_DESC_WPTR_LBN 96\n+#define\tFRF_AZ_TX_DESC_WPTR_WIDTH 12\n+#define\tFRF_AZ_TX_DESC_PUSH_CMD_LBN 95\n+#define\tFRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1\n+#define\tFRF_AZ_TX_DESC_LBN 0\n+#define\tFRF_AZ_TX_DESC_WIDTH 95\n+#define\tFRF_AZ_TX_DESC_DW0_LBN 0\n+#define\tFRF_AZ_TX_DESC_DW0_WIDTH 32\n+#define\tFRF_AZ_TX_DESC_DW1_LBN 32\n+#define\tFRF_AZ_TX_DESC_DW1_WIDTH 32\n+#define\tFRF_AZ_TX_DESC_DW2_LBN 64\n+#define\tFRF_AZ_TX_DESC_DW2_WIDTH 31\n+\n+\n+/*\n+ * FR_AZ_TX_DC_CFG_REG(128bit):\n+ * Transmit descriptor cache configuration register\n+ */\n+#define\tFR_AZ_TX_DC_CFG_REG_OFST 0x00000a20\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_TX_DC_SIZE_LBN 0\n+#define\tFRF_AZ_TX_DC_SIZE_WIDTH 2\n+#define\tFFE_AZ_TX_DC_SIZE_32 2\n+#define\tFFE_AZ_TX_DC_SIZE_16 1\n+#define\tFFE_AZ_TX_DC_SIZE_8 0\n+\n+\n+/*\n+ * FR_AA_TX_CHKSM_CFG_REG(128bit):\n+ * Transmit checksum configuration register\n+ */\n+#define\tFR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30\n+/* falcona0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0\n+#define\tFRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_TX_CFG_REG(128bit):\n+ * Transmit configuration register\n+ */\n+#define\tFR_AZ_TX_CFG_REG_OFST 0x00000a50\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114\n+#define\tFRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8\n+#define\tFRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113\n+#define\tFRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1\n+#define\tFRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105\n+#define\tFRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8\n+#define\tFRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97\n+#define\tFRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8\n+#define\tFRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89\n+#define\tFRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8\n+#define\tFRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81\n+#define\tFRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8\n+#define\tFRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73\n+#define\tFRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8\n+#define\tFRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65\n+#define\tFRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8\n+#define\tFRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64\n+#define\tFRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1\n+#define\tFRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48\n+#define\tFRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16\n+#define\tFRF_CZ_TX_FILTER_EN_BIT_LBN 47\n+#define\tFRF_CZ_TX_FILTER_EN_BIT_WIDTH 1\n+#define\tFRF_AZ_TX_IP_ID_P0_OFS_LBN 16\n+#define\tFRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15\n+#define\tFRF_AZ_TX_NO_EOP_DISC_EN_LBN 5\n+#define\tFRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1\n+#define\tFRF_AZ_TX_P1_PRI_EN_LBN 4\n+#define\tFRF_AZ_TX_P1_PRI_EN_WIDTH 1\n+#define\tFRF_AZ_TX_OWNERR_CTL_LBN 2\n+#define\tFRF_AZ_TX_OWNERR_CTL_WIDTH 1\n+#define\tFRF_AA_TX_NON_IP_DROP_DIS_LBN 1\n+#define\tFRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1\n+#define\tFRF_AZ_TX_IP_ID_REP_EN_LBN 0\n+#define\tFRF_AZ_TX_IP_ID_REP_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AZ_TX_PUSH_DROP_REG(128bit):\n+ * Transmit push dropped register\n+ */\n+#define\tFR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_TX_PUSH_DROP_CNT_LBN 0\n+#define\tFRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_TX_RESERVED_REG(128bit):\n+ * Transmit configuration register\n+ */\n+#define\tFR_AZ_TX_RESERVED_REG_OFST 0x00000a80\n+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_TX_EVT_CNT_LBN 121\n+#define\tFRF_AZ_TX_EVT_CNT_WIDTH 7\n+#define\tFRF_AZ_TX_PREF_AGE_CNT_LBN 119\n+#define\tFRF_AZ_TX_PREF_AGE_CNT_WIDTH 2\n+#define\tFRF_AZ_TX_RD_COMP_TMR_LBN 96\n+#define\tFRF_AZ_TX_RD_COMP_TMR_WIDTH 23\n+#define\tFRF_AZ_TX_PUSH_EN_LBN 89\n+#define\tFRF_AZ_TX_PUSH_EN_WIDTH 1\n+#define\tFRF_AZ_TX_PUSH_CHK_DIS_LBN 88\n+#define\tFRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1\n+#define\tFRF_AZ_TX_D_FF_FULL_P0_LBN 85\n+#define\tFRF_AZ_TX_D_FF_FULL_P0_WIDTH 1\n+#define\tFRF_AZ_TX_DMAR_ST_P0_LBN 81\n+#define\tFRF_AZ_TX_DMAR_ST_P0_WIDTH 1\n+#define\tFRF_AZ_TX_DMAQ_ST_LBN 78\n+#define\tFRF_AZ_TX_DMAQ_ST_WIDTH 1\n+#define\tFRF_AZ_TX_RX_SPACER_LBN 64\n+#define\tFRF_AZ_TX_RX_SPACER_WIDTH 8\n+#define\tFRF_AZ_TX_DROP_ABORT_EN_LBN 60\n+#define\tFRF_AZ_TX_DROP_ABORT_EN_WIDTH 1\n+#define\tFRF_AZ_TX_SOFT_EVT_EN_LBN 59\n+#define\tFRF_AZ_TX_SOFT_EVT_EN_WIDTH 1\n+#define\tFRF_AZ_TX_PS_EVT_DIS_LBN 58\n+#define\tFRF_AZ_TX_PS_EVT_DIS_WIDTH 1\n+#define\tFRF_AZ_TX_RX_SPACER_EN_LBN 57\n+#define\tFRF_AZ_TX_RX_SPACER_EN_WIDTH 1\n+#define\tFRF_AZ_TX_XP_TIMER_LBN 52\n+#define\tFRF_AZ_TX_XP_TIMER_WIDTH 5\n+#define\tFRF_AZ_TX_PREF_SPACER_LBN 44\n+#define\tFRF_AZ_TX_PREF_SPACER_WIDTH 8\n+#define\tFRF_AZ_TX_PREF_WD_TMR_LBN 22\n+#define\tFRF_AZ_TX_PREF_WD_TMR_WIDTH 22\n+#define\tFRF_AZ_TX_ONLY1TAG_LBN 21\n+#define\tFRF_AZ_TX_ONLY1TAG_WIDTH 1\n+#define\tFRF_AZ_TX_PREF_THRESHOLD_LBN 19\n+#define\tFRF_AZ_TX_PREF_THRESHOLD_WIDTH 2\n+#define\tFRF_AZ_TX_ONE_PKT_PER_Q_LBN 18\n+#define\tFRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1\n+#define\tFRF_AZ_TX_DIS_NON_IP_EV_LBN 17\n+#define\tFRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1\n+#define\tFRF_AA_TX_DMA_FF_THR_LBN 16\n+#define\tFRF_AA_TX_DMA_FF_THR_WIDTH 1\n+#define\tFRF_AZ_TX_DMA_SPACER_LBN 8\n+#define\tFRF_AZ_TX_DMA_SPACER_WIDTH 8\n+#define\tFRF_AA_TX_TCP_DIS_LBN 7\n+#define\tFRF_AA_TX_TCP_DIS_WIDTH 1\n+#define\tFRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7\n+#define\tFRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1\n+#define\tFRF_AA_TX_IP_DIS_LBN 6\n+#define\tFRF_AA_TX_IP_DIS_WIDTH 1\n+#define\tFRF_AZ_TX_MAX_CPL_LBN 2\n+#define\tFRF_AZ_TX_MAX_CPL_WIDTH 2\n+#define\tFFE_AZ_TX_MAX_CPL_16 3\n+#define\tFFE_AZ_TX_MAX_CPL_8 2\n+#define\tFFE_AZ_TX_MAX_CPL_4 1\n+#define\tFFE_AZ_TX_MAX_CPL_NOLIMIT 0\n+#define\tFRF_AZ_TX_MAX_PREF_LBN 0\n+#define\tFRF_AZ_TX_MAX_PREF_WIDTH 2\n+#define\tFFE_AZ_TX_MAX_PREF_32 3\n+#define\tFFE_AZ_TX_MAX_PREF_16 2\n+#define\tFFE_AZ_TX_MAX_PREF_8 1\n+#define\tFFE_AZ_TX_MAX_PREF_OFF 0\n+\n+\n+/*\n+ * FR_BZ_TX_PACE_REG(128bit):\n+ * Transmit pace control register\n+ */\n+#define\tFR_BZ_TX_PACE_REG_OFST 0x00000a90\n+/* falconb0,sienaa0=net_func_bar2 */\n+/*\n+ * FR_AA_TX_PACE_REG(128bit):\n+ * Transmit pace control register\n+ */\n+#define\tFR_AA_TX_PACE_REG_OFST 0x00f80000\n+/* falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_TX_PACE_SB_NOT_AF_LBN 19\n+#define\tFRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10\n+#define\tFRF_AZ_TX_PACE_SB_AF_LBN 9\n+#define\tFRF_AZ_TX_PACE_SB_AF_WIDTH 10\n+#define\tFRF_AZ_TX_PACE_FB_BASE_LBN 5\n+#define\tFRF_AZ_TX_PACE_FB_BASE_WIDTH 4\n+#define\tFRF_AZ_TX_PACE_BIN_TH_LBN 0\n+#define\tFRF_AZ_TX_PACE_BIN_TH_WIDTH 5\n+\n+\n+/*\n+ * FR_AZ_TX_PACE_DROP_QID_REG(128bit):\n+ * PACE Drop QID Counter\n+ */\n+#define\tFR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0\n+#define\tFRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_TX_VLAN_REG(128bit):\n+ * Transmit VLAN tag register\n+ */\n+#define\tFR_AB_TX_VLAN_REG_OFST 0x00000ae0\n+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_TX_VLAN_EN_LBN 127\n+#define\tFRF_AB_TX_VLAN_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN7_PORT1_EN_LBN 125\n+#define\tFRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN7_PORT0_EN_LBN 124\n+#define\tFRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN7_LBN 112\n+#define\tFRF_AB_TX_VLAN7_WIDTH 12\n+#define\tFRF_AB_TX_VLAN6_PORT1_EN_LBN 109\n+#define\tFRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN6_PORT0_EN_LBN 108\n+#define\tFRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN6_LBN 96\n+#define\tFRF_AB_TX_VLAN6_WIDTH 12\n+#define\tFRF_AB_TX_VLAN5_PORT1_EN_LBN 93\n+#define\tFRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN5_PORT0_EN_LBN 92\n+#define\tFRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN5_LBN 80\n+#define\tFRF_AB_TX_VLAN5_WIDTH 12\n+#define\tFRF_AB_TX_VLAN4_PORT1_EN_LBN 77\n+#define\tFRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN4_PORT0_EN_LBN 76\n+#define\tFRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN4_LBN 64\n+#define\tFRF_AB_TX_VLAN4_WIDTH 12\n+#define\tFRF_AB_TX_VLAN3_PORT1_EN_LBN 61\n+#define\tFRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN3_PORT0_EN_LBN 60\n+#define\tFRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN3_LBN 48\n+#define\tFRF_AB_TX_VLAN3_WIDTH 12\n+#define\tFRF_AB_TX_VLAN2_PORT1_EN_LBN 45\n+#define\tFRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN2_PORT0_EN_LBN 44\n+#define\tFRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN2_LBN 32\n+#define\tFRF_AB_TX_VLAN2_WIDTH 12\n+#define\tFRF_AB_TX_VLAN1_PORT1_EN_LBN 29\n+#define\tFRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN1_PORT0_EN_LBN 28\n+#define\tFRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN1_LBN 16\n+#define\tFRF_AB_TX_VLAN1_WIDTH 12\n+#define\tFRF_AB_TX_VLAN0_PORT1_EN_LBN 13\n+#define\tFRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN0_PORT0_EN_LBN 12\n+#define\tFRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1\n+#define\tFRF_AB_TX_VLAN0_LBN 0\n+#define\tFRF_AB_TX_VLAN0_WIDTH 12\n+\n+\n+/*\n+ * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):\n+ * Transmit filter control register\n+ */\n+#define\tFR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AZ_TX_MADR0_FIL_EN_LBN 64\n+#define\tFRF_AZ_TX_MADR0_FIL_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL31_PORT_EN_LBN 62\n+#define\tFRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL30_PORT_EN_LBN 60\n+#define\tFRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL29_PORT_EN_LBN 58\n+#define\tFRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL28_PORT_EN_LBN 56\n+#define\tFRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL27_PORT_EN_LBN 54\n+#define\tFRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL26_PORT_EN_LBN 52\n+#define\tFRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL25_PORT_EN_LBN 50\n+#define\tFRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL24_PORT_EN_LBN 48\n+#define\tFRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL23_PORT_EN_LBN 46\n+#define\tFRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL22_PORT_EN_LBN 44\n+#define\tFRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL21_PORT_EN_LBN 42\n+#define\tFRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL20_PORT_EN_LBN 40\n+#define\tFRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL19_PORT_EN_LBN 38\n+#define\tFRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL18_PORT_EN_LBN 36\n+#define\tFRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL17_PORT_EN_LBN 34\n+#define\tFRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL16_PORT_EN_LBN 32\n+#define\tFRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL15_PORT_EN_LBN 30\n+#define\tFRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL14_PORT_EN_LBN 28\n+#define\tFRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL13_PORT_EN_LBN 26\n+#define\tFRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL12_PORT_EN_LBN 24\n+#define\tFRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL11_PORT_EN_LBN 22\n+#define\tFRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL10_PORT_EN_LBN 20\n+#define\tFRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL9_PORT_EN_LBN 18\n+#define\tFRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL8_PORT_EN_LBN 16\n+#define\tFRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL7_PORT_EN_LBN 14\n+#define\tFRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL6_PORT_EN_LBN 12\n+#define\tFRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL5_PORT_EN_LBN 10\n+#define\tFRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL4_PORT_EN_LBN 8\n+#define\tFRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL3_PORT_EN_LBN 6\n+#define\tFRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL2_PORT_EN_LBN 4\n+#define\tFRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL1_PORT_EN_LBN 2\n+#define\tFRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1\n+#define\tFRF_AB_TX_IPFIL0_PORT_EN_LBN 0\n+#define\tFRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_TX_IPFIL_TBL(128bit):\n+ * Transmit IP source address filter table\n+ */\n+#define\tFR_AB_TX_IPFIL_TBL_OFST 0x00000b00\n+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AB_TX_IPFIL_TBL_STEP 16\n+#define\tFR_AB_TX_IPFIL_TBL_ROWS 16\n+\n+#define\tFRF_AB_TX_IPFIL_MASK_1_LBN 96\n+#define\tFRF_AB_TX_IPFIL_MASK_1_WIDTH 32\n+#define\tFRF_AB_TX_IP_SRC_ADR_1_LBN 64\n+#define\tFRF_AB_TX_IP_SRC_ADR_1_WIDTH 32\n+#define\tFRF_AB_TX_IPFIL_MASK_0_LBN 32\n+#define\tFRF_AB_TX_IPFIL_MASK_0_WIDTH 32\n+#define\tFRF_AB_TX_IP_SRC_ADR_0_LBN 0\n+#define\tFRF_AB_TX_IP_SRC_ADR_0_WIDTH 32\n+\n+\n+/*\n+ * FR_AB_MD_TXD_REG(128bit):\n+ * PHY management transmit data register\n+ */\n+#define\tFR_AB_MD_TXD_REG_OFST 0x00000c00\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MD_TXD_LBN 0\n+#define\tFRF_AB_MD_TXD_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_MD_RXD_REG(128bit):\n+ * PHY management receive data register\n+ */\n+#define\tFR_AB_MD_RXD_REG_OFST 0x00000c10\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MD_RXD_LBN 0\n+#define\tFRF_AB_MD_RXD_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_MD_CS_REG(128bit):\n+ * PHY management configuration & status register\n+ */\n+#define\tFR_AB_MD_CS_REG_OFST 0x00000c20\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MD_RD_EN_LBN 15\n+#define\tFRF_AB_MD_RD_EN_WIDTH 1\n+#define\tFRF_AB_MD_WR_EN_LBN 14\n+#define\tFRF_AB_MD_WR_EN_WIDTH 1\n+#define\tFRF_AB_MD_ADDR_CMD_LBN 13\n+#define\tFRF_AB_MD_ADDR_CMD_WIDTH 1\n+#define\tFRF_AB_MD_PT_LBN 7\n+#define\tFRF_AB_MD_PT_WIDTH 3\n+#define\tFRF_AB_MD_PL_LBN 6\n+#define\tFRF_AB_MD_PL_WIDTH 1\n+#define\tFRF_AB_MD_INT_CLR_LBN 5\n+#define\tFRF_AB_MD_INT_CLR_WIDTH 1\n+#define\tFRF_AB_MD_GC_LBN 4\n+#define\tFRF_AB_MD_GC_WIDTH 1\n+#define\tFRF_AB_MD_PRSP_LBN 3\n+#define\tFRF_AB_MD_PRSP_WIDTH 1\n+#define\tFRF_AB_MD_RIC_LBN 2\n+#define\tFRF_AB_MD_RIC_WIDTH 1\n+#define\tFRF_AB_MD_RDC_LBN 1\n+#define\tFRF_AB_MD_RDC_WIDTH 1\n+#define\tFRF_AB_MD_WRC_LBN 0\n+#define\tFRF_AB_MD_WRC_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_MD_PHY_ADR_REG(128bit):\n+ * PHY management PHY address register\n+ */\n+#define\tFR_AB_MD_PHY_ADR_REG_OFST 0x00000c30\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MD_PHY_ADR_LBN 0\n+#define\tFRF_AB_MD_PHY_ADR_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_MD_ID_REG(128bit):\n+ * PHY management ID register\n+ */\n+#define\tFR_AB_MD_ID_REG_OFST 0x00000c40\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MD_PRT_ADR_LBN 11\n+#define\tFRF_AB_MD_PRT_ADR_WIDTH 5\n+#define\tFRF_AB_MD_DEV_ADR_LBN 6\n+#define\tFRF_AB_MD_DEV_ADR_WIDTH 5\n+\n+\n+/*\n+ * FR_AB_MD_STAT_REG(128bit):\n+ * PHY management status & mask register\n+ */\n+#define\tFR_AB_MD_STAT_REG_OFST 0x00000c50\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MD_PINT_LBN 4\n+#define\tFRF_AB_MD_PINT_WIDTH 1\n+#define\tFRF_AB_MD_DONE_LBN 3\n+#define\tFRF_AB_MD_DONE_WIDTH 1\n+#define\tFRF_AB_MD_BSERR_LBN 2\n+#define\tFRF_AB_MD_BSERR_WIDTH 1\n+#define\tFRF_AB_MD_LNFL_LBN 1\n+#define\tFRF_AB_MD_LNFL_WIDTH 1\n+#define\tFRF_AB_MD_BSY_LBN 0\n+#define\tFRF_AB_MD_BSY_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_MAC_STAT_DMA_REG(128bit):\n+ * Port MAC statistical counter DMA register\n+ */\n+#define\tFR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MAC_STAT_DMA_CMD_LBN 48\n+#define\tFRF_AB_MAC_STAT_DMA_CMD_WIDTH 1\n+#define\tFRF_AB_MAC_STAT_DMA_ADR_LBN 0\n+#define\tFRF_AB_MAC_STAT_DMA_ADR_WIDTH 48\n+#define\tFRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0\n+#define\tFRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32\n+#define\tFRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32\n+#define\tFRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_MAC_CTRL_REG(128bit):\n+ * Port MAC control register\n+ */\n+#define\tFR_AB_MAC_CTRL_REG_OFST 0x00000c80\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MAC_XOFF_VAL_LBN 16\n+#define\tFRF_AB_MAC_XOFF_VAL_WIDTH 16\n+#define\tFRF_BB_TXFIFO_DRAIN_EN_LBN 7\n+#define\tFRF_BB_TXFIFO_DRAIN_EN_WIDTH 1\n+#define\tFRF_AB_MAC_XG_DISTXCRC_LBN 5\n+#define\tFRF_AB_MAC_XG_DISTXCRC_WIDTH 1\n+#define\tFRF_AB_MAC_BCAD_ACPT_LBN 4\n+#define\tFRF_AB_MAC_BCAD_ACPT_WIDTH 1\n+#define\tFRF_AB_MAC_UC_PROM_LBN 3\n+#define\tFRF_AB_MAC_UC_PROM_WIDTH 1\n+#define\tFRF_AB_MAC_LINK_STATUS_LBN 2\n+#define\tFRF_AB_MAC_LINK_STATUS_WIDTH 1\n+#define\tFRF_AB_MAC_SPEED_LBN 0\n+#define\tFRF_AB_MAC_SPEED_WIDTH 2\n+#define\tFRF_AB_MAC_SPEED_10M 0\n+#define\tFRF_AB_MAC_SPEED_100M 1\n+#define\tFRF_AB_MAC_SPEED_1G 2\n+#define\tFRF_AB_MAC_SPEED_10G 3\n+\n+/*\n+ * FR_BB_GEN_MODE_REG(128bit):\n+ * General Purpose mode register (external interrupt mask)\n+ */\n+#define\tFR_BB_GEN_MODE_REG_OFST 0x00000c90\n+/* falconb0=net_func_bar2 */\n+\n+#define\tFRF_BB_XFP_PHY_INT_POL_SEL_LBN 3\n+#define\tFRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1\n+#define\tFRF_BB_XG_PHY_INT_POL_SEL_LBN 2\n+#define\tFRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1\n+#define\tFRF_BB_XFP_PHY_INT_MASK_LBN 1\n+#define\tFRF_BB_XFP_PHY_INT_MASK_WIDTH 1\n+#define\tFRF_BB_XG_PHY_INT_MASK_LBN 0\n+#define\tFRF_BB_XG_PHY_INT_MASK_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_MAC_MC_HASH_REG0(128bit):\n+ * Multicast address hash table\n+ */\n+#define\tFR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MAC_MCAST_HASH0_LBN 0\n+#define\tFRF_AB_MAC_MCAST_HASH0_WIDTH 128\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW0_LBN 0\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW1_LBN 32\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW2_LBN 64\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW3_LBN 96\n+#define\tFRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32\n+\n+\n+/*\n+ * FR_AB_MAC_MC_HASH_REG1(128bit):\n+ * Multicast address hash table\n+ */\n+#define\tFR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_MAC_MCAST_HASH1_LBN 0\n+#define\tFRF_AB_MAC_MCAST_HASH1_WIDTH 128\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW0_LBN 0\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW1_LBN 32\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW2_LBN 64\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW3_LBN 96\n+#define\tFRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32\n+\n+\n+/*\n+ * FR_AB_GM_CFG1_REG(32bit):\n+ * GMAC configuration register 1\n+ */\n+#define\tFR_AB_GM_CFG1_REG_OFST 0x00000e00\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_SW_RST_LBN 31\n+#define\tFRF_AB_GM_SW_RST_WIDTH 1\n+#define\tFRF_AB_GM_SIM_RST_LBN 30\n+#define\tFRF_AB_GM_SIM_RST_WIDTH 1\n+#define\tFRF_AB_GM_RST_RX_MAC_CTL_LBN 19\n+#define\tFRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1\n+#define\tFRF_AB_GM_RST_TX_MAC_CTL_LBN 18\n+#define\tFRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1\n+#define\tFRF_AB_GM_RST_RX_FUNC_LBN 17\n+#define\tFRF_AB_GM_RST_RX_FUNC_WIDTH 1\n+#define\tFRF_AB_GM_RST_TX_FUNC_LBN 16\n+#define\tFRF_AB_GM_RST_TX_FUNC_WIDTH 1\n+#define\tFRF_AB_GM_LOOP_LBN 8\n+#define\tFRF_AB_GM_LOOP_WIDTH 1\n+#define\tFRF_AB_GM_RX_FC_EN_LBN 5\n+#define\tFRF_AB_GM_RX_FC_EN_WIDTH 1\n+#define\tFRF_AB_GM_TX_FC_EN_LBN 4\n+#define\tFRF_AB_GM_TX_FC_EN_WIDTH 1\n+#define\tFRF_AB_GM_SYNC_RXEN_LBN 3\n+#define\tFRF_AB_GM_SYNC_RXEN_WIDTH 1\n+#define\tFRF_AB_GM_RX_EN_LBN 2\n+#define\tFRF_AB_GM_RX_EN_WIDTH 1\n+#define\tFRF_AB_GM_SYNC_TXEN_LBN 1\n+#define\tFRF_AB_GM_SYNC_TXEN_WIDTH 1\n+#define\tFRF_AB_GM_TX_EN_LBN 0\n+#define\tFRF_AB_GM_TX_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_GM_CFG2_REG(32bit):\n+ * GMAC configuration register 2\n+ */\n+#define\tFR_AB_GM_CFG2_REG_OFST 0x00000e10\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_PAMBL_LEN_LBN 12\n+#define\tFRF_AB_GM_PAMBL_LEN_WIDTH 4\n+#define\tFRF_AB_GM_IF_MODE_LBN 8\n+#define\tFRF_AB_GM_IF_MODE_WIDTH 2\n+#define\tFRF_AB_GM_IF_MODE_BYTE_MODE 2\n+#define\tFRF_AB_GM_IF_MODE_NIBBLE_MODE 1\n+#define\tFRF_AB_GM_HUGE_FRM_EN_LBN 5\n+#define\tFRF_AB_GM_HUGE_FRM_EN_WIDTH 1\n+#define\tFRF_AB_GM_LEN_CHK_LBN 4\n+#define\tFRF_AB_GM_LEN_CHK_WIDTH 1\n+#define\tFRF_AB_GM_PAD_CRC_EN_LBN 2\n+#define\tFRF_AB_GM_PAD_CRC_EN_WIDTH 1\n+#define\tFRF_AB_GM_CRC_EN_LBN 1\n+#define\tFRF_AB_GM_CRC_EN_WIDTH 1\n+#define\tFRF_AB_GM_FD_LBN 0\n+#define\tFRF_AB_GM_FD_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_GM_IPG_REG(32bit):\n+ * GMAC IPG register\n+ */\n+#define\tFR_AB_GM_IPG_REG_OFST 0x00000e20\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_NONB2B_IPG1_LBN 24\n+#define\tFRF_AB_GM_NONB2B_IPG1_WIDTH 7\n+#define\tFRF_AB_GM_NONB2B_IPG2_LBN 16\n+#define\tFRF_AB_GM_NONB2B_IPG2_WIDTH 7\n+#define\tFRF_AB_GM_MIN_IPG_ENF_LBN 8\n+#define\tFRF_AB_GM_MIN_IPG_ENF_WIDTH 8\n+#define\tFRF_AB_GM_B2B_IPG_LBN 0\n+#define\tFRF_AB_GM_B2B_IPG_WIDTH 7\n+\n+\n+/*\n+ * FR_AB_GM_HD_REG(32bit):\n+ * GMAC half duplex register\n+ */\n+#define\tFR_AB_GM_HD_REG_OFST 0x00000e30\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_ALT_BOFF_VAL_LBN 20\n+#define\tFRF_AB_GM_ALT_BOFF_VAL_WIDTH 4\n+#define\tFRF_AB_GM_ALT_BOFF_EN_LBN 19\n+#define\tFRF_AB_GM_ALT_BOFF_EN_WIDTH 1\n+#define\tFRF_AB_GM_BP_NO_BOFF_LBN 18\n+#define\tFRF_AB_GM_BP_NO_BOFF_WIDTH 1\n+#define\tFRF_AB_GM_DIS_BOFF_LBN 17\n+#define\tFRF_AB_GM_DIS_BOFF_WIDTH 1\n+#define\tFRF_AB_GM_EXDEF_TX_EN_LBN 16\n+#define\tFRF_AB_GM_EXDEF_TX_EN_WIDTH 1\n+#define\tFRF_AB_GM_RTRY_LIMIT_LBN 12\n+#define\tFRF_AB_GM_RTRY_LIMIT_WIDTH 4\n+#define\tFRF_AB_GM_COL_WIN_LBN 0\n+#define\tFRF_AB_GM_COL_WIN_WIDTH 10\n+\n+\n+/*\n+ * FR_AB_GM_MAX_FLEN_REG(32bit):\n+ * GMAC maximum frame length register\n+ */\n+#define\tFR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_MAX_FLEN_LBN 0\n+#define\tFRF_AB_GM_MAX_FLEN_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_GM_TEST_REG(32bit):\n+ * GMAC test register\n+ */\n+#define\tFR_AB_GM_TEST_REG_OFST 0x00000e70\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_MAX_BOFF_LBN 3\n+#define\tFRF_AB_GM_MAX_BOFF_WIDTH 1\n+#define\tFRF_AB_GM_REG_TX_FLOW_EN_LBN 2\n+#define\tFRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1\n+#define\tFRF_AB_GM_TEST_PAUSE_LBN 1\n+#define\tFRF_AB_GM_TEST_PAUSE_WIDTH 1\n+#define\tFRF_AB_GM_SHORT_SLOT_LBN 0\n+#define\tFRF_AB_GM_SHORT_SLOT_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_GM_ADR1_REG(32bit):\n+ * GMAC station address register 1\n+ */\n+#define\tFR_AB_GM_ADR1_REG_OFST 0x00000f00\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_ADR_B0_LBN 24\n+#define\tFRF_AB_GM_ADR_B0_WIDTH 8\n+#define\tFRF_AB_GM_ADR_B1_LBN 16\n+#define\tFRF_AB_GM_ADR_B1_WIDTH 8\n+#define\tFRF_AB_GM_ADR_B2_LBN 8\n+#define\tFRF_AB_GM_ADR_B2_WIDTH 8\n+#define\tFRF_AB_GM_ADR_B3_LBN 0\n+#define\tFRF_AB_GM_ADR_B3_WIDTH 8\n+\n+\n+/*\n+ * FR_AB_GM_ADR2_REG(32bit):\n+ * GMAC station address register 2\n+ */\n+#define\tFR_AB_GM_ADR2_REG_OFST 0x00000f10\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GM_ADR_B4_LBN 24\n+#define\tFRF_AB_GM_ADR_B4_WIDTH 8\n+#define\tFRF_AB_GM_ADR_B5_LBN 16\n+#define\tFRF_AB_GM_ADR_B5_WIDTH 8\n+\n+\n+/*\n+ * FR_AB_GMF_CFG0_REG(32bit):\n+ * GMAC FIFO configuration register 0\n+ */\n+#define\tFR_AB_GMF_CFG0_REG_OFST 0x00000f20\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GMF_FTFENRPLY_LBN 20\n+#define\tFRF_AB_GMF_FTFENRPLY_WIDTH 1\n+#define\tFRF_AB_GMF_STFENRPLY_LBN 19\n+#define\tFRF_AB_GMF_STFENRPLY_WIDTH 1\n+#define\tFRF_AB_GMF_FRFENRPLY_LBN 18\n+#define\tFRF_AB_GMF_FRFENRPLY_WIDTH 1\n+#define\tFRF_AB_GMF_SRFENRPLY_LBN 17\n+#define\tFRF_AB_GMF_SRFENRPLY_WIDTH 1\n+#define\tFRF_AB_GMF_WTMENRPLY_LBN 16\n+#define\tFRF_AB_GMF_WTMENRPLY_WIDTH 1\n+#define\tFRF_AB_GMF_FTFENREQ_LBN 12\n+#define\tFRF_AB_GMF_FTFENREQ_WIDTH 1\n+#define\tFRF_AB_GMF_STFENREQ_LBN 11\n+#define\tFRF_AB_GMF_STFENREQ_WIDTH 1\n+#define\tFRF_AB_GMF_FRFENREQ_LBN 10\n+#define\tFRF_AB_GMF_FRFENREQ_WIDTH 1\n+#define\tFRF_AB_GMF_SRFENREQ_LBN 9\n+#define\tFRF_AB_GMF_SRFENREQ_WIDTH 1\n+#define\tFRF_AB_GMF_WTMENREQ_LBN 8\n+#define\tFRF_AB_GMF_WTMENREQ_WIDTH 1\n+#define\tFRF_AB_GMF_HSTRSTFT_LBN 4\n+#define\tFRF_AB_GMF_HSTRSTFT_WIDTH 1\n+#define\tFRF_AB_GMF_HSTRSTST_LBN 3\n+#define\tFRF_AB_GMF_HSTRSTST_WIDTH 1\n+#define\tFRF_AB_GMF_HSTRSTFR_LBN 2\n+#define\tFRF_AB_GMF_HSTRSTFR_WIDTH 1\n+#define\tFRF_AB_GMF_HSTRSTSR_LBN 1\n+#define\tFRF_AB_GMF_HSTRSTSR_WIDTH 1\n+#define\tFRF_AB_GMF_HSTRSTWT_LBN 0\n+#define\tFRF_AB_GMF_HSTRSTWT_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_GMF_CFG1_REG(32bit):\n+ * GMAC FIFO configuration register 1\n+ */\n+#define\tFR_AB_GMF_CFG1_REG_OFST 0x00000f30\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GMF_CFGFRTH_LBN 16\n+#define\tFRF_AB_GMF_CFGFRTH_WIDTH 5\n+#define\tFRF_AB_GMF_CFGXOFFRTX_LBN 0\n+#define\tFRF_AB_GMF_CFGXOFFRTX_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_GMF_CFG2_REG(32bit):\n+ * GMAC FIFO configuration register 2\n+ */\n+#define\tFR_AB_GMF_CFG2_REG_OFST 0x00000f40\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GMF_CFGHWM_LBN 16\n+#define\tFRF_AB_GMF_CFGHWM_WIDTH 6\n+#define\tFRF_AB_GMF_CFGLWM_LBN 0\n+#define\tFRF_AB_GMF_CFGLWM_WIDTH 6\n+\n+\n+/*\n+ * FR_AB_GMF_CFG3_REG(32bit):\n+ * GMAC FIFO configuration register 3\n+ */\n+#define\tFR_AB_GMF_CFG3_REG_OFST 0x00000f50\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GMF_CFGHWMFT_LBN 16\n+#define\tFRF_AB_GMF_CFGHWMFT_WIDTH 6\n+#define\tFRF_AB_GMF_CFGFTTH_LBN 0\n+#define\tFRF_AB_GMF_CFGFTTH_WIDTH 6\n+\n+\n+/*\n+ * FR_AB_GMF_CFG4_REG(32bit):\n+ * GMAC FIFO configuration register 4\n+ */\n+#define\tFR_AB_GMF_CFG4_REG_OFST 0x00000f60\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GMF_HSTFLTRFRM_LBN 0\n+#define\tFRF_AB_GMF_HSTFLTRFRM_WIDTH 18\n+\n+\n+/*\n+ * FR_AB_GMF_CFG5_REG(32bit):\n+ * GMAC FIFO configuration register 5\n+ */\n+#define\tFR_AB_GMF_CFG5_REG_OFST 0x00000f70\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_GMF_CFGHDPLX_LBN 22\n+#define\tFRF_AB_GMF_CFGHDPLX_WIDTH 1\n+#define\tFRF_AB_GMF_SRFULL_LBN 21\n+#define\tFRF_AB_GMF_SRFULL_WIDTH 1\n+#define\tFRF_AB_GMF_HSTSRFULLCLR_LBN 20\n+#define\tFRF_AB_GMF_HSTSRFULLCLR_WIDTH 1\n+#define\tFRF_AB_GMF_CFGBYTMODE_LBN 19\n+#define\tFRF_AB_GMF_CFGBYTMODE_WIDTH 1\n+#define\tFRF_AB_GMF_HSTDRPLT64_LBN 18\n+#define\tFRF_AB_GMF_HSTDRPLT64_WIDTH 1\n+#define\tFRF_AB_GMF_HSTFLTRFRMDC_LBN 0\n+#define\tFRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18\n+\n+\n+/*\n+ * FR_BB_TX_SRC_MAC_TBL(128bit):\n+ * Transmit IP source address filter table\n+ */\n+#define\tFR_BB_TX_SRC_MAC_TBL_OFST 0x00001000\n+/* falconb0=net_func_bar2 */\n+#define\tFR_BB_TX_SRC_MAC_TBL_STEP 16\n+#define\tFR_BB_TX_SRC_MAC_TBL_ROWS 16\n+\n+#define\tFRF_BB_TX_SRC_MAC_ADR_1_LBN 64\n+#define\tFRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48\n+#define\tFRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64\n+#define\tFRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32\n+#define\tFRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96\n+#define\tFRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16\n+#define\tFRF_BB_TX_SRC_MAC_ADR_0_LBN 0\n+#define\tFRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48\n+#define\tFRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0\n+#define\tFRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32\n+#define\tFRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32\n+#define\tFRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16\n+\n+\n+/*\n+ * FR_BB_TX_SRC_MAC_CTL_REG(128bit):\n+ * Transmit MAC source address filter control\n+ */\n+#define\tFR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100\n+/* falconb0=net_func_bar2 */\n+\n+#define\tFRF_BB_TX_SRC_DROP_CTR_LBN 16\n+#define\tFRF_BB_TX_SRC_DROP_CTR_WIDTH 16\n+#define\tFRF_BB_TX_SRC_FLTR_EN_LBN 15\n+#define\tFRF_BB_TX_SRC_FLTR_EN_WIDTH 1\n+#define\tFRF_BB_TX_DROP_CTR_CLR_LBN 12\n+#define\tFRF_BB_TX_DROP_CTR_CLR_WIDTH 1\n+#define\tFRF_BB_TX_MAC_QID_SEL_LBN 0\n+#define\tFRF_BB_TX_MAC_QID_SEL_WIDTH 3\n+\n+\n+/*\n+ * FR_AB_XM_ADR_LO_REG(128bit):\n+ * XGMAC address register low\n+ */\n+#define\tFR_AB_XM_ADR_LO_REG_OFST 0x00001200\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_ADR_LO_LBN 0\n+#define\tFRF_AB_XM_ADR_LO_WIDTH 32\n+\n+\n+/*\n+ * FR_AB_XM_ADR_HI_REG(128bit):\n+ * XGMAC address register high\n+ */\n+#define\tFR_AB_XM_ADR_HI_REG_OFST 0x00001210\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_ADR_HI_LBN 0\n+#define\tFRF_AB_XM_ADR_HI_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_XM_GLB_CFG_REG(128bit):\n+ * XGMAC global configuration\n+ */\n+#define\tFR_AB_XM_GLB_CFG_REG_OFST 0x00001220\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_RMTFLT_GEN_LBN 17\n+#define\tFRF_AB_XM_RMTFLT_GEN_WIDTH 1\n+#define\tFRF_AB_XM_DEBUG_MODE_LBN 16\n+#define\tFRF_AB_XM_DEBUG_MODE_WIDTH 1\n+#define\tFRF_AB_XM_RX_STAT_EN_LBN 11\n+#define\tFRF_AB_XM_RX_STAT_EN_WIDTH 1\n+#define\tFRF_AB_XM_TX_STAT_EN_LBN 10\n+#define\tFRF_AB_XM_TX_STAT_EN_WIDTH 1\n+#define\tFRF_AB_XM_RX_JUMBO_MODE_LBN 6\n+#define\tFRF_AB_XM_RX_JUMBO_MODE_WIDTH 1\n+#define\tFRF_AB_XM_WAN_MODE_LBN 5\n+#define\tFRF_AB_XM_WAN_MODE_WIDTH 1\n+#define\tFRF_AB_XM_INTCLR_MODE_LBN 3\n+#define\tFRF_AB_XM_INTCLR_MODE_WIDTH 1\n+#define\tFRF_AB_XM_CORE_RST_LBN 0\n+#define\tFRF_AB_XM_CORE_RST_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XM_TX_CFG_REG(128bit):\n+ * XGMAC transmit configuration\n+ */\n+#define\tFR_AB_XM_TX_CFG_REG_OFST 0x00001230\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_TX_PROG_LBN 24\n+#define\tFRF_AB_XM_TX_PROG_WIDTH 1\n+#define\tFRF_AB_XM_IPG_LBN 16\n+#define\tFRF_AB_XM_IPG_WIDTH 4\n+#define\tFRF_AB_XM_FCNTL_LBN 10\n+#define\tFRF_AB_XM_FCNTL_WIDTH 1\n+#define\tFRF_AB_XM_TXCRC_LBN 8\n+#define\tFRF_AB_XM_TXCRC_WIDTH 1\n+#define\tFRF_AB_XM_EDRC_LBN 6\n+#define\tFRF_AB_XM_EDRC_WIDTH 1\n+#define\tFRF_AB_XM_AUTO_PAD_LBN 5\n+#define\tFRF_AB_XM_AUTO_PAD_WIDTH 1\n+#define\tFRF_AB_XM_TX_PRMBL_LBN 2\n+#define\tFRF_AB_XM_TX_PRMBL_WIDTH 1\n+#define\tFRF_AB_XM_TXEN_LBN 1\n+#define\tFRF_AB_XM_TXEN_WIDTH 1\n+#define\tFRF_AB_XM_TX_RST_LBN 0\n+#define\tFRF_AB_XM_TX_RST_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XM_RX_CFG_REG(128bit):\n+ * XGMAC receive configuration\n+ */\n+#define\tFR_AB_XM_RX_CFG_REG_OFST 0x00001240\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_PASS_LENERR_LBN 26\n+#define\tFRF_AB_XM_PASS_LENERR_WIDTH 1\n+#define\tFRF_AB_XM_PASS_CRC_ERR_LBN 25\n+#define\tFRF_AB_XM_PASS_CRC_ERR_WIDTH 1\n+#define\tFRF_AB_XM_PASS_PRMBLE_ERR_LBN 24\n+#define\tFRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1\n+#define\tFRF_AB_XM_REJ_BCAST_LBN 20\n+#define\tFRF_AB_XM_REJ_BCAST_WIDTH 1\n+#define\tFRF_AB_XM_ACPT_ALL_MCAST_LBN 11\n+#define\tFRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1\n+#define\tFRF_AB_XM_ACPT_ALL_UCAST_LBN 9\n+#define\tFRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1\n+#define\tFRF_AB_XM_AUTO_DEPAD_LBN 8\n+#define\tFRF_AB_XM_AUTO_DEPAD_WIDTH 1\n+#define\tFRF_AB_XM_RXCRC_LBN 3\n+#define\tFRF_AB_XM_RXCRC_WIDTH 1\n+#define\tFRF_AB_XM_RX_PRMBL_LBN 2\n+#define\tFRF_AB_XM_RX_PRMBL_WIDTH 1\n+#define\tFRF_AB_XM_RXEN_LBN 1\n+#define\tFRF_AB_XM_RXEN_WIDTH 1\n+#define\tFRF_AB_XM_RX_RST_LBN 0\n+#define\tFRF_AB_XM_RX_RST_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XM_MGT_INT_MASK(128bit):\n+ * documentation to be written for sum_XM_MGT_INT_MASK\n+ */\n+#define\tFR_AB_XM_MGT_INT_MASK_OFST 0x00001250\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_MSK_STA_INTR_LBN 16\n+#define\tFRF_AB_XM_MSK_STA_INTR_WIDTH 1\n+#define\tFRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9\n+#define\tFRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1\n+#define\tFRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8\n+#define\tFRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1\n+#define\tFRF_AB_XM_MSK_PRMBLE_ERR_LBN 2\n+#define\tFRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1\n+#define\tFRF_AB_XM_MSK_RMTFLT_LBN 1\n+#define\tFRF_AB_XM_MSK_RMTFLT_WIDTH 1\n+#define\tFRF_AB_XM_MSK_LCLFLT_LBN 0\n+#define\tFRF_AB_XM_MSK_LCLFLT_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XM_FC_REG(128bit):\n+ * XGMAC flow control register\n+ */\n+#define\tFR_AB_XM_FC_REG_OFST 0x00001270\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_PAUSE_TIME_LBN 16\n+#define\tFRF_AB_XM_PAUSE_TIME_WIDTH 16\n+#define\tFRF_AB_XM_RX_MAC_STAT_LBN 11\n+#define\tFRF_AB_XM_RX_MAC_STAT_WIDTH 1\n+#define\tFRF_AB_XM_TX_MAC_STAT_LBN 10\n+#define\tFRF_AB_XM_TX_MAC_STAT_WIDTH 1\n+#define\tFRF_AB_XM_MCNTL_PASS_LBN 8\n+#define\tFRF_AB_XM_MCNTL_PASS_WIDTH 2\n+#define\tFRF_AB_XM_REJ_CNTL_UCAST_LBN 6\n+#define\tFRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1\n+#define\tFRF_AB_XM_REJ_CNTL_MCAST_LBN 5\n+#define\tFRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1\n+#define\tFRF_AB_XM_ZPAUSE_LBN 2\n+#define\tFRF_AB_XM_ZPAUSE_WIDTH 1\n+#define\tFRF_AB_XM_XMIT_PAUSE_LBN 1\n+#define\tFRF_AB_XM_XMIT_PAUSE_WIDTH 1\n+#define\tFRF_AB_XM_DIS_FCNTL_LBN 0\n+#define\tFRF_AB_XM_DIS_FCNTL_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XM_PAUSE_TIME_REG(128bit):\n+ * XGMAC pause time register\n+ */\n+#define\tFR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_TX_PAUSE_CNT_LBN 16\n+#define\tFRF_AB_XM_TX_PAUSE_CNT_WIDTH 16\n+#define\tFRF_AB_XM_RX_PAUSE_CNT_LBN 0\n+#define\tFRF_AB_XM_RX_PAUSE_CNT_WIDTH 16\n+\n+\n+/*\n+ * FR_AB_XM_TX_PARAM_REG(128bit):\n+ * XGMAC transmit parameter register\n+ */\n+#define\tFR_AB_XM_TX_PARAM_REG_OFST 0x000012d0\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_TX_JUMBO_MODE_LBN 31\n+#define\tFRF_AB_XM_TX_JUMBO_MODE_WIDTH 1\n+#define\tFRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19\n+#define\tFRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11\n+#define\tFRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16\n+#define\tFRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3\n+#define\tFRF_AB_XM_PAD_CHAR_LBN 0\n+#define\tFRF_AB_XM_PAD_CHAR_WIDTH 8\n+\n+\n+/*\n+ * FR_AB_XM_RX_PARAM_REG(128bit):\n+ * XGMAC receive parameter register\n+ */\n+#define\tFR_AB_XM_RX_PARAM_REG_OFST 0x000012e0\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3\n+#define\tFRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11\n+#define\tFRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0\n+#define\tFRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3\n+\n+\n+/*\n+ * FR_AB_XM_MGT_INT_MSK_REG(128bit):\n+ * XGMAC management interrupt mask register\n+ */\n+#define\tFR_AB_XM_MGT_INT_REG_OFST 0x000012f0\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XM_STAT_CNTR_OF_LBN 9\n+#define\tFRF_AB_XM_STAT_CNTR_OF_WIDTH 1\n+#define\tFRF_AB_XM_STAT_CNTR_HF_LBN 8\n+#define\tFRF_AB_XM_STAT_CNTR_HF_WIDTH 1\n+#define\tFRF_AB_XM_PRMBLE_ERR_LBN 2\n+#define\tFRF_AB_XM_PRMBLE_ERR_WIDTH 1\n+#define\tFRF_AB_XM_RMTFLT_LBN 1\n+#define\tFRF_AB_XM_RMTFLT_WIDTH 1\n+#define\tFRF_AB_XM_LCLFLT_LBN 0\n+#define\tFRF_AB_XM_LCLFLT_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XX_PWR_RST_REG(128bit):\n+ * XGXS/XAUI powerdown/reset register\n+ */\n+#define\tFR_AB_XX_PWR_RST_REG_OFST 0x00001300\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XX_PWRDND_SIG_LBN 31\n+#define\tFRF_AB_XX_PWRDND_SIG_WIDTH 1\n+#define\tFRF_AB_XX_PWRDNC_SIG_LBN 30\n+#define\tFRF_AB_XX_PWRDNC_SIG_WIDTH 1\n+#define\tFRF_AB_XX_PWRDNB_SIG_LBN 29\n+#define\tFRF_AB_XX_PWRDNB_SIG_WIDTH 1\n+#define\tFRF_AB_XX_PWRDNA_SIG_LBN 28\n+#define\tFRF_AB_XX_PWRDNA_SIG_WIDTH 1\n+#define\tFRF_AB_XX_SIM_MODE_LBN 27\n+#define\tFRF_AB_XX_SIM_MODE_WIDTH 1\n+#define\tFRF_AB_XX_RSTPLLCD_SIG_LBN 25\n+#define\tFRF_AB_XX_RSTPLLCD_SIG_WIDTH 1\n+#define\tFRF_AB_XX_RSTPLLAB_SIG_LBN 24\n+#define\tFRF_AB_XX_RSTPLLAB_SIG_WIDTH 1\n+#define\tFRF_AB_XX_RESETD_SIG_LBN 23\n+#define\tFRF_AB_XX_RESETD_SIG_WIDTH 1\n+#define\tFRF_AB_XX_RESETC_SIG_LBN 22\n+#define\tFRF_AB_XX_RESETC_SIG_WIDTH 1\n+#define\tFRF_AB_XX_RESETB_SIG_LBN 21\n+#define\tFRF_AB_XX_RESETB_SIG_WIDTH 1\n+#define\tFRF_AB_XX_RESETA_SIG_LBN 20\n+#define\tFRF_AB_XX_RESETA_SIG_WIDTH 1\n+#define\tFRF_AB_XX_RSTXGXSRX_SIG_LBN 18\n+#define\tFRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1\n+#define\tFRF_AB_XX_RSTXGXSTX_SIG_LBN 17\n+#define\tFRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1\n+#define\tFRF_AB_XX_SD_RST_ACT_LBN 16\n+#define\tFRF_AB_XX_SD_RST_ACT_WIDTH 1\n+#define\tFRF_AB_XX_PWRDND_EN_LBN 15\n+#define\tFRF_AB_XX_PWRDND_EN_WIDTH 1\n+#define\tFRF_AB_XX_PWRDNC_EN_LBN 14\n+#define\tFRF_AB_XX_PWRDNC_EN_WIDTH 1\n+#define\tFRF_AB_XX_PWRDNB_EN_LBN 13\n+#define\tFRF_AB_XX_PWRDNB_EN_WIDTH 1\n+#define\tFRF_AB_XX_PWRDNA_EN_LBN 12\n+#define\tFRF_AB_XX_PWRDNA_EN_WIDTH 1\n+#define\tFRF_AB_XX_RSTPLLCD_EN_LBN 9\n+#define\tFRF_AB_XX_RSTPLLCD_EN_WIDTH 1\n+#define\tFRF_AB_XX_RSTPLLAB_EN_LBN 8\n+#define\tFRF_AB_XX_RSTPLLAB_EN_WIDTH 1\n+#define\tFRF_AB_XX_RESETD_EN_LBN 7\n+#define\tFRF_AB_XX_RESETD_EN_WIDTH 1\n+#define\tFRF_AB_XX_RESETC_EN_LBN 6\n+#define\tFRF_AB_XX_RESETC_EN_WIDTH 1\n+#define\tFRF_AB_XX_RESETB_EN_LBN 5\n+#define\tFRF_AB_XX_RESETB_EN_WIDTH 1\n+#define\tFRF_AB_XX_RESETA_EN_LBN 4\n+#define\tFRF_AB_XX_RESETA_EN_WIDTH 1\n+#define\tFRF_AB_XX_RSTXGXSRX_EN_LBN 2\n+#define\tFRF_AB_XX_RSTXGXSRX_EN_WIDTH 1\n+#define\tFRF_AB_XX_RSTXGXSTX_EN_LBN 1\n+#define\tFRF_AB_XX_RSTXGXSTX_EN_WIDTH 1\n+#define\tFRF_AB_XX_RST_XX_EN_LBN 0\n+#define\tFRF_AB_XX_RST_XX_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XX_SD_CTL_REG(128bit):\n+ * XGXS/XAUI powerdown/reset control register\n+ */\n+#define\tFR_AB_XX_SD_CTL_REG_OFST 0x00001310\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XX_TERMADJ1_LBN 17\n+#define\tFRF_AB_XX_TERMADJ1_WIDTH 1\n+#define\tFRF_AB_XX_TERMADJ0_LBN 16\n+#define\tFRF_AB_XX_TERMADJ0_WIDTH 1\n+#define\tFRF_AB_XX_HIDRVD_LBN 15\n+#define\tFRF_AB_XX_HIDRVD_WIDTH 1\n+#define\tFRF_AB_XX_LODRVD_LBN 14\n+#define\tFRF_AB_XX_LODRVD_WIDTH 1\n+#define\tFRF_AB_XX_HIDRVC_LBN 13\n+#define\tFRF_AB_XX_HIDRVC_WIDTH 1\n+#define\tFRF_AB_XX_LODRVC_LBN 12\n+#define\tFRF_AB_XX_LODRVC_WIDTH 1\n+#define\tFRF_AB_XX_HIDRVB_LBN 11\n+#define\tFRF_AB_XX_HIDRVB_WIDTH 1\n+#define\tFRF_AB_XX_LODRVB_LBN 10\n+#define\tFRF_AB_XX_LODRVB_WIDTH 1\n+#define\tFRF_AB_XX_HIDRVA_LBN 9\n+#define\tFRF_AB_XX_HIDRVA_WIDTH 1\n+#define\tFRF_AB_XX_LODRVA_LBN 8\n+#define\tFRF_AB_XX_LODRVA_WIDTH 1\n+#define\tFRF_AB_XX_LPBKD_LBN 3\n+#define\tFRF_AB_XX_LPBKD_WIDTH 1\n+#define\tFRF_AB_XX_LPBKC_LBN 2\n+#define\tFRF_AB_XX_LPBKC_WIDTH 1\n+#define\tFRF_AB_XX_LPBKB_LBN 1\n+#define\tFRF_AB_XX_LPBKB_WIDTH 1\n+#define\tFRF_AB_XX_LPBKA_LBN 0\n+#define\tFRF_AB_XX_LPBKA_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XX_TXDRV_CTL_REG(128bit):\n+ * XAUI SerDes transmit drive control register\n+ */\n+#define\tFR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XX_DEQD_LBN 28\n+#define\tFRF_AB_XX_DEQD_WIDTH 4\n+#define\tFRF_AB_XX_DEQC_LBN 24\n+#define\tFRF_AB_XX_DEQC_WIDTH 4\n+#define\tFRF_AB_XX_DEQB_LBN 20\n+#define\tFRF_AB_XX_DEQB_WIDTH 4\n+#define\tFRF_AB_XX_DEQA_LBN 16\n+#define\tFRF_AB_XX_DEQA_WIDTH 4\n+#define\tFRF_AB_XX_DTXD_LBN 12\n+#define\tFRF_AB_XX_DTXD_WIDTH 4\n+#define\tFRF_AB_XX_DTXC_LBN 8\n+#define\tFRF_AB_XX_DTXC_WIDTH 4\n+#define\tFRF_AB_XX_DTXB_LBN 4\n+#define\tFRF_AB_XX_DTXB_WIDTH 4\n+#define\tFRF_AB_XX_DTXA_LBN 0\n+#define\tFRF_AB_XX_DTXA_WIDTH 4\n+\n+\n+/*\n+ * FR_AB_XX_PRBS_CTL_REG(128bit):\n+ * documentation to be written for sum_XX_PRBS_CTL_REG\n+ */\n+#define\tFR_AB_XX_PRBS_CTL_REG_OFST 0x00001330\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30\n+#define\tFRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH3_RX_PRBS_INV_LBN 29\n+#define\tFRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28\n+#define\tFRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1\n+#define\tFRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26\n+#define\tFRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH2_RX_PRBS_INV_LBN 25\n+#define\tFRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24\n+#define\tFRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1\n+#define\tFRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22\n+#define\tFRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH1_RX_PRBS_INV_LBN 21\n+#define\tFRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20\n+#define\tFRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1\n+#define\tFRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18\n+#define\tFRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH0_RX_PRBS_INV_LBN 17\n+#define\tFRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16\n+#define\tFRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1\n+#define\tFRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14\n+#define\tFRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH3_TX_PRBS_INV_LBN 13\n+#define\tFRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12\n+#define\tFRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1\n+#define\tFRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10\n+#define\tFRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH2_TX_PRBS_INV_LBN 9\n+#define\tFRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8\n+#define\tFRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1\n+#define\tFRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6\n+#define\tFRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH1_TX_PRBS_INV_LBN 5\n+#define\tFRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4\n+#define\tFRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1\n+#define\tFRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2\n+#define\tFRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2\n+#define\tFRF_AB_XX_CH0_TX_PRBS_INV_LBN 1\n+#define\tFRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1\n+#define\tFRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0\n+#define\tFRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XX_PRBS_CHK_REG(128bit):\n+ * documentation to be written for sum_XX_PRBS_CHK_REG\n+ */\n+#define\tFR_AB_XX_PRBS_CHK_REG_OFST 0x00001340\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XX_REV_LB_EN_LBN 16\n+#define\tFRF_AB_XX_REV_LB_EN_WIDTH 1\n+#define\tFRF_AB_XX_CH3_DEG_DET_LBN 15\n+#define\tFRF_AB_XX_CH3_DEG_DET_WIDTH 1\n+#define\tFRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14\n+#define\tFRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1\n+#define\tFRF_AB_XX_CH3_PRBS_FRUN_LBN 13\n+#define\tFRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1\n+#define\tFRF_AB_XX_CH3_ERR_CHK_LBN 12\n+#define\tFRF_AB_XX_CH3_ERR_CHK_WIDTH 1\n+#define\tFRF_AB_XX_CH2_DEG_DET_LBN 11\n+#define\tFRF_AB_XX_CH2_DEG_DET_WIDTH 1\n+#define\tFRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10\n+#define\tFRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1\n+#define\tFRF_AB_XX_CH2_PRBS_FRUN_LBN 9\n+#define\tFRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1\n+#define\tFRF_AB_XX_CH2_ERR_CHK_LBN 8\n+#define\tFRF_AB_XX_CH2_ERR_CHK_WIDTH 1\n+#define\tFRF_AB_XX_CH1_DEG_DET_LBN 7\n+#define\tFRF_AB_XX_CH1_DEG_DET_WIDTH 1\n+#define\tFRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6\n+#define\tFRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1\n+#define\tFRF_AB_XX_CH1_PRBS_FRUN_LBN 5\n+#define\tFRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1\n+#define\tFRF_AB_XX_CH1_ERR_CHK_LBN 4\n+#define\tFRF_AB_XX_CH1_ERR_CHK_WIDTH 1\n+#define\tFRF_AB_XX_CH0_DEG_DET_LBN 3\n+#define\tFRF_AB_XX_CH0_DEG_DET_WIDTH 1\n+#define\tFRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2\n+#define\tFRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1\n+#define\tFRF_AB_XX_CH0_PRBS_FRUN_LBN 1\n+#define\tFRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1\n+#define\tFRF_AB_XX_CH0_ERR_CHK_LBN 0\n+#define\tFRF_AB_XX_CH0_ERR_CHK_WIDTH 1\n+\n+\n+/*\n+ * FR_AB_XX_PRBS_ERR_REG(128bit):\n+ * documentation to be written for sum_XX_PRBS_ERR_REG\n+ */\n+#define\tFR_AB_XX_PRBS_ERR_REG_OFST 0x00001350\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24\n+#define\tFRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8\n+#define\tFRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16\n+#define\tFRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8\n+#define\tFRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8\n+#define\tFRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8\n+#define\tFRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0\n+#define\tFRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8\n+\n+\n+/*\n+ * FR_AB_XX_CORE_STAT_REG(128bit):\n+ * XAUI XGXS core status register\n+ */\n+#define\tFR_AB_XX_CORE_STAT_REG_OFST 0x00001360\n+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+\n+#define\tFRF_AB_XX_FORCE_SIG3_LBN 31\n+#define\tFRF_AB_XX_FORCE_SIG3_WIDTH 1\n+#define\tFRF_AB_XX_FORCE_SIG3_VAL_LBN 30\n+#define\tFRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1\n+#define\tFRF_AB_XX_FORCE_SIG2_LBN 29\n+#define\tFRF_AB_XX_FORCE_SIG2_WIDTH 1\n+#define\tFRF_AB_XX_FORCE_SIG2_VAL_LBN 28\n+#define\tFRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1\n+#define\tFRF_AB_XX_FORCE_SIG1_LBN 27\n+#define\tFRF_AB_XX_FORCE_SIG1_WIDTH 1\n+#define\tFRF_AB_XX_FORCE_SIG1_VAL_LBN 26\n+#define\tFRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1\n+#define\tFRF_AB_XX_FORCE_SIG0_LBN 25\n+#define\tFRF_AB_XX_FORCE_SIG0_WIDTH 1\n+#define\tFRF_AB_XX_FORCE_SIG0_VAL_LBN 24\n+#define\tFRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1\n+#define\tFRF_AB_XX_XGXS_LB_EN_LBN 23\n+#define\tFRF_AB_XX_XGXS_LB_EN_WIDTH 1\n+#define\tFRF_AB_XX_XGMII_LB_EN_LBN 22\n+#define\tFRF_AB_XX_XGMII_LB_EN_WIDTH 1\n+#define\tFRF_AB_XX_MATCH_FAULT_LBN 21\n+#define\tFRF_AB_XX_MATCH_FAULT_WIDTH 1\n+#define\tFRF_AB_XX_ALIGN_DONE_LBN 20\n+#define\tFRF_AB_XX_ALIGN_DONE_WIDTH 1\n+#define\tFRF_AB_XX_SYNC_STAT3_LBN 19\n+#define\tFRF_AB_XX_SYNC_STAT3_WIDTH 1\n+#define\tFRF_AB_XX_SYNC_STAT2_LBN 18\n+#define\tFRF_AB_XX_SYNC_STAT2_WIDTH 1\n+#define\tFRF_AB_XX_SYNC_STAT1_LBN 17\n+#define\tFRF_AB_XX_SYNC_STAT1_WIDTH 1\n+#define\tFRF_AB_XX_SYNC_STAT0_LBN 16\n+#define\tFRF_AB_XX_SYNC_STAT0_WIDTH 1\n+#define\tFRF_AB_XX_COMMA_DET_CH3_LBN 15\n+#define\tFRF_AB_XX_COMMA_DET_CH3_WIDTH 1\n+#define\tFRF_AB_XX_COMMA_DET_CH2_LBN 14\n+#define\tFRF_AB_XX_COMMA_DET_CH2_WIDTH 1\n+#define\tFRF_AB_XX_COMMA_DET_CH1_LBN 13\n+#define\tFRF_AB_XX_COMMA_DET_CH1_WIDTH 1\n+#define\tFRF_AB_XX_COMMA_DET_CH0_LBN 12\n+#define\tFRF_AB_XX_COMMA_DET_CH0_WIDTH 1\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH3_LBN 11\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH2_LBN 10\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH1_LBN 9\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH0_LBN 8\n+#define\tFRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1\n+#define\tFRF_AB_XX_CHAR_ERR_CH3_LBN 7\n+#define\tFRF_AB_XX_CHAR_ERR_CH3_WIDTH 1\n+#define\tFRF_AB_XX_CHAR_ERR_CH2_LBN 6\n+#define\tFRF_AB_XX_CHAR_ERR_CH2_WIDTH 1\n+#define\tFRF_AB_XX_CHAR_ERR_CH1_LBN 5\n+#define\tFRF_AB_XX_CHAR_ERR_CH1_WIDTH 1\n+#define\tFRF_AB_XX_CHAR_ERR_CH0_LBN 4\n+#define\tFRF_AB_XX_CHAR_ERR_CH0_WIDTH 1\n+#define\tFRF_AB_XX_DISPERR_CH3_LBN 3\n+#define\tFRF_AB_XX_DISPERR_CH3_WIDTH 1\n+#define\tFRF_AB_XX_DISPERR_CH2_LBN 2\n+#define\tFRF_AB_XX_DISPERR_CH2_WIDTH 1\n+#define\tFRF_AB_XX_DISPERR_CH1_LBN 1\n+#define\tFRF_AB_XX_DISPERR_CH1_WIDTH 1\n+#define\tFRF_AB_XX_DISPERR_CH0_LBN 0\n+#define\tFRF_AB_XX_DISPERR_CH0_WIDTH 1\n+\n+\n+/*\n+ * FR_AA_RX_DESC_PTR_TBL_KER(128bit):\n+ * Receive descriptor pointer table\n+ */\n+#define\tFR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_RX_DESC_PTR_TBL_KER_STEP 16\n+#define\tFR_AA_RX_DESC_PTR_TBL_KER_ROWS 4\n+/*\n+ * FR_AZ_RX_DESC_PTR_TBL(128bit):\n+ * Receive descriptor pointer table\n+ */\n+#define\tFR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000\n+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_RX_DESC_PTR_TBL_STEP 16\n+#define\tFR_CZ_RX_DESC_PTR_TBL_ROWS 1024\n+#define\tFR_AB_RX_DESC_PTR_TBL_ROWS 4096\n+\n+#define\tFRF_CZ_RX_HDR_SPLIT_LBN 90\n+#define\tFRF_CZ_RX_HDR_SPLIT_WIDTH 1\n+#define\tFRF_AZ_RX_RESET_LBN 89\n+#define\tFRF_AZ_RX_RESET_WIDTH 1\n+#define\tFRF_AZ_RX_ISCSI_DDIG_EN_LBN 88\n+#define\tFRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1\n+#define\tFRF_AZ_RX_ISCSI_HDIG_EN_LBN 87\n+#define\tFRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1\n+#define\tFRF_AZ_RX_DESC_PREF_ACT_LBN 86\n+#define\tFRF_AZ_RX_DESC_PREF_ACT_WIDTH 1\n+#define\tFRF_AZ_RX_DC_HW_RPTR_LBN 80\n+#define\tFRF_AZ_RX_DC_HW_RPTR_WIDTH 6\n+#define\tFRF_AZ_RX_DESCQ_HW_RPTR_LBN 68\n+#define\tFRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12\n+#define\tFRF_AZ_RX_DESCQ_SW_WPTR_LBN 56\n+#define\tFRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12\n+#define\tFRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36\n+#define\tFRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20\n+#define\tFRF_AZ_RX_DESCQ_EVQ_ID_LBN 24\n+#define\tFRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12\n+#define\tFRF_AZ_RX_DESCQ_OWNER_ID_LBN 10\n+#define\tFRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14\n+#define\tFRF_AZ_RX_DESCQ_LABEL_LBN 5\n+#define\tFRF_AZ_RX_DESCQ_LABEL_WIDTH 5\n+#define\tFRF_AZ_RX_DESCQ_SIZE_LBN 3\n+#define\tFRF_AZ_RX_DESCQ_SIZE_WIDTH 2\n+#define\tFFE_AZ_RX_DESCQ_SIZE_4K 3\n+#define\tFFE_AZ_RX_DESCQ_SIZE_2K 2\n+#define\tFFE_AZ_RX_DESCQ_SIZE_1K 1\n+#define\tFFE_AZ_RX_DESCQ_SIZE_512 0\n+#define\tFRF_AZ_RX_DESCQ_TYPE_LBN 2\n+#define\tFRF_AZ_RX_DESCQ_TYPE_WIDTH 1\n+#define\tFRF_AZ_RX_DESCQ_JUMBO_LBN 1\n+#define\tFRF_AZ_RX_DESCQ_JUMBO_WIDTH 1\n+#define\tFRF_AZ_RX_DESCQ_EN_LBN 0\n+#define\tFRF_AZ_RX_DESCQ_EN_WIDTH 1\n+\n+\n+/*\n+ * FR_AA_TX_DESC_PTR_TBL_KER(128bit):\n+ * Transmit descriptor pointer\n+ */\n+#define\tFR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_TX_DESC_PTR_TBL_KER_STEP 16\n+#define\tFR_AA_TX_DESC_PTR_TBL_KER_ROWS 8\n+/*\n+ * FR_AZ_TX_DESC_PTR_TBL(128bit):\n+ * Transmit descriptor pointer\n+ */\n+#define\tFR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000\n+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_TX_DESC_PTR_TBL_STEP 16\n+#define\tFR_AB_TX_DESC_PTR_TBL_ROWS 4096\n+#define\tFR_CZ_TX_DESC_PTR_TBL_ROWS 1024\n+\n+#define\tFRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94\n+#define\tFRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2\n+#define\tFRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93\n+#define\tFRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1\n+#define\tFRF_CZ_TX_DPT_IP_FILT_EN_LBN 92\n+#define\tFRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1\n+#define\tFRF_BZ_TX_NON_IP_DROP_DIS_LBN 91\n+#define\tFRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1\n+#define\tFRF_BZ_TX_IP_CHKSM_DIS_LBN 90\n+#define\tFRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1\n+#define\tFRF_BZ_TX_TCP_CHKSM_DIS_LBN 89\n+#define\tFRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1\n+#define\tFRF_AZ_TX_DESCQ_EN_LBN 88\n+#define\tFRF_AZ_TX_DESCQ_EN_WIDTH 1\n+#define\tFRF_AZ_TX_ISCSI_DDIG_EN_LBN 87\n+#define\tFRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1\n+#define\tFRF_AZ_TX_ISCSI_HDIG_EN_LBN 86\n+#define\tFRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1\n+#define\tFRF_AZ_TX_DC_HW_RPTR_LBN 80\n+#define\tFRF_AZ_TX_DC_HW_RPTR_WIDTH 6\n+#define\tFRF_AZ_TX_DESCQ_HW_RPTR_LBN 68\n+#define\tFRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12\n+#define\tFRF_AZ_TX_DESCQ_SW_WPTR_LBN 56\n+#define\tFRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12\n+#define\tFRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36\n+#define\tFRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20\n+#define\tFRF_AZ_TX_DESCQ_EVQ_ID_LBN 24\n+#define\tFRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12\n+#define\tFRF_AZ_TX_DESCQ_OWNER_ID_LBN 10\n+#define\tFRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14\n+#define\tFRF_AZ_TX_DESCQ_LABEL_LBN 5\n+#define\tFRF_AZ_TX_DESCQ_LABEL_WIDTH 5\n+#define\tFRF_AZ_TX_DESCQ_SIZE_LBN 3\n+#define\tFRF_AZ_TX_DESCQ_SIZE_WIDTH 2\n+#define\tFFE_AZ_TX_DESCQ_SIZE_4K 3\n+#define\tFFE_AZ_TX_DESCQ_SIZE_2K 2\n+#define\tFFE_AZ_TX_DESCQ_SIZE_1K 1\n+#define\tFFE_AZ_TX_DESCQ_SIZE_512 0\n+#define\tFRF_AZ_TX_DESCQ_TYPE_LBN 1\n+#define\tFRF_AZ_TX_DESCQ_TYPE_WIDTH 2\n+#define\tFRF_AZ_TX_DESCQ_FLUSH_LBN 0\n+#define\tFRF_AZ_TX_DESCQ_FLUSH_WIDTH 1\n+\n+\n+/*\n+ * FR_AA_EVQ_PTR_TBL_KER(128bit):\n+ * Event queue pointer table\n+ */\n+#define\tFR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_EVQ_PTR_TBL_KER_STEP 16\n+#define\tFR_AA_EVQ_PTR_TBL_KER_ROWS 4\n+/*\n+ * FR_AZ_EVQ_PTR_TBL(128bit):\n+ * Event queue pointer table\n+ */\n+#define\tFR_AZ_EVQ_PTR_TBL_OFST 0x00f60000\n+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_EVQ_PTR_TBL_STEP 16\n+#define\tFR_CZ_EVQ_PTR_TBL_ROWS 1024\n+#define\tFR_AB_EVQ_PTR_TBL_ROWS 4096\n+\n+#define\tFRF_BZ_EVQ_RPTR_IGN_LBN 40\n+#define\tFRF_BZ_EVQ_RPTR_IGN_WIDTH 1\n+#define\tFRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39\n+#define\tFRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1\n+#define\tFRF_AZ_EVQ_NXT_WPTR_LBN 24\n+#define\tFRF_AZ_EVQ_NXT_WPTR_WIDTH 15\n+#define\tFRF_AZ_EVQ_EN_LBN 23\n+#define\tFRF_AZ_EVQ_EN_WIDTH 1\n+#define\tFRF_AZ_EVQ_SIZE_LBN 20\n+#define\tFRF_AZ_EVQ_SIZE_WIDTH 3\n+#define\tFFE_AZ_EVQ_SIZE_32K 6\n+#define\tFFE_AZ_EVQ_SIZE_16K 5\n+#define\tFFE_AZ_EVQ_SIZE_8K 4\n+#define\tFFE_AZ_EVQ_SIZE_4K 3\n+#define\tFFE_AZ_EVQ_SIZE_2K 2\n+#define\tFFE_AZ_EVQ_SIZE_1K 1\n+#define\tFFE_AZ_EVQ_SIZE_512 0\n+#define\tFRF_AZ_EVQ_BUF_BASE_ID_LBN 0\n+#define\tFRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20\n+\n+\n+/*\n+ * FR_AA_BUF_HALF_TBL_KER(64bit):\n+ * Buffer table in half buffer table mode direct access by driver\n+ */\n+#define\tFR_AA_BUF_HALF_TBL_KER_OFST 0x00018000\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_BUF_HALF_TBL_KER_STEP 8\n+#define\tFR_AA_BUF_HALF_TBL_KER_ROWS 4096\n+/*\n+ * FR_AZ_BUF_HALF_TBL(64bit):\n+ * Buffer table in half buffer table mode direct access by driver\n+ */\n+#define\tFR_AZ_BUF_HALF_TBL_OFST 0x00800000\n+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_BUF_HALF_TBL_STEP 8\n+#define\tFR_CZ_BUF_HALF_TBL_ROWS 147456\n+#define\tFR_AB_BUF_HALF_TBL_ROWS 524288\n+\n+#define\tFRF_AZ_BUF_ADR_HBUF_ODD_LBN 44\n+#define\tFRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20\n+#define\tFRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32\n+#define\tFRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12\n+#define\tFRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12\n+#define\tFRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20\n+#define\tFRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0\n+#define\tFRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12\n+\n+\n+/*\n+ * FR_AA_BUF_FULL_TBL_KER(64bit):\n+ * Buffer table in full buffer table mode direct access by driver\n+ */\n+#define\tFR_AA_BUF_FULL_TBL_KER_OFST 0x00018000\n+/* falcona0=net_func_bar2 */\n+#define\tFR_AA_BUF_FULL_TBL_KER_STEP 8\n+#define\tFR_AA_BUF_FULL_TBL_KER_ROWS 4096\n+/*\n+ * FR_AZ_BUF_FULL_TBL(64bit):\n+ * Buffer table in full buffer table mode direct access by driver\n+ */\n+#define\tFR_AZ_BUF_FULL_TBL_OFST 0x00800000\n+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_BUF_FULL_TBL_STEP 8\n+\n+#define\tFR_CZ_BUF_FULL_TBL_ROWS 147456\n+#define\tFR_AB_BUF_FULL_TBL_ROWS 917504\n+\n+#define\tFRF_AZ_BUF_FULL_UNUSED_LBN 51\n+#define\tFRF_AZ_BUF_FULL_UNUSED_WIDTH 13\n+#define\tFRF_AZ_IP_DAT_BUF_SIZE_LBN 50\n+#define\tFRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1\n+#define\tFRF_AZ_BUF_ADR_REGION_LBN 48\n+#define\tFRF_AZ_BUF_ADR_REGION_WIDTH 2\n+#define\tFFE_AZ_BUF_ADR_REGN3 3\n+#define\tFFE_AZ_BUF_ADR_REGN2 2\n+#define\tFFE_AZ_BUF_ADR_REGN1 1\n+#define\tFFE_AZ_BUF_ADR_REGN0 0\n+#define\tFRF_AZ_BUF_ADR_FBUF_LBN 14\n+#define\tFRF_AZ_BUF_ADR_FBUF_WIDTH 34\n+#define\tFRF_AZ_BUF_ADR_FBUF_DW0_LBN 14\n+#define\tFRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32\n+#define\tFRF_AZ_BUF_ADR_FBUF_DW1_LBN 46\n+#define\tFRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2\n+#define\tFRF_AZ_BUF_OWNER_ID_FBUF_LBN 0\n+#define\tFRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14\n+\n+\n+/*\n+ * FR_AZ_RX_FILTER_TBL0(128bit):\n+ * TCP/IPv4 Receive filter table\n+ */\n+#define\tFR_AZ_RX_FILTER_TBL0_OFST 0x00f00000\n+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_RX_FILTER_TBL0_STEP 32\n+#define\tFR_AZ_RX_FILTER_TBL0_ROWS 8192\n+/*\n+ * FR_AB_RX_FILTER_TBL1(128bit):\n+ * TCP/IPv4 Receive filter table\n+ */\n+#define\tFR_AB_RX_FILTER_TBL1_OFST 0x00f00010\n+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AB_RX_FILTER_TBL1_STEP 32\n+#define\tFR_AB_RX_FILTER_TBL1_ROWS 8192\n+\n+#define\tFRF_BZ_RSS_EN_LBN 110\n+#define\tFRF_BZ_RSS_EN_WIDTH 1\n+#define\tFRF_BZ_SCATTER_EN_LBN 109\n+#define\tFRF_BZ_SCATTER_EN_WIDTH 1\n+#define\tFRF_AZ_TCP_UDP_LBN 108\n+#define\tFRF_AZ_TCP_UDP_WIDTH 1\n+#define\tFRF_AZ_RXQ_ID_LBN 96\n+#define\tFRF_AZ_RXQ_ID_WIDTH 12\n+#define\tFRF_AZ_DEST_IP_LBN 64\n+#define\tFRF_AZ_DEST_IP_WIDTH 32\n+#define\tFRF_AZ_DEST_PORT_TCP_LBN 48\n+#define\tFRF_AZ_DEST_PORT_TCP_WIDTH 16\n+#define\tFRF_AZ_SRC_IP_LBN 16\n+#define\tFRF_AZ_SRC_IP_WIDTH 32\n+#define\tFRF_AZ_SRC_TCP_DEST_UDP_LBN 0\n+#define\tFRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16\n+\n+\n+/*\n+ * FR_CZ_RX_MAC_FILTER_TBL0(128bit):\n+ * Receive Ethernet filter table\n+ */\n+#define\tFR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010\n+/* sienaa0=net_func_bar2 */\n+#define\tFR_CZ_RX_MAC_FILTER_TBL0_STEP 32\n+#define\tFR_CZ_RX_MAC_FILTER_TBL0_ROWS 512\n+\n+#define\tFRF_CZ_RMFT_RSS_EN_LBN 75\n+#define\tFRF_CZ_RMFT_RSS_EN_WIDTH 1\n+#define\tFRF_CZ_RMFT_SCATTER_EN_LBN 74\n+#define\tFRF_CZ_RMFT_SCATTER_EN_WIDTH 1\n+#define\tFRF_CZ_RMFT_IP_OVERRIDE_LBN 73\n+#define\tFRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1\n+#define\tFRF_CZ_RMFT_RXQ_ID_LBN 61\n+#define\tFRF_CZ_RMFT_RXQ_ID_WIDTH 12\n+#define\tFRF_CZ_RMFT_WILDCARD_MATCH_LBN 60\n+#define\tFRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1\n+#define\tFRF_CZ_RMFT_DEST_MAC_LBN 12\n+#define\tFRF_CZ_RMFT_DEST_MAC_WIDTH 48\n+#define\tFRF_CZ_RMFT_DEST_MAC_DW0_LBN 12\n+#define\tFRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32\n+#define\tFRF_CZ_RMFT_DEST_MAC_DW1_LBN 44\n+#define\tFRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16\n+#define\tFRF_CZ_RMFT_VLAN_ID_LBN 0\n+#define\tFRF_CZ_RMFT_VLAN_ID_WIDTH 12\n+\n+\n+/*\n+ * FR_AZ_TIMER_TBL(128bit):\n+ * Timer table\n+ */\n+#define\tFR_AZ_TIMER_TBL_OFST 0x00f70000\n+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_TIMER_TBL_STEP 16\n+#define\tFR_CZ_TIMER_TBL_ROWS 1024\n+#define\tFR_AB_TIMER_TBL_ROWS 4096\n+\n+#define\tFRF_CZ_TIMER_Q_EN_LBN 33\n+#define\tFRF_CZ_TIMER_Q_EN_WIDTH 1\n+#define\tFRF_CZ_INT_ARMD_LBN 32\n+#define\tFRF_CZ_INT_ARMD_WIDTH 1\n+#define\tFRF_CZ_INT_PEND_LBN 31\n+#define\tFRF_CZ_INT_PEND_WIDTH 1\n+#define\tFRF_CZ_HOST_NOTIFY_MODE_LBN 30\n+#define\tFRF_CZ_HOST_NOTIFY_MODE_WIDTH 1\n+#define\tFRF_CZ_RELOAD_TIMER_VAL_LBN 16\n+#define\tFRF_CZ_RELOAD_TIMER_VAL_WIDTH 14\n+#define\tFRF_CZ_TIMER_MODE_LBN 14\n+#define\tFRF_CZ_TIMER_MODE_WIDTH 2\n+#define\tFFE_CZ_TIMER_MODE_INT_HLDOFF 3\n+#define\tFFE_CZ_TIMER_MODE_TRIG_START 2\n+#define\tFFE_CZ_TIMER_MODE_IMMED_START 1\n+#define\tFFE_CZ_TIMER_MODE_DIS 0\n+#define\tFRF_AB_TIMER_MODE_LBN 12\n+#define\tFRF_AB_TIMER_MODE_WIDTH 2\n+#define\tFFE_AB_TIMER_MODE_INT_HLDOFF 2\n+#define\tFFE_AB_TIMER_MODE_TRIG_START 2\n+#define\tFFE_AB_TIMER_MODE_IMMED_START 1\n+#define\tFFE_AB_TIMER_MODE_DIS 0\n+#define\tFRF_CZ_TIMER_VAL_LBN 0\n+#define\tFRF_CZ_TIMER_VAL_WIDTH 14\n+#define\tFRF_AB_TIMER_VAL_LBN 0\n+#define\tFRF_AB_TIMER_VAL_WIDTH 12\n+\n+\n+/*\n+ * FR_BZ_TX_PACE_TBL(128bit):\n+ * Transmit pacing table\n+ */\n+#define\tFR_BZ_TX_PACE_TBL_OFST 0x00f80000\n+/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */\n+#define\tFR_AZ_TX_PACE_TBL_STEP 16\n+#define\tFR_CZ_TX_PACE_TBL_ROWS 1024\n+#define\tFR_BB_TX_PACE_TBL_ROWS 4096\n+/*\n+ * FR_AA_TX_PACE_TBL(128bit):\n+ * Transmit pacing table\n+ */\n+#define\tFR_AA_TX_PACE_TBL_OFST 0x00f80040\n+/* falcona0=char_func_bar0 */\n+/* FR_AZ_TX_PACE_TBL_STEP 16 */\n+#define\tFR_AA_TX_PACE_TBL_ROWS 4092\n+\n+#define\tFRF_AZ_TX_PACE_LBN 0\n+#define\tFRF_AZ_TX_PACE_WIDTH 5\n+\n+\n+/*\n+ * FR_BZ_RX_INDIRECTION_TBL(7bit):\n+ * RX Indirection Table\n+ */\n+#define\tFR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000\n+/* falconb0,sienaa0=net_func_bar2 */\n+#define\tFR_BZ_RX_INDIRECTION_TBL_STEP 16\n+#define\tFR_BZ_RX_INDIRECTION_TBL_ROWS 128\n+\n+#define\tFRF_BZ_IT_QUEUE_LBN 0\n+#define\tFRF_BZ_IT_QUEUE_WIDTH 6\n+\n+\n+/*\n+ * FR_CZ_TX_FILTER_TBL0(128bit):\n+ * TCP/IPv4 Transmit filter table\n+ */\n+#define\tFR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000\n+/* sienaa0=net_func_bar2 */\n+#define\tFR_CZ_TX_FILTER_TBL0_STEP 16\n+#define\tFR_CZ_TX_FILTER_TBL0_ROWS 8192\n+\n+#define\tFRF_CZ_TIFT_TCP_UDP_LBN 108\n+#define\tFRF_CZ_TIFT_TCP_UDP_WIDTH 1\n+#define\tFRF_CZ_TIFT_TXQ_ID_LBN 96\n+#define\tFRF_CZ_TIFT_TXQ_ID_WIDTH 12\n+#define\tFRF_CZ_TIFT_DEST_IP_LBN 64\n+#define\tFRF_CZ_TIFT_DEST_IP_WIDTH 32\n+#define\tFRF_CZ_TIFT_DEST_PORT_TCP_LBN 48\n+#define\tFRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16\n+#define\tFRF_CZ_TIFT_SRC_IP_LBN 16\n+#define\tFRF_CZ_TIFT_SRC_IP_WIDTH 32\n+#define\tFRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0\n+#define\tFRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16\n+\n+\n+/*\n+ * FR_CZ_TX_MAC_FILTER_TBL0(128bit):\n+ * Transmit Ethernet filter table\n+ */\n+#define\tFR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000\n+/* sienaa0=net_func_bar2 */\n+#define\tFR_CZ_TX_MAC_FILTER_TBL0_STEP 16\n+#define\tFR_CZ_TX_MAC_FILTER_TBL0_ROWS 512\n+\n+#define\tFRF_CZ_TMFT_TXQ_ID_LBN 61\n+#define\tFRF_CZ_TMFT_TXQ_ID_WIDTH 12\n+#define\tFRF_CZ_TMFT_WILDCARD_MATCH_LBN 60\n+#define\tFRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1\n+#define\tFRF_CZ_TMFT_SRC_MAC_LBN 12\n+#define\tFRF_CZ_TMFT_SRC_MAC_WIDTH 48\n+#define\tFRF_CZ_TMFT_SRC_MAC_DW0_LBN 12\n+#define\tFRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32\n+#define\tFRF_CZ_TMFT_SRC_MAC_DW1_LBN 44\n+#define\tFRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16\n+#define\tFRF_CZ_TMFT_VLAN_ID_LBN 0\n+#define\tFRF_CZ_TMFT_VLAN_ID_WIDTH 12\n+\n+\n+/*\n+ * FR_CZ_MC_TREG_SMEM(32bit):\n+ * MC Shared Memory\n+ */\n+#define\tFR_CZ_MC_TREG_SMEM_OFST 0x00ff0000\n+/* sienaa0=net_func_bar2 */\n+#define\tFR_CZ_MC_TREG_SMEM_STEP 4\n+#define\tFR_CZ_MC_TREG_SMEM_ROWS 512\n+\n+#define\tFRF_CZ_MC_TREG_SMEM_ROW_LBN 0\n+#define\tFRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32\n+\n+\n+/*\n+ * FR_BB_MSIX_VECTOR_TABLE(128bit):\n+ * MSIX Vector Table\n+ */\n+#define\tFR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000\n+/* falconb0=net_func_bar2 */\n+#define\tFR_BZ_MSIX_VECTOR_TABLE_STEP 16\n+#define\tFR_BB_MSIX_VECTOR_TABLE_ROWS 64\n+/*\n+ * FR_CZ_MSIX_VECTOR_TABLE(128bit):\n+ * MSIX Vector Table\n+ */\n+#define\tFR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000\n+/* sienaa0=pci_f0_bar4 */\n+/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */\n+#define\tFR_CZ_MSIX_VECTOR_TABLE_ROWS 1024\n+\n+#define\tFRF_BZ_MSIX_VECTOR_RESERVED_LBN 97\n+#define\tFRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31\n+#define\tFRF_BZ_MSIX_VECTOR_MASK_LBN 96\n+#define\tFRF_BZ_MSIX_VECTOR_MASK_WIDTH 1\n+#define\tFRF_BZ_MSIX_MESSAGE_DATA_LBN 64\n+#define\tFRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32\n+#define\tFRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32\n+#define\tFRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32\n+#define\tFRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0\n+#define\tFRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32\n+\n+\n+/*\n+ * FR_BB_MSIX_PBA_TABLE(32bit):\n+ * MSIX Pending Bit Array\n+ */\n+#define\tFR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000\n+/* falconb0=net_func_bar2 */\n+#define\tFR_BZ_MSIX_PBA_TABLE_STEP 4\n+#define\tFR_BB_MSIX_PBA_TABLE_ROWS 2\n+/*\n+ * FR_CZ_MSIX_PBA_TABLE(32bit):\n+ * MSIX Pending Bit Array\n+ */\n+#define\tFR_CZ_MSIX_PBA_TABLE_OFST 0x00008000\n+/* sienaa0=pci_f0_bar4 */\n+/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */\n+#define\tFR_CZ_MSIX_PBA_TABLE_ROWS 32\n+\n+#define\tFRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0\n+#define\tFRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32\n+\n+\n+/*\n+ * FR_AZ_SRM_DBG_REG(64bit):\n+ * SRAM debug access\n+ */\n+#define\tFR_AZ_SRM_DBG_REG_OFST 0x03000000\n+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */\n+#define\tFR_AZ_SRM_DBG_REG_STEP 8\n+\n+#define\tFR_CZ_SRM_DBG_REG_ROWS 262144\n+#define\tFR_AB_SRM_DBG_REG_ROWS 2097152\n+\n+#define\tFRF_AZ_SRM_DBG_LBN 0\n+#define\tFRF_AZ_SRM_DBG_WIDTH 64\n+#define\tFRF_AZ_SRM_DBG_DW0_LBN 0\n+#define\tFRF_AZ_SRM_DBG_DW0_WIDTH 32\n+#define\tFRF_AZ_SRM_DBG_DW1_LBN 32\n+#define\tFRF_AZ_SRM_DBG_DW1_WIDTH 32\n+\n+\n+/*\n+ * FR_AA_INT_ACK_CHAR(32bit):\n+ * CHAR interrupt acknowledge register\n+ */\n+#define\tFR_AA_INT_ACK_CHAR_OFST 0x00000060\n+/* falcona0=char_func_bar0 */\n+\n+#define\tFRF_AA_INT_ACK_CHAR_FIELD_LBN 0\n+#define\tFRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32\n+\n+\n+/* FS_DRIVER_EV */\n+#define\tFSF_AZ_DRIVER_EV_SUBCODE_LBN 56\n+#define\tFSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4\n+#define\tFSE_AZ_TX_DSC_ERROR_EV 15\n+#define\tFSE_AZ_RX_DSC_ERROR_EV 14\n+#define\tFSE_AZ_RX_RECOVER_EV 11\n+#define\tFSE_AZ_TIMER_EV 10\n+#define\tFSE_AZ_TX_PKT_NON_TCP_UDP 9\n+#define\tFSE_AZ_WAKE_UP_EV 6\n+#define\tFSE_AZ_SRM_UPD_DONE_EV 5\n+#define\tFSE_AZ_EVQ_NOT_EN_EV 3\n+#define\tFSE_AZ_EVQ_INIT_DONE_EV 2\n+#define\tFSE_AZ_RX_DESCQ_FLS_DONE_EV 1\n+#define\tFSE_AZ_TX_DESCQ_FLS_DONE_EV 0\n+#define\tFSF_AZ_DRIVER_EV_SUBDATA_LBN 0\n+#define\tFSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14\n+\n+\n+/* FS_EVENT_ENTRY */\n+#define\tFSF_AZ_EV_CODE_LBN 60\n+#define\tFSF_AZ_EV_CODE_WIDTH 4\n+#define\tFSE_AZ_EV_CODE_USER_EV 8\n+#define\tFSE_AZ_EV_CODE_DRV_GEN_EV 7\n+#define\tFSE_AZ_EV_CODE_GLOBAL_EV 6\n+#define\tFSE_AZ_EV_CODE_DRIVER_EV 5\n+#define\tFSE_AZ_EV_CODE_TX_EV 2\n+#define\tFSE_AZ_EV_CODE_RX_EV 0\n+#define\tFSF_AZ_EV_DATA_LBN 0\n+#define\tFSF_AZ_EV_DATA_WIDTH 60\n+#define\tFSF_AZ_EV_DATA_DW0_LBN 0\n+#define\tFSF_AZ_EV_DATA_DW0_WIDTH 32\n+#define\tFSF_AZ_EV_DATA_DW1_LBN 32\n+#define\tFSF_AZ_EV_DATA_DW1_WIDTH 28\n+\n+\n+/* FS_GLOBAL_EV */\n+#define\tFSF_AA_GLB_EV_RX_RECOVERY_LBN 12\n+#define\tFSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1\n+#define\tFSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11\n+#define\tFSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1\n+#define\tFSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10\n+#define\tFSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1\n+#define\tFSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9\n+#define\tFSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1\n+#define\tFSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7\n+#define\tFSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1\n+\n+\n+/* FS_RX_EV */\n+#define\tFSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58\n+#define\tFSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1\n+#define\tFSF_CZ_RX_EV_IPV6_PKT_LBN 57\n+#define\tFSF_CZ_RX_EV_IPV6_PKT_WIDTH 1\n+#define\tFSF_AZ_RX_EV_PKT_OK_LBN 56\n+#define\tFSF_AZ_RX_EV_PKT_OK_WIDTH 1\n+#define\tFSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55\n+#define\tFSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54\n+#define\tFSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53\n+#define\tFSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52\n+#define\tFSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51\n+#define\tFSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50\n+#define\tFSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_FRM_TRUNC_LBN 49\n+#define\tFSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1\n+#define\tFSF_AZ_RX_EV_TOBE_DISC_LBN 47\n+#define\tFSF_AZ_RX_EV_TOBE_DISC_WIDTH 1\n+#define\tFSF_AZ_RX_EV_PKT_TYPE_LBN 44\n+#define\tFSF_AZ_RX_EV_PKT_TYPE_WIDTH 3\n+#define\tFSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5\n+#define\tFSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4\n+#define\tFSE_AZ_RX_EV_PKT_TYPE_VLAN 3\n+#define\tFSE_AZ_RX_EV_PKT_TYPE_JUMBO 2\n+#define\tFSE_AZ_RX_EV_PKT_TYPE_LLC 1\n+#define\tFSE_AZ_RX_EV_PKT_TYPE_ETH 0\n+#define\tFSF_AZ_RX_EV_HDR_TYPE_LBN 42\n+#define\tFSF_AZ_RX_EV_HDR_TYPE_WIDTH 2\n+#define\tFSE_AZ_RX_EV_HDR_TYPE_OTHER 3\n+#define\tFSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2\n+#define\tFSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2\n+#define\tFSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1\n+#define\tFSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1\n+#define\tFSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0\n+#define\tFSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0\n+#define\tFSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41\n+#define\tFSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1\n+#define\tFSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40\n+#define\tFSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1\n+#define\tFSF_AZ_RX_EV_MCAST_PKT_LBN 39\n+#define\tFSF_AZ_RX_EV_MCAST_PKT_WIDTH 1\n+#define\tFSF_AA_RX_EV_RECOVERY_FLAG_LBN 37\n+#define\tFSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1\n+#define\tFSF_AZ_RX_EV_Q_LABEL_LBN 32\n+#define\tFSF_AZ_RX_EV_Q_LABEL_WIDTH 5\n+#define\tFSF_AZ_RX_EV_JUMBO_CONT_LBN 31\n+#define\tFSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1\n+#define\tFSF_AZ_RX_EV_PORT_LBN 30\n+#define\tFSF_AZ_RX_EV_PORT_WIDTH 1\n+#define\tFSF_AZ_RX_EV_BYTE_CNT_LBN 16\n+#define\tFSF_AZ_RX_EV_BYTE_CNT_WIDTH 14\n+#define\tFSF_AZ_RX_EV_SOP_LBN 15\n+#define\tFSF_AZ_RX_EV_SOP_WIDTH 1\n+#define\tFSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14\n+#define\tFSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1\n+#define\tFSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13\n+#define\tFSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12\n+#define\tFSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1\n+#define\tFSF_AZ_RX_EV_DESC_PTR_LBN 0\n+#define\tFSF_AZ_RX_EV_DESC_PTR_WIDTH 12\n+\n+\n+/* FS_RX_KER_DESC */\n+#define\tFSF_AZ_RX_KER_BUF_SIZE_LBN 48\n+#define\tFSF_AZ_RX_KER_BUF_SIZE_WIDTH 14\n+#define\tFSF_AZ_RX_KER_BUF_REGION_LBN 46\n+#define\tFSF_AZ_RX_KER_BUF_REGION_WIDTH 2\n+#define\tFSF_AZ_RX_KER_BUF_ADDR_LBN 0\n+#define\tFSF_AZ_RX_KER_BUF_ADDR_WIDTH 46\n+#define\tFSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0\n+#define\tFSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32\n+#define\tFSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32\n+#define\tFSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14\n+\n+\n+/* FS_RX_USER_DESC */\n+#define\tFSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20\n+#define\tFSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12\n+#define\tFSF_AZ_RX_USER_BUF_ID_LBN 0\n+#define\tFSF_AZ_RX_USER_BUF_ID_WIDTH 20\n+\n+\n+/* FS_TX_EV */\n+#define\tFSF_AZ_TX_EV_PKT_ERR_LBN 38\n+#define\tFSF_AZ_TX_EV_PKT_ERR_WIDTH 1\n+#define\tFSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37\n+#define\tFSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1\n+#define\tFSF_AZ_TX_EV_Q_LABEL_LBN 32\n+#define\tFSF_AZ_TX_EV_Q_LABEL_WIDTH 5\n+#define\tFSF_AZ_TX_EV_PORT_LBN 16\n+#define\tFSF_AZ_TX_EV_PORT_WIDTH 1\n+#define\tFSF_AZ_TX_EV_WQ_FF_FULL_LBN 15\n+#define\tFSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1\n+#define\tFSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14\n+#define\tFSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1\n+#define\tFSF_AZ_TX_EV_COMP_LBN 12\n+#define\tFSF_AZ_TX_EV_COMP_WIDTH 1\n+#define\tFSF_AZ_TX_EV_DESC_PTR_LBN 0\n+#define\tFSF_AZ_TX_EV_DESC_PTR_WIDTH 12\n+\n+\n+/* FS_TX_KER_DESC */\n+#define\tFSF_AZ_TX_KER_CONT_LBN 62\n+#define\tFSF_AZ_TX_KER_CONT_WIDTH 1\n+#define\tFSF_AZ_TX_KER_BYTE_COUNT_LBN 48\n+#define\tFSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14\n+#define\tFSF_AZ_TX_KER_BUF_REGION_LBN 46\n+#define\tFSF_AZ_TX_KER_BUF_REGION_WIDTH 2\n+#define\tFSF_AZ_TX_KER_BUF_ADDR_LBN 0\n+#define\tFSF_AZ_TX_KER_BUF_ADDR_WIDTH 46\n+#define\tFSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0\n+#define\tFSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32\n+#define\tFSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32\n+#define\tFSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14\n+\n+\n+/* FS_TX_USER_DESC */\n+#define\tFSF_AZ_TX_USER_SW_EV_EN_LBN 48\n+#define\tFSF_AZ_TX_USER_SW_EV_EN_WIDTH 1\n+#define\tFSF_AZ_TX_USER_CONT_LBN 46\n+#define\tFSF_AZ_TX_USER_CONT_WIDTH 1\n+#define\tFSF_AZ_TX_USER_BYTE_CNT_LBN 33\n+#define\tFSF_AZ_TX_USER_BYTE_CNT_WIDTH 13\n+#define\tFSF_AZ_TX_USER_BUF_ID_LBN 13\n+#define\tFSF_AZ_TX_USER_BUF_ID_WIDTH 20\n+#define\tFSF_AZ_TX_USER_BYTE_OFS_LBN 0\n+#define\tFSF_AZ_TX_USER_BYTE_OFS_WIDTH 13\n+\n+\n+/* FS_USER_EV */\n+#define\tFSF_CZ_USER_QID_LBN 32\n+#define\tFSF_CZ_USER_QID_WIDTH 10\n+#define\tFSF_CZ_USER_EV_REG_VALUE_LBN 0\n+#define\tFSF_CZ_USER_EV_REG_VALUE_WIDTH 32\n+\n+\n+/* FS_NET_IVEC */\n+#define\tFSF_AZ_NET_IVEC_FATAL_INT_LBN 64\n+#define\tFSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1\n+#define\tFSF_AZ_NET_IVEC_INT_Q_LBN 40\n+#define\tFSF_AZ_NET_IVEC_INT_Q_WIDTH 4\n+#define\tFSF_AZ_NET_IVEC_INT_FLAG_LBN 32\n+#define\tFSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1\n+#define\tFSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1\n+#define\tFSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1\n+#define\tFSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0\n+#define\tFSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1\n+\n+\n+/* DRIVER_EV */\n+/* Sub-fields of an RX flush completion event */\n+#define\tFSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12\n+#define\tFSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1\n+#define\tFSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0\n+#define\tFSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12\n+\n+\n+\n+/**************************************************************************\n+ *\n+ * Falcon non-volatile configuration\n+ *\n+ **************************************************************************\n+ */\n+\n+\n+#define\tFR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST\n+\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+\n+\n+\n+#endif /* _SYS_EFX_REGS_H */\ndiff --git a/drivers/net/sfc/efx/base/efx_regs_pci.h b/drivers/net/sfc/efx/base/efx_regs_pci.h\nnew file mode 100644\nindex 0000000..f90f956\n--- /dev/null\n+++ b/drivers/net/sfc/efx/base/efx_regs_pci.h\n@@ -0,0 +1,2356 @@\n+/*\n+ * Copyright (c) 2007-2016 Solarflare Communications Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *    this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ *    this list of conditions and the following disclaimer in the documentation\n+ *    and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\n+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\n+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * The views and conclusions contained in the software and documentation are\n+ * those of the authors and should not be interpreted as representing official\n+ * policies, either expressed or implied, of the FreeBSD Project.\n+ */\n+\n+#ifndef\t_SYS_EFX_REGS_PCI_H\n+#define\t_SYS_EFX_REGS_PCI_H\n+\n+#ifdef\t__cplusplus\n+extern \"C\" {\n+#endif\n+\n+/*\n+ * PC_VEND_ID_REG(16bit):\n+ * Vendor ID register\n+ */\n+\n+#define\tPCR_AZ_VEND_ID_REG 0x00000000\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_VEND_ID_LBN 0\n+#define\tPCRF_AZ_VEND_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_DEV_ID_REG(16bit):\n+ * Device ID register\n+ */\n+\n+#define\tPCR_AZ_DEV_ID_REG 0x00000002\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_DEV_ID_LBN 0\n+#define\tPCRF_AZ_DEV_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_CMD_REG(16bit):\n+ * Command register\n+ */\n+\n+#define\tPCR_AZ_CMD_REG 0x00000004\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_INTX_DIS_LBN 10\n+#define\tPCRF_AZ_INTX_DIS_WIDTH 1\n+#define\tPCRF_AZ_FB2B_EN_LBN 9\n+#define\tPCRF_AZ_FB2B_EN_WIDTH 1\n+#define\tPCRF_AZ_SERR_EN_LBN 8\n+#define\tPCRF_AZ_SERR_EN_WIDTH 1\n+#define\tPCRF_AZ_IDSEL_CTL_LBN 7\n+#define\tPCRF_AZ_IDSEL_CTL_WIDTH 1\n+#define\tPCRF_AZ_PERR_EN_LBN 6\n+#define\tPCRF_AZ_PERR_EN_WIDTH 1\n+#define\tPCRF_AZ_VGA_PAL_SNP_LBN 5\n+#define\tPCRF_AZ_VGA_PAL_SNP_WIDTH 1\n+#define\tPCRF_AZ_MWI_EN_LBN 4\n+#define\tPCRF_AZ_MWI_EN_WIDTH 1\n+#define\tPCRF_AZ_SPEC_CYC_LBN 3\n+#define\tPCRF_AZ_SPEC_CYC_WIDTH 1\n+#define\tPCRF_AZ_MST_EN_LBN 2\n+#define\tPCRF_AZ_MST_EN_WIDTH 1\n+#define\tPCRF_AZ_MEM_EN_LBN 1\n+#define\tPCRF_AZ_MEM_EN_WIDTH 1\n+#define\tPCRF_AZ_IO_EN_LBN 0\n+#define\tPCRF_AZ_IO_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_STAT_REG(16bit):\n+ * Status register\n+ */\n+\n+#define\tPCR_AZ_STAT_REG 0x00000006\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_DET_PERR_LBN 15\n+#define\tPCRF_AZ_DET_PERR_WIDTH 1\n+#define\tPCRF_AZ_SIG_SERR_LBN 14\n+#define\tPCRF_AZ_SIG_SERR_WIDTH 1\n+#define\tPCRF_AZ_GOT_MABRT_LBN 13\n+#define\tPCRF_AZ_GOT_MABRT_WIDTH 1\n+#define\tPCRF_AZ_GOT_TABRT_LBN 12\n+#define\tPCRF_AZ_GOT_TABRT_WIDTH 1\n+#define\tPCRF_AZ_SIG_TABRT_LBN 11\n+#define\tPCRF_AZ_SIG_TABRT_WIDTH 1\n+#define\tPCRF_AZ_DEVSEL_TIM_LBN 9\n+#define\tPCRF_AZ_DEVSEL_TIM_WIDTH 2\n+#define\tPCRF_AZ_MDAT_PERR_LBN 8\n+#define\tPCRF_AZ_MDAT_PERR_WIDTH 1\n+#define\tPCRF_AZ_FB2B_CAP_LBN 7\n+#define\tPCRF_AZ_FB2B_CAP_WIDTH 1\n+#define\tPCRF_AZ_66MHZ_CAP_LBN 5\n+#define\tPCRF_AZ_66MHZ_CAP_WIDTH 1\n+#define\tPCRF_AZ_CAP_LIST_LBN 4\n+#define\tPCRF_AZ_CAP_LIST_WIDTH 1\n+#define\tPCRF_AZ_INTX_STAT_LBN 3\n+#define\tPCRF_AZ_INTX_STAT_WIDTH 1\n+\n+\n+/*\n+ * PC_REV_ID_REG(8bit):\n+ * Class code & revision ID register\n+ */\n+\n+#define\tPCR_AZ_REV_ID_REG 0x00000008\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_REV_ID_LBN 0\n+#define\tPCRF_AZ_REV_ID_WIDTH 8\n+\n+\n+/*\n+ * PC_CC_REG(24bit):\n+ * Class code register\n+ */\n+\n+#define\tPCR_AZ_CC_REG 0x00000009\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_BASE_CC_LBN 16\n+#define\tPCRF_AZ_BASE_CC_WIDTH 8\n+#define\tPCRF_AZ_SUB_CC_LBN 8\n+#define\tPCRF_AZ_SUB_CC_WIDTH 8\n+#define\tPCRF_AZ_PROG_IF_LBN 0\n+#define\tPCRF_AZ_PROG_IF_WIDTH 8\n+\n+\n+/*\n+ * PC_CACHE_LSIZE_REG(8bit):\n+ * Cache line size\n+ */\n+\n+#define\tPCR_AZ_CACHE_LSIZE_REG 0x0000000c\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_CACHE_LSIZE_LBN 0\n+#define\tPCRF_AZ_CACHE_LSIZE_WIDTH 8\n+\n+\n+/*\n+ * PC_MST_LAT_REG(8bit):\n+ * Master latency timer register\n+ */\n+\n+#define\tPCR_AZ_MST_LAT_REG 0x0000000d\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MST_LAT_LBN 0\n+#define\tPCRF_AZ_MST_LAT_WIDTH 8\n+\n+\n+/*\n+ * PC_HDR_TYPE_REG(8bit):\n+ * Header type register\n+ */\n+\n+#define\tPCR_AZ_HDR_TYPE_REG 0x0000000e\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MULT_FUNC_LBN 7\n+#define\tPCRF_AZ_MULT_FUNC_WIDTH 1\n+#define\tPCRF_AZ_TYPE_LBN 0\n+#define\tPCRF_AZ_TYPE_WIDTH 7\n+\n+\n+/*\n+ * PC_BIST_REG(8bit):\n+ * BIST register\n+ */\n+\n+#define\tPCR_AZ_BIST_REG 0x0000000f\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_BIST_LBN 0\n+#define\tPCRF_AZ_BIST_WIDTH 8\n+\n+\n+/*\n+ * PC_BAR0_REG(32bit):\n+ * Primary function base address register 0\n+ */\n+\n+#define\tPCR_AZ_BAR0_REG 0x00000010\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_BAR0_LBN 4\n+#define\tPCRF_AZ_BAR0_WIDTH 28\n+#define\tPCRF_AZ_BAR0_PREF_LBN 3\n+#define\tPCRF_AZ_BAR0_PREF_WIDTH 1\n+#define\tPCRF_AZ_BAR0_TYPE_LBN 1\n+#define\tPCRF_AZ_BAR0_TYPE_WIDTH 2\n+#define\tPCRF_AZ_BAR0_IOM_LBN 0\n+#define\tPCRF_AZ_BAR0_IOM_WIDTH 1\n+\n+\n+/*\n+ * PC_BAR1_REG(32bit):\n+ * Primary function base address register 1, BAR1 is not implemented so read only.\n+ */\n+\n+#define\tPCR_DZ_BAR1_REG 0x00000014\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_BAR1_LBN 0\n+#define\tPCRF_DZ_BAR1_WIDTH 32\n+\n+\n+/*\n+ * PC_BAR2_LO_REG(32bit):\n+ * Primary function base address register 2 low bits\n+ */\n+\n+#define\tPCR_AZ_BAR2_LO_REG 0x00000018\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_BAR2_LO_LBN 4\n+#define\tPCRF_AZ_BAR2_LO_WIDTH 28\n+#define\tPCRF_AZ_BAR2_PREF_LBN 3\n+#define\tPCRF_AZ_BAR2_PREF_WIDTH 1\n+#define\tPCRF_AZ_BAR2_TYPE_LBN 1\n+#define\tPCRF_AZ_BAR2_TYPE_WIDTH 2\n+#define\tPCRF_AZ_BAR2_IOM_LBN 0\n+#define\tPCRF_AZ_BAR2_IOM_WIDTH 1\n+\n+\n+/*\n+ * PC_BAR2_HI_REG(32bit):\n+ * Primary function base address register 2 high bits\n+ */\n+\n+#define\tPCR_AZ_BAR2_HI_REG 0x0000001c\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_BAR2_HI_LBN 0\n+#define\tPCRF_AZ_BAR2_HI_WIDTH 32\n+\n+\n+/*\n+ * PC_BAR4_LO_REG(32bit):\n+ * Primary function base address register 2 low bits\n+ */\n+\n+#define\tPCR_CZ_BAR4_LO_REG 0x00000020\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_BAR4_LO_LBN 4\n+#define\tPCRF_CZ_BAR4_LO_WIDTH 28\n+#define\tPCRF_CZ_BAR4_PREF_LBN 3\n+#define\tPCRF_CZ_BAR4_PREF_WIDTH 1\n+#define\tPCRF_CZ_BAR4_TYPE_LBN 1\n+#define\tPCRF_CZ_BAR4_TYPE_WIDTH 2\n+#define\tPCRF_CZ_BAR4_IOM_LBN 0\n+#define\tPCRF_CZ_BAR4_IOM_WIDTH 1\n+\n+\n+/*\n+ * PC_BAR4_HI_REG(32bit):\n+ * Primary function base address register 2 high bits\n+ */\n+\n+#define\tPCR_CZ_BAR4_HI_REG 0x00000024\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_BAR4_HI_LBN 0\n+#define\tPCRF_CZ_BAR4_HI_WIDTH 32\n+\n+\n+/*\n+ * PC_SS_VEND_ID_REG(16bit):\n+ * Sub-system vendor ID register\n+ */\n+\n+#define\tPCR_AZ_SS_VEND_ID_REG 0x0000002c\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_SS_VEND_ID_LBN 0\n+#define\tPCRF_AZ_SS_VEND_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_SS_ID_REG(16bit):\n+ * Sub-system ID register\n+ */\n+\n+#define\tPCR_AZ_SS_ID_REG 0x0000002e\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_SS_ID_LBN 0\n+#define\tPCRF_AZ_SS_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_EXPROM_BAR_REG(32bit):\n+ * Expansion ROM base address register\n+ */\n+\n+#define\tPCR_AZ_EXPROM_BAR_REG 0x00000030\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_EXPROM_BAR_LBN 11\n+#define\tPCRF_AZ_EXPROM_BAR_WIDTH 21\n+#define\tPCRF_AB_EXPROM_MIN_SIZE_LBN 2\n+#define\tPCRF_AB_EXPROM_MIN_SIZE_WIDTH 9\n+#define\tPCRF_CZ_EXPROM_MIN_SIZE_LBN 1\n+#define\tPCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10\n+#define\tPCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1\n+#define\tPCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1\n+#define\tPCRF_AZ_EXPROM_EN_LBN 0\n+#define\tPCRF_AZ_EXPROM_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_CAP_PTR_REG(8bit):\n+ * Capability pointer register\n+ */\n+\n+#define\tPCR_AZ_CAP_PTR_REG 0x00000034\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_CAP_PTR_LBN 0\n+#define\tPCRF_AZ_CAP_PTR_WIDTH 8\n+\n+\n+/*\n+ * PC_INT_LINE_REG(8bit):\n+ * Interrupt line register\n+ */\n+\n+#define\tPCR_AZ_INT_LINE_REG 0x0000003c\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_INT_LINE_LBN 0\n+#define\tPCRF_AZ_INT_LINE_WIDTH 8\n+\n+\n+/*\n+ * PC_INT_PIN_REG(8bit):\n+ * Interrupt pin register\n+ */\n+\n+#define\tPCR_AZ_INT_PIN_REG 0x0000003d\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_INT_PIN_LBN 0\n+#define\tPCRF_AZ_INT_PIN_WIDTH 8\n+#define\tPCFE_DZ_INTPIN_INTD 4\n+#define\tPCFE_DZ_INTPIN_INTC 3\n+#define\tPCFE_DZ_INTPIN_INTB 2\n+#define\tPCFE_DZ_INTPIN_INTA 1\n+\n+\n+/*\n+ * PC_PM_CAP_ID_REG(8bit):\n+ * Power management capability ID\n+ */\n+\n+#define\tPCR_AZ_PM_CAP_ID_REG 0x00000040\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_PM_CAP_ID_LBN 0\n+#define\tPCRF_AZ_PM_CAP_ID_WIDTH 8\n+\n+\n+/*\n+ * PC_PM_NXT_PTR_REG(8bit):\n+ * Power management next item pointer\n+ */\n+\n+#define\tPCR_AZ_PM_NXT_PTR_REG 0x00000041\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_PM_NXT_PTR_LBN 0\n+#define\tPCRF_AZ_PM_NXT_PTR_WIDTH 8\n+\n+\n+/*\n+ * PC_PM_CAP_REG(16bit):\n+ * Power management capabilities register\n+ */\n+\n+#define\tPCR_AZ_PM_CAP_REG 0x00000042\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_PM_PME_SUPT_LBN 11\n+#define\tPCRF_AZ_PM_PME_SUPT_WIDTH 5\n+#define\tPCRF_AZ_PM_D2_SUPT_LBN 10\n+#define\tPCRF_AZ_PM_D2_SUPT_WIDTH 1\n+#define\tPCRF_AZ_PM_D1_SUPT_LBN 9\n+#define\tPCRF_AZ_PM_D1_SUPT_WIDTH 1\n+#define\tPCRF_AZ_PM_AUX_CURR_LBN 6\n+#define\tPCRF_AZ_PM_AUX_CURR_WIDTH 3\n+#define\tPCRF_AZ_PM_DSI_LBN 5\n+#define\tPCRF_AZ_PM_DSI_WIDTH 1\n+#define\tPCRF_AZ_PM_PME_CLK_LBN 3\n+#define\tPCRF_AZ_PM_PME_CLK_WIDTH 1\n+#define\tPCRF_AZ_PM_PME_VER_LBN 0\n+#define\tPCRF_AZ_PM_PME_VER_WIDTH 3\n+\n+\n+/*\n+ * PC_PM_CS_REG(16bit):\n+ * Power management control & status register\n+ */\n+\n+#define\tPCR_AZ_PM_CS_REG 0x00000044\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_PM_PME_STAT_LBN 15\n+#define\tPCRF_AZ_PM_PME_STAT_WIDTH 1\n+#define\tPCRF_AZ_PM_DAT_SCALE_LBN 13\n+#define\tPCRF_AZ_PM_DAT_SCALE_WIDTH 2\n+#define\tPCRF_AZ_PM_DAT_SEL_LBN 9\n+#define\tPCRF_AZ_PM_DAT_SEL_WIDTH 4\n+#define\tPCRF_AZ_PM_PME_EN_LBN 8\n+#define\tPCRF_AZ_PM_PME_EN_WIDTH 1\n+#define\tPCRF_CZ_NO_SOFT_RESET_LBN 3\n+#define\tPCRF_CZ_NO_SOFT_RESET_WIDTH 1\n+#define\tPCRF_AZ_PM_PWR_ST_LBN 0\n+#define\tPCRF_AZ_PM_PWR_ST_WIDTH 2\n+\n+\n+/*\n+ * PC_MSI_CAP_ID_REG(8bit):\n+ * MSI capability ID\n+ */\n+\n+#define\tPCR_AZ_MSI_CAP_ID_REG 0x00000050\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MSI_CAP_ID_LBN 0\n+#define\tPCRF_AZ_MSI_CAP_ID_WIDTH 8\n+\n+\n+/*\n+ * PC_MSI_NXT_PTR_REG(8bit):\n+ * MSI next item pointer\n+ */\n+\n+#define\tPCR_AZ_MSI_NXT_PTR_REG 0x00000051\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MSI_NXT_PTR_LBN 0\n+#define\tPCRF_AZ_MSI_NXT_PTR_WIDTH 8\n+\n+\n+/*\n+ * PC_MSI_CTL_REG(16bit):\n+ * MSI control register\n+ */\n+\n+#define\tPCR_AZ_MSI_CTL_REG 0x00000052\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MSI_64_EN_LBN 7\n+#define\tPCRF_AZ_MSI_64_EN_WIDTH 1\n+#define\tPCRF_AZ_MSI_MULT_MSG_EN_LBN 4\n+#define\tPCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3\n+#define\tPCRF_AZ_MSI_MULT_MSG_CAP_LBN 1\n+#define\tPCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3\n+#define\tPCRF_AZ_MSI_EN_LBN 0\n+#define\tPCRF_AZ_MSI_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_MSI_ADR_LO_REG(32bit):\n+ * MSI low 32 bits address register\n+ */\n+\n+#define\tPCR_AZ_MSI_ADR_LO_REG 0x00000054\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MSI_ADR_LO_LBN 2\n+#define\tPCRF_AZ_MSI_ADR_LO_WIDTH 30\n+\n+\n+/*\n+ * PC_MSI_ADR_HI_REG(32bit):\n+ * MSI high 32 bits address register\n+ */\n+\n+#define\tPCR_AZ_MSI_ADR_HI_REG 0x00000058\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MSI_ADR_HI_LBN 0\n+#define\tPCRF_AZ_MSI_ADR_HI_WIDTH 32\n+\n+\n+/*\n+ * PC_MSI_DAT_REG(16bit):\n+ * MSI data register\n+ */\n+\n+#define\tPCR_AZ_MSI_DAT_REG 0x0000005c\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_MSI_DAT_LBN 0\n+#define\tPCRF_AZ_MSI_DAT_WIDTH 16\n+\n+\n+/*\n+ * PC_PCIE_CAP_LIST_REG(16bit):\n+ * PCIe capability list register\n+ */\n+\n+#define\tPCR_AB_PCIE_CAP_LIST_REG 0x00000060\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_PCIE_CAP_LIST_REG 0x00000070\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_PCIE_NXT_PTR_LBN 8\n+#define\tPCRF_AZ_PCIE_NXT_PTR_WIDTH 8\n+#define\tPCRF_AZ_PCIE_CAP_ID_LBN 0\n+#define\tPCRF_AZ_PCIE_CAP_ID_WIDTH 8\n+\n+\n+/*\n+ * PC_PCIE_CAP_REG(16bit):\n+ * PCIe capability register\n+ */\n+\n+#define\tPCR_AB_PCIE_CAP_REG 0x00000062\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_PCIE_CAP_REG 0x00000072\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_PCIE_INT_MSG_NUM_LBN 9\n+#define\tPCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5\n+#define\tPCRF_AZ_PCIE_SLOT_IMP_LBN 8\n+#define\tPCRF_AZ_PCIE_SLOT_IMP_WIDTH 1\n+#define\tPCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4\n+#define\tPCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4\n+#define\tPCRF_AZ_PCIE_CAP_VER_LBN 0\n+#define\tPCRF_AZ_PCIE_CAP_VER_WIDTH 4\n+\n+\n+/*\n+ * PC_DEV_CAP_REG(32bit):\n+ * PCIe device capabilities register\n+ */\n+\n+#define\tPCR_AB_DEV_CAP_REG 0x00000064\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_DEV_CAP_REG 0x00000074\n+/* sienaa0=pci_f0_config,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28\n+#define\tPCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1\n+#define\tPCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26\n+#define\tPCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2\n+#define\tPCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18\n+#define\tPCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8\n+#define\tPCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15\n+#define\tPCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1\n+#define\tPCRF_AB_PWR_IND_LBN 14\n+#define\tPCRF_AB_PWR_IND_WIDTH 1\n+#define\tPCRF_AB_ATTN_IND_LBN 13\n+#define\tPCRF_AB_ATTN_IND_WIDTH 1\n+#define\tPCRF_AB_ATTN_BUTTON_LBN 12\n+#define\tPCRF_AB_ATTN_BUTTON_WIDTH 1\n+#define\tPCRF_AZ_ENDPT_L1_LAT_LBN 9\n+#define\tPCRF_AZ_ENDPT_L1_LAT_WIDTH 3\n+#define\tPCRF_AZ_ENDPT_L0_LAT_LBN 6\n+#define\tPCRF_AZ_ENDPT_L0_LAT_WIDTH 3\n+#define\tPCRF_AZ_TAG_FIELD_LBN 5\n+#define\tPCRF_AZ_TAG_FIELD_WIDTH 1\n+#define\tPCRF_AZ_PHAN_FUNC_LBN 3\n+#define\tPCRF_AZ_PHAN_FUNC_WIDTH 2\n+#define\tPCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0\n+#define\tPCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3\n+\n+\n+/*\n+ * PC_DEV_CTL_REG(16bit):\n+ * PCIe device control register\n+ */\n+\n+#define\tPCR_AB_DEV_CTL_REG 0x00000068\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_DEV_CTL_REG 0x00000078\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_FN_LEVEL_RESET_LBN 15\n+#define\tPCRF_CZ_FN_LEVEL_RESET_WIDTH 1\n+#define\tPCRF_AZ_MAX_RD_REQ_SIZE_LBN 12\n+#define\tPCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3\n+#define\tPCFE_AZ_MAX_RD_REQ_SIZE_4096 5\n+#define\tPCFE_AZ_MAX_RD_REQ_SIZE_2048 4\n+#define\tPCFE_AZ_MAX_RD_REQ_SIZE_1024 3\n+#define\tPCFE_AZ_MAX_RD_REQ_SIZE_512 2\n+#define\tPCFE_AZ_MAX_RD_REQ_SIZE_256 1\n+#define\tPCFE_AZ_MAX_RD_REQ_SIZE_128 0\n+#define\tPCRF_AZ_EN_NO_SNOOP_LBN 11\n+#define\tPCRF_AZ_EN_NO_SNOOP_WIDTH 1\n+#define\tPCRF_AZ_AUX_PWR_PM_EN_LBN 10\n+#define\tPCRF_AZ_AUX_PWR_PM_EN_WIDTH 1\n+#define\tPCRF_AZ_PHAN_FUNC_EN_LBN 9\n+#define\tPCRF_AZ_PHAN_FUNC_EN_WIDTH 1\n+#define\tPCRF_AB_DEV_CAP_REG_RSVD0_LBN 8\n+#define\tPCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1\n+#define\tPCRF_CZ_EXTENDED_TAG_EN_LBN 8\n+#define\tPCRF_CZ_EXTENDED_TAG_EN_WIDTH 1\n+#define\tPCRF_AZ_MAX_PAYL_SIZE_LBN 5\n+#define\tPCRF_AZ_MAX_PAYL_SIZE_WIDTH 3\n+#define\tPCFE_AZ_MAX_PAYL_SIZE_4096 5\n+#define\tPCFE_AZ_MAX_PAYL_SIZE_2048 4\n+#define\tPCFE_AZ_MAX_PAYL_SIZE_1024 3\n+#define\tPCFE_AZ_MAX_PAYL_SIZE_512 2\n+#define\tPCFE_AZ_MAX_PAYL_SIZE_256 1\n+#define\tPCFE_AZ_MAX_PAYL_SIZE_128 0\n+#define\tPCRF_AZ_EN_RELAX_ORDER_LBN 4\n+#define\tPCRF_AZ_EN_RELAX_ORDER_WIDTH 1\n+#define\tPCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3\n+#define\tPCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1\n+#define\tPCRF_AZ_FATAL_ERR_RPT_EN_LBN 2\n+#define\tPCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1\n+#define\tPCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1\n+#define\tPCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1\n+#define\tPCRF_AZ_CORR_ERR_RPT_EN_LBN 0\n+#define\tPCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_DEV_STAT_REG(16bit):\n+ * PCIe device status register\n+ */\n+\n+#define\tPCR_AB_DEV_STAT_REG 0x0000006a\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_DEV_STAT_REG 0x0000007a\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_TRNS_PEND_LBN 5\n+#define\tPCRF_AZ_TRNS_PEND_WIDTH 1\n+#define\tPCRF_AZ_AUX_PWR_DET_LBN 4\n+#define\tPCRF_AZ_AUX_PWR_DET_WIDTH 1\n+#define\tPCRF_AZ_UNSUP_REQ_DET_LBN 3\n+#define\tPCRF_AZ_UNSUP_REQ_DET_WIDTH 1\n+#define\tPCRF_AZ_FATAL_ERR_DET_LBN 2\n+#define\tPCRF_AZ_FATAL_ERR_DET_WIDTH 1\n+#define\tPCRF_AZ_NONFATAL_ERR_DET_LBN 1\n+#define\tPCRF_AZ_NONFATAL_ERR_DET_WIDTH 1\n+#define\tPCRF_AZ_CORR_ERR_DET_LBN 0\n+#define\tPCRF_AZ_CORR_ERR_DET_WIDTH 1\n+\n+\n+/*\n+ * PC_LNK_CAP_REG(32bit):\n+ * PCIe link capabilities register\n+ */\n+\n+#define\tPCR_AB_LNK_CAP_REG 0x0000006c\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_LNK_CAP_REG 0x0000007c\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_PORT_NUM_LBN 24\n+#define\tPCRF_AZ_PORT_NUM_WIDTH 8\n+#define\tPCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22\n+#define\tPCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1\n+#define\tPCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21\n+#define\tPCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1\n+#define\tPCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20\n+#define\tPCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1\n+#define\tPCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19\n+#define\tPCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1\n+#define\tPCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18\n+#define\tPCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1\n+#define\tPCRF_AZ_DEF_L1_EXIT_LAT_LBN 15\n+#define\tPCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3\n+#define\tPCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12\n+#define\tPCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3\n+#define\tPCRF_AZ_AS_LNK_PM_SUPT_LBN 10\n+#define\tPCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2\n+#define\tPCRF_AZ_MAX_LNK_WIDTH_LBN 4\n+#define\tPCRF_AZ_MAX_LNK_WIDTH_WIDTH 6\n+#define\tPCRF_AZ_MAX_LNK_SP_LBN 0\n+#define\tPCRF_AZ_MAX_LNK_SP_WIDTH 4\n+\n+\n+/*\n+ * PC_LNK_CTL_REG(16bit):\n+ * PCIe link control register\n+ */\n+\n+#define\tPCR_AB_LNK_CTL_REG 0x00000070\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_LNK_CTL_REG 0x00000080\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_EXT_SYNC_LBN 7\n+#define\tPCRF_AZ_EXT_SYNC_WIDTH 1\n+#define\tPCRF_AZ_COMM_CLK_CFG_LBN 6\n+#define\tPCRF_AZ_COMM_CLK_CFG_WIDTH 1\n+#define\tPCRF_AB_LNK_CTL_REG_RSVD0_LBN 5\n+#define\tPCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1\n+#define\tPCRF_CZ_LNK_RETRAIN_LBN 5\n+#define\tPCRF_CZ_LNK_RETRAIN_WIDTH 1\n+#define\tPCRF_AZ_LNK_DIS_LBN 4\n+#define\tPCRF_AZ_LNK_DIS_WIDTH 1\n+#define\tPCRF_AZ_RD_COM_BDRY_LBN 3\n+#define\tPCRF_AZ_RD_COM_BDRY_WIDTH 1\n+#define\tPCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0\n+#define\tPCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2\n+\n+\n+/*\n+ * PC_LNK_STAT_REG(16bit):\n+ * PCIe link status register\n+ */\n+\n+#define\tPCR_AB_LNK_STAT_REG 0x00000072\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_LNK_STAT_REG 0x00000082\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_SLOT_CLK_CFG_LBN 12\n+#define\tPCRF_AZ_SLOT_CLK_CFG_WIDTH 1\n+#define\tPCRF_AZ_LNK_TRAIN_LBN 11\n+#define\tPCRF_AZ_LNK_TRAIN_WIDTH 1\n+#define\tPCRF_AB_TRAIN_ERR_LBN 10\n+#define\tPCRF_AB_TRAIN_ERR_WIDTH 1\n+#define\tPCRF_AZ_LNK_WIDTH_LBN 4\n+#define\tPCRF_AZ_LNK_WIDTH_WIDTH 6\n+#define\tPCRF_AZ_LNK_SP_LBN 0\n+#define\tPCRF_AZ_LNK_SP_WIDTH 4\n+\n+\n+/*\n+ * PC_SLOT_CAP_REG(32bit):\n+ * PCIe slot capabilities register\n+ */\n+\n+#define\tPCR_AB_SLOT_CAP_REG 0x00000074\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCRF_AB_SLOT_NUM_LBN 19\n+#define\tPCRF_AB_SLOT_NUM_WIDTH 13\n+#define\tPCRF_AB_SLOT_PWR_LIM_SCL_LBN 15\n+#define\tPCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2\n+#define\tPCRF_AB_SLOT_PWR_LIM_VAL_LBN 7\n+#define\tPCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8\n+#define\tPCRF_AB_SLOT_HP_CAP_LBN 6\n+#define\tPCRF_AB_SLOT_HP_CAP_WIDTH 1\n+#define\tPCRF_AB_SLOT_HP_SURP_LBN 5\n+#define\tPCRF_AB_SLOT_HP_SURP_WIDTH 1\n+#define\tPCRF_AB_SLOT_PWR_IND_PRST_LBN 4\n+#define\tPCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1\n+#define\tPCRF_AB_SLOT_ATTN_IND_PRST_LBN 3\n+#define\tPCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1\n+#define\tPCRF_AB_SLOT_MRL_SENS_PRST_LBN 2\n+#define\tPCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1\n+#define\tPCRF_AB_SLOT_PWR_CTL_PRST_LBN 1\n+#define\tPCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1\n+#define\tPCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0\n+#define\tPCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1\n+\n+\n+/*\n+ * PC_SLOT_CTL_REG(16bit):\n+ * PCIe slot control register\n+ */\n+\n+#define\tPCR_AB_SLOT_CTL_REG 0x00000078\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10\n+#define\tPCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1\n+#define\tPCRF_AB_SLOT_PWR_IND_CTL_LBN 8\n+#define\tPCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2\n+#define\tPCRF_AB_SLOT_ATT_IND_CTL_LBN 6\n+#define\tPCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2\n+#define\tPCRF_AB_SLOT_HP_INT_EN_LBN 5\n+#define\tPCRF_AB_SLOT_HP_INT_EN_WIDTH 1\n+#define\tPCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4\n+#define\tPCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1\n+#define\tPCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3\n+#define\tPCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1\n+#define\tPCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2\n+#define\tPCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1\n+#define\tPCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1\n+#define\tPCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1\n+#define\tPCRF_AB_SLOT_ATTN_BUT_EN_LBN 0\n+#define\tPCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_SLOT_STAT_REG(16bit):\n+ * PCIe slot status register\n+ */\n+\n+#define\tPCR_AB_SLOT_STAT_REG 0x0000007a\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCRF_AB_PRES_DET_ST_LBN 6\n+#define\tPCRF_AB_PRES_DET_ST_WIDTH 1\n+#define\tPCRF_AB_MRL_SENS_ST_LBN 5\n+#define\tPCRF_AB_MRL_SENS_ST_WIDTH 1\n+#define\tPCRF_AB_SLOT_PWR_IND_LBN 4\n+#define\tPCRF_AB_SLOT_PWR_IND_WIDTH 1\n+#define\tPCRF_AB_SLOT_ATTN_IND_LBN 3\n+#define\tPCRF_AB_SLOT_ATTN_IND_WIDTH 1\n+#define\tPCRF_AB_SLOT_MRL_SENS_LBN 2\n+#define\tPCRF_AB_SLOT_MRL_SENS_WIDTH 1\n+#define\tPCRF_AB_PWR_FLTDET_LBN 1\n+#define\tPCRF_AB_PWR_FLTDET_WIDTH 1\n+#define\tPCRF_AB_ATTN_BUTDET_LBN 0\n+#define\tPCRF_AB_ATTN_BUTDET_WIDTH 1\n+\n+\n+/*\n+ * PC_MSIX_CAP_ID_REG(8bit):\n+ * MSIX Capability ID\n+ */\n+\n+#define\tPCR_BB_MSIX_CAP_ID_REG 0x00000090\n+/* falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_MSIX_CAP_ID_REG 0x000000b0\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_BZ_MSIX_CAP_ID_LBN 0\n+#define\tPCRF_BZ_MSIX_CAP_ID_WIDTH 8\n+\n+\n+/*\n+ * PC_MSIX_NXT_PTR_REG(8bit):\n+ * MSIX Capability Next Capability Ptr\n+ */\n+\n+#define\tPCR_BB_MSIX_NXT_PTR_REG 0x00000091\n+/* falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_MSIX_NXT_PTR_REG 0x000000b1\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_BZ_MSIX_NXT_PTR_LBN 0\n+#define\tPCRF_BZ_MSIX_NXT_PTR_WIDTH 8\n+\n+\n+/*\n+ * PC_MSIX_CTL_REG(16bit):\n+ * MSIX control register\n+ */\n+\n+#define\tPCR_BB_MSIX_CTL_REG 0x00000092\n+/* falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_MSIX_CTL_REG 0x000000b2\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_BZ_MSIX_EN_LBN 15\n+#define\tPCRF_BZ_MSIX_EN_WIDTH 1\n+#define\tPCRF_BZ_MSIX_FUNC_MASK_LBN 14\n+#define\tPCRF_BZ_MSIX_FUNC_MASK_WIDTH 1\n+#define\tPCRF_BZ_MSIX_TBL_SIZE_LBN 0\n+#define\tPCRF_BZ_MSIX_TBL_SIZE_WIDTH 11\n+\n+\n+/*\n+ * PC_MSIX_TBL_BASE_REG(32bit):\n+ * MSIX Capability Vector Table Base\n+ */\n+\n+#define\tPCR_BB_MSIX_TBL_BASE_REG 0x00000094\n+/* falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_MSIX_TBL_BASE_REG 0x000000b4\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_BZ_MSIX_TBL_OFF_LBN 3\n+#define\tPCRF_BZ_MSIX_TBL_OFF_WIDTH 29\n+#define\tPCRF_BZ_MSIX_TBL_BIR_LBN 0\n+#define\tPCRF_BZ_MSIX_TBL_BIR_WIDTH 3\n+\n+\n+/*\n+ * PC_DEV_CAP2_REG(32bit):\n+ * PCIe Device Capabilities 2\n+ */\n+\n+#define\tPCR_CZ_DEV_CAP2_REG 0x00000094\n+/* sienaa0=pci_f0_config,hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_OBFF_SUPPORTED_LBN 18\n+#define\tPCRF_DZ_OBFF_SUPPORTED_WIDTH 2\n+#define\tPCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12\n+#define\tPCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2\n+#define\tPCRF_DZ_LTR_M_SUPPORTED_LBN 11\n+#define\tPCRF_DZ_LTR_M_SUPPORTED_WIDTH 1\n+#define\tPCRF_CC_CMPL_TIMEOUT_DIS_LBN 4\n+#define\tPCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1\n+#define\tPCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4\n+#define\tPCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1\n+#define\tPCRF_CZ_CMPL_TIMEOUT_LBN 0\n+#define\tPCRF_CZ_CMPL_TIMEOUT_WIDTH 4\n+#define\tPCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14\n+#define\tPCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13\n+#define\tPCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10\n+#define\tPCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9\n+#define\tPCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6\n+#define\tPCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5\n+#define\tPCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2\n+#define\tPCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1\n+#define\tPCFE_CZ_CMPL_TIMEOUT_DEFAULT 0\n+\n+\n+/*\n+ * PC_DEV_CTL2_REG(16bit):\n+ * PCIe Device Control 2\n+ */\n+\n+#define\tPCR_CZ_DEV_CTL2_REG 0x00000098\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_OBFF_ENABLE_LBN 13\n+#define\tPCRF_DZ_OBFF_ENABLE_WIDTH 2\n+#define\tPCRF_DZ_LTR_ENABLE_LBN 10\n+#define\tPCRF_DZ_LTR_ENABLE_WIDTH 1\n+#define\tPCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9\n+#define\tPCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1\n+#define\tPCRF_DZ_IDO_REQUEST_ENABLE_LBN 8\n+#define\tPCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1\n+#define\tPCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4\n+#define\tPCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1\n+#define\tPCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0\n+#define\tPCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4\n+\n+\n+/*\n+ * PC_MSIX_PBA_BASE_REG(32bit):\n+ * MSIX Capability PBA Base\n+ */\n+\n+#define\tPCR_BB_MSIX_PBA_BASE_REG 0x00000098\n+/* falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_MSIX_PBA_BASE_REG 0x000000b8\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_BZ_MSIX_PBA_OFF_LBN 3\n+#define\tPCRF_BZ_MSIX_PBA_OFF_WIDTH 29\n+#define\tPCRF_BZ_MSIX_PBA_BIR_LBN 0\n+#define\tPCRF_BZ_MSIX_PBA_BIR_WIDTH 3\n+\n+\n+/*\n+ * PC_LNK_CAP2_REG(32bit):\n+ * PCIe Link Capability 2\n+ */\n+\n+#define\tPCR_DZ_LNK_CAP2_REG 0x0000009c\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LNK_SPEED_SUP_LBN 1\n+#define\tPCRF_DZ_LNK_SPEED_SUP_WIDTH 7\n+\n+\n+/*\n+ * PC_LNK_CTL2_REG(16bit):\n+ * PCIe Link Control 2\n+ */\n+\n+#define\tPCR_CZ_LNK_CTL2_REG 0x000000a0\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_POLLING_DEEMPH_LVL_LBN 12\n+#define\tPCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1\n+#define\tPCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11\n+#define\tPCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1\n+#define\tPCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10\n+#define\tPCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1\n+#define\tPCRF_CZ_TRANSMIT_MARGIN_LBN 7\n+#define\tPCRF_CZ_TRANSMIT_MARGIN_WIDTH 3\n+#define\tPCRF_CZ_SELECT_DEEMPH_LBN 6\n+#define\tPCRF_CZ_SELECT_DEEMPH_WIDTH 1\n+#define\tPCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5\n+#define\tPCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1\n+#define\tPCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4\n+#define\tPCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1\n+#define\tPCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0\n+#define\tPCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4\n+#define\tPCFE_DZ_LCTL2_TGT_SPEED_GEN3 3\n+#define\tPCFE_DZ_LCTL2_TGT_SPEED_GEN2 2\n+#define\tPCFE_DZ_LCTL2_TGT_SPEED_GEN1 1\n+\n+\n+/*\n+ * PC_LNK_STAT2_REG(16bit):\n+ * PCIe Link Status 2\n+ */\n+\n+#define\tPCR_CZ_LNK_STAT2_REG 0x000000a2\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_CURRENT_DEEMPH_LBN 0\n+#define\tPCRF_CZ_CURRENT_DEEMPH_WIDTH 1\n+\n+\n+/*\n+ * PC_VPD_CAP_ID_REG(8bit):\n+ * VPD data register\n+ */\n+\n+#define\tPCR_AB_VPD_CAP_ID_REG 0x000000b0\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCRF_AB_VPD_CAP_ID_LBN 0\n+#define\tPCRF_AB_VPD_CAP_ID_WIDTH 8\n+\n+\n+/*\n+ * PC_VPD_NXT_PTR_REG(8bit):\n+ * VPD next item pointer\n+ */\n+\n+#define\tPCR_AB_VPD_NXT_PTR_REG 0x000000b1\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCRF_AB_VPD_NXT_PTR_LBN 0\n+#define\tPCRF_AB_VPD_NXT_PTR_WIDTH 8\n+\n+\n+/*\n+ * PC_VPD_ADDR_REG(16bit):\n+ * VPD address register\n+ */\n+\n+#define\tPCR_AB_VPD_ADDR_REG 0x000000b2\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCRF_AB_VPD_FLAG_LBN 15\n+#define\tPCRF_AB_VPD_FLAG_WIDTH 1\n+#define\tPCRF_AB_VPD_ADDR_LBN 0\n+#define\tPCRF_AB_VPD_ADDR_WIDTH 15\n+\n+\n+/*\n+ * PC_VPD_CAP_DATA_REG(32bit):\n+ * documentation to be written for sum_PC_VPD_CAP_DATA_REG\n+ */\n+\n+#define\tPCR_AB_VPD_CAP_DATA_REG 0x000000b4\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CZ_VPD_CAP_DATA_REG 0x000000d4\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_VPD_DATA_LBN 0\n+#define\tPCRF_AZ_VPD_DATA_WIDTH 32\n+\n+\n+/*\n+ * PC_VPD_CAP_CTL_REG(8bit):\n+ * VPD control and capabilities register\n+ */\n+\n+#define\tPCR_CZ_VPD_CAP_CTL_REG 0x000000d0\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VPD_FLAG_LBN 31\n+#define\tPCRF_CZ_VPD_FLAG_WIDTH 1\n+#define\tPCRF_CZ_VPD_ADDR_LBN 16\n+#define\tPCRF_CZ_VPD_ADDR_WIDTH 15\n+#define\tPCRF_CZ_VPD_NXT_PTR_LBN 8\n+#define\tPCRF_CZ_VPD_NXT_PTR_WIDTH 8\n+#define\tPCRF_CZ_VPD_CAP_ID_LBN 0\n+#define\tPCRF_CZ_VPD_CAP_ID_WIDTH 8\n+\n+\n+/*\n+ * PC_AER_CAP_HDR_REG(32bit):\n+ * AER capability header register\n+ */\n+\n+#define\tPCR_AZ_AER_CAP_HDR_REG 0x00000100\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20\n+#define\tPCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12\n+#define\tPCRF_AZ_AERCAPHDR_VER_LBN 16\n+#define\tPCRF_AZ_AERCAPHDR_VER_WIDTH 4\n+#define\tPCRF_AZ_AERCAPHDR_ID_LBN 0\n+#define\tPCRF_AZ_AERCAPHDR_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_AER_UNCORR_ERR_STAT_REG(32bit):\n+ * AER Uncorrectable error status register\n+ */\n+\n+#define\tPCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20\n+#define\tPCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1\n+#define\tPCRF_AZ_ECRC_ERR_STAT_LBN 19\n+#define\tPCRF_AZ_ECRC_ERR_STAT_WIDTH 1\n+#define\tPCRF_AZ_MALF_TLP_STAT_LBN 18\n+#define\tPCRF_AZ_MALF_TLP_STAT_WIDTH 1\n+#define\tPCRF_AZ_RX_OVF_STAT_LBN 17\n+#define\tPCRF_AZ_RX_OVF_STAT_WIDTH 1\n+#define\tPCRF_AZ_UNEXP_COMP_STAT_LBN 16\n+#define\tPCRF_AZ_UNEXP_COMP_STAT_WIDTH 1\n+#define\tPCRF_AZ_COMP_ABRT_STAT_LBN 15\n+#define\tPCRF_AZ_COMP_ABRT_STAT_WIDTH 1\n+#define\tPCRF_AZ_COMP_TIMEOUT_STAT_LBN 14\n+#define\tPCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1\n+#define\tPCRF_AZ_FC_PROTO_ERR_STAT_LBN 13\n+#define\tPCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1\n+#define\tPCRF_AZ_PSON_TLP_STAT_LBN 12\n+#define\tPCRF_AZ_PSON_TLP_STAT_WIDTH 1\n+#define\tPCRF_AZ_DL_PROTO_ERR_STAT_LBN 4\n+#define\tPCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1\n+#define\tPCRF_AB_TRAIN_ERR_STAT_LBN 0\n+#define\tPCRF_AB_TRAIN_ERR_STAT_WIDTH 1\n+\n+\n+/*\n+ * PC_AER_UNCORR_ERR_MASK_REG(32bit):\n+ * AER Uncorrectable error mask register\n+ */\n+\n+#define\tPCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24\n+#define\tPCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1\n+#define\tPCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22\n+#define\tPCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1\n+#define\tPCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20\n+#define\tPCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1\n+#define\tPCRF_AZ_ECRC_ERR_MASK_LBN 19\n+#define\tPCRF_AZ_ECRC_ERR_MASK_WIDTH 1\n+#define\tPCRF_AZ_MALF_TLP_MASK_LBN 18\n+#define\tPCRF_AZ_MALF_TLP_MASK_WIDTH 1\n+#define\tPCRF_AZ_RX_OVF_MASK_LBN 17\n+#define\tPCRF_AZ_RX_OVF_MASK_WIDTH 1\n+#define\tPCRF_AZ_UNEXP_COMP_MASK_LBN 16\n+#define\tPCRF_AZ_UNEXP_COMP_MASK_WIDTH 1\n+#define\tPCRF_AZ_COMP_ABRT_MASK_LBN 15\n+#define\tPCRF_AZ_COMP_ABRT_MASK_WIDTH 1\n+#define\tPCRF_AZ_COMP_TIMEOUT_MASK_LBN 14\n+#define\tPCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1\n+#define\tPCRF_AZ_FC_PROTO_ERR_MASK_LBN 13\n+#define\tPCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1\n+#define\tPCRF_AZ_PSON_TLP_MASK_LBN 12\n+#define\tPCRF_AZ_PSON_TLP_MASK_WIDTH 1\n+#define\tPCRF_AZ_DL_PROTO_ERR_MASK_LBN 4\n+#define\tPCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1\n+#define\tPCRF_AB_TRAIN_ERR_MASK_LBN 0\n+#define\tPCRF_AB_TRAIN_ERR_MASK_WIDTH 1\n+\n+\n+/*\n+ * PC_AER_UNCORR_ERR_SEV_REG(32bit):\n+ * AER Uncorrectable error severity register\n+ */\n+\n+#define\tPCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20\n+#define\tPCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1\n+#define\tPCRF_AZ_ECRC_ERR_SEV_LBN 19\n+#define\tPCRF_AZ_ECRC_ERR_SEV_WIDTH 1\n+#define\tPCRF_AZ_MALF_TLP_SEV_LBN 18\n+#define\tPCRF_AZ_MALF_TLP_SEV_WIDTH 1\n+#define\tPCRF_AZ_RX_OVF_SEV_LBN 17\n+#define\tPCRF_AZ_RX_OVF_SEV_WIDTH 1\n+#define\tPCRF_AZ_UNEXP_COMP_SEV_LBN 16\n+#define\tPCRF_AZ_UNEXP_COMP_SEV_WIDTH 1\n+#define\tPCRF_AZ_COMP_ABRT_SEV_LBN 15\n+#define\tPCRF_AZ_COMP_ABRT_SEV_WIDTH 1\n+#define\tPCRF_AZ_COMP_TIMEOUT_SEV_LBN 14\n+#define\tPCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1\n+#define\tPCRF_AZ_FC_PROTO_ERR_SEV_LBN 13\n+#define\tPCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1\n+#define\tPCRF_AZ_PSON_TLP_SEV_LBN 12\n+#define\tPCRF_AZ_PSON_TLP_SEV_WIDTH 1\n+#define\tPCRF_AZ_DL_PROTO_ERR_SEV_LBN 4\n+#define\tPCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1\n+#define\tPCRF_AB_TRAIN_ERR_SEV_LBN 0\n+#define\tPCRF_AB_TRAIN_ERR_SEV_WIDTH 1\n+\n+\n+/*\n+ * PC_AER_CORR_ERR_STAT_REG(32bit):\n+ * AER Correctable error status register\n+ */\n+\n+#define\tPCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13\n+#define\tPCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1\n+#define\tPCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12\n+#define\tPCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1\n+#define\tPCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8\n+#define\tPCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1\n+#define\tPCRF_AZ_BAD_DLLP_STAT_LBN 7\n+#define\tPCRF_AZ_BAD_DLLP_STAT_WIDTH 1\n+#define\tPCRF_AZ_BAD_TLP_STAT_LBN 6\n+#define\tPCRF_AZ_BAD_TLP_STAT_WIDTH 1\n+#define\tPCRF_AZ_RX_ERR_STAT_LBN 0\n+#define\tPCRF_AZ_RX_ERR_STAT_WIDTH 1\n+\n+\n+/*\n+ * PC_AER_CORR_ERR_MASK_REG(32bit):\n+ * AER Correctable error status register\n+ */\n+\n+#define\tPCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13\n+#define\tPCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1\n+#define\tPCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12\n+#define\tPCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1\n+#define\tPCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8\n+#define\tPCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1\n+#define\tPCRF_AZ_BAD_DLLP_MASK_LBN 7\n+#define\tPCRF_AZ_BAD_DLLP_MASK_WIDTH 1\n+#define\tPCRF_AZ_BAD_TLP_MASK_LBN 6\n+#define\tPCRF_AZ_BAD_TLP_MASK_WIDTH 1\n+#define\tPCRF_AZ_RX_ERR_MASK_LBN 0\n+#define\tPCRF_AZ_RX_ERR_MASK_WIDTH 1\n+\n+\n+/*\n+ * PC_AER_CAP_CTL_REG(32bit):\n+ * AER capability and control register\n+ */\n+\n+#define\tPCR_AZ_AER_CAP_CTL_REG 0x00000118\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_ECRC_CHK_EN_LBN 8\n+#define\tPCRF_AZ_ECRC_CHK_EN_WIDTH 1\n+#define\tPCRF_AZ_ECRC_CHK_CAP_LBN 7\n+#define\tPCRF_AZ_ECRC_CHK_CAP_WIDTH 1\n+#define\tPCRF_AZ_ECRC_GEN_EN_LBN 6\n+#define\tPCRF_AZ_ECRC_GEN_EN_WIDTH 1\n+#define\tPCRF_AZ_ECRC_GEN_CAP_LBN 5\n+#define\tPCRF_AZ_ECRC_GEN_CAP_WIDTH 1\n+#define\tPCRF_AZ_1ST_ERR_PTR_LBN 0\n+#define\tPCRF_AZ_1ST_ERR_PTR_WIDTH 5\n+\n+\n+/*\n+ * PC_AER_HDR_LOG_REG(128bit):\n+ * AER Header log register\n+ */\n+\n+#define\tPCR_AZ_AER_HDR_LOG_REG 0x0000011c\n+/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_AZ_HDR_LOG_LBN 0\n+#define\tPCRF_AZ_HDR_LOG_WIDTH 128\n+\n+\n+/*\n+ * PC_DEVSN_CAP_HDR_REG(32bit):\n+ * Device serial number capability header register\n+ */\n+\n+#define\tPCR_CZ_DEVSN_CAP_HDR_REG 0x00000140\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20\n+#define\tPCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12\n+#define\tPCRF_CZ_DEVSNCAPHDR_VER_LBN 16\n+#define\tPCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4\n+#define\tPCRF_CZ_DEVSNCAPHDR_ID_LBN 0\n+#define\tPCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_DEVSN_DWORD0_REG(32bit):\n+ * Device serial number DWORD0\n+ */\n+\n+#define\tPCR_CZ_DEVSN_DWORD0_REG 0x00000144\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_DEVSN_DWORD0_LBN 0\n+#define\tPCRF_CZ_DEVSN_DWORD0_WIDTH 32\n+\n+\n+/*\n+ * PC_DEVSN_DWORD1_REG(32bit):\n+ * Device serial number DWORD0\n+ */\n+\n+#define\tPCR_CZ_DEVSN_DWORD1_REG 0x00000148\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_DEVSN_DWORD1_LBN 0\n+#define\tPCRF_CZ_DEVSN_DWORD1_WIDTH 32\n+\n+\n+/*\n+ * PC_ARI_CAP_HDR_REG(32bit):\n+ * ARI capability header register\n+ */\n+\n+#define\tPCR_CZ_ARI_CAP_HDR_REG 0x00000150\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20\n+#define\tPCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12\n+#define\tPCRF_CZ_ARICAPHDR_VER_LBN 16\n+#define\tPCRF_CZ_ARICAPHDR_VER_WIDTH 4\n+#define\tPCRF_CZ_ARICAPHDR_ID_LBN 0\n+#define\tPCRF_CZ_ARICAPHDR_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_ARI_CAP_REG(16bit):\n+ * ARI Capabilities\n+ */\n+\n+#define\tPCR_CZ_ARI_CAP_REG 0x00000154\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_ARI_NXT_FN_NUM_LBN 8\n+#define\tPCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8\n+#define\tPCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1\n+#define\tPCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1\n+#define\tPCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0\n+#define\tPCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1\n+\n+\n+/*\n+ * PC_ARI_CTL_REG(16bit):\n+ * ARI Control\n+ */\n+\n+#define\tPCR_CZ_ARI_CTL_REG 0x00000156\n+/* sienaa0,hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_ARI_FN_GRP_LBN 4\n+#define\tPCRF_CZ_ARI_FN_GRP_WIDTH 3\n+#define\tPCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1\n+#define\tPCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1\n+#define\tPCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0\n+#define\tPCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_SEC_PCIE_CAP_REG(32bit):\n+ * Secondary PCIE Capability Register\n+ */\n+\n+#define\tPCR_DZ_SEC_PCIE_CAP_REG 0x00000160\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_SEC_NXT_PTR_LBN 20\n+#define\tPCRF_DZ_SEC_NXT_PTR_WIDTH 12\n+#define\tPCRF_DZ_SEC_VERSION_LBN 16\n+#define\tPCRF_DZ_SEC_VERSION_WIDTH 4\n+#define\tPCRF_DZ_SEC_EXT_CAP_ID_LBN 0\n+#define\tPCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_CAP_HDR_REG(32bit):\n+ * SRIOV capability header register\n+ */\n+\n+#define\tPCR_CC_SRIOV_CAP_HDR_REG 0x00000160\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_CAP_HDR_REG 0x00000180\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20\n+#define\tPCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12\n+#define\tPCRF_CZ_SRIOVCAPHDR_VER_LBN 16\n+#define\tPCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4\n+#define\tPCRF_CZ_SRIOVCAPHDR_ID_LBN 0\n+#define\tPCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_CAP_REG(32bit):\n+ * SRIOV Capabilities\n+ */\n+\n+#define\tPCR_CC_SRIOV_CAP_REG 0x00000164\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_CAP_REG 0x00000184\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21\n+#define\tPCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11\n+#define\tPCRF_DZ_VF_ARI_CAP_PRESV_LBN 1\n+#define\tPCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1\n+#define\tPCRF_CZ_VF_MIGR_CAP_LBN 0\n+#define\tPCRF_CZ_VF_MIGR_CAP_WIDTH 1\n+\n+\n+/*\n+ * PC_LINK_CONTROL3_REG(32bit):\n+ * Link Control 3.\n+ */\n+\n+#define\tPCR_DZ_LINK_CONTROL3_REG 0x00000164\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LINK_EQ_INT_EN_LBN 1\n+#define\tPCRF_DZ_LINK_EQ_INT_EN_WIDTH 1\n+#define\tPCRF_DZ_PERFORM_EQL_LBN 0\n+#define\tPCRF_DZ_PERFORM_EQL_WIDTH 1\n+\n+\n+/*\n+ * PC_LANE_ERROR_STAT_REG(32bit):\n+ * Lane Error Status Register.\n+ */\n+\n+#define\tPCR_DZ_LANE_ERROR_STAT_REG 0x00000168\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LANE_STATUS_LBN 0\n+#define\tPCRF_DZ_LANE_STATUS_WIDTH 8\n+\n+\n+/*\n+ * PC_SRIOV_CTL_REG(16bit):\n+ * SRIOV Control\n+ */\n+\n+#define\tPCR_CC_SRIOV_CTL_REG 0x00000168\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_CTL_REG 0x00000188\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4\n+#define\tPCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1\n+#define\tPCRF_CZ_VF_MSE_LBN 3\n+#define\tPCRF_CZ_VF_MSE_WIDTH 1\n+#define\tPCRF_CZ_VF_MIGR_INT_EN_LBN 2\n+#define\tPCRF_CZ_VF_MIGR_INT_EN_WIDTH 1\n+#define\tPCRF_CZ_VF_MIGR_EN_LBN 1\n+#define\tPCRF_CZ_VF_MIGR_EN_WIDTH 1\n+#define\tPCRF_CZ_VF_EN_LBN 0\n+#define\tPCRF_CZ_VF_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_SRIOV_STAT_REG(16bit):\n+ * SRIOV Status\n+ */\n+\n+#define\tPCR_CC_SRIOV_STAT_REG 0x0000016a\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_STAT_REG 0x0000018a\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_MIGR_STAT_LBN 0\n+#define\tPCRF_CZ_VF_MIGR_STAT_WIDTH 1\n+\n+\n+/*\n+ * PC_LANE01_EQU_CONTROL_REG(32bit):\n+ * Lanes 0,1 Equalization Control Register.\n+ */\n+\n+#define\tPCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LANE1_EQ_CTRL_LBN 16\n+#define\tPCRF_DZ_LANE1_EQ_CTRL_WIDTH 16\n+#define\tPCRF_DZ_LANE0_EQ_CTRL_LBN 0\n+#define\tPCRF_DZ_LANE0_EQ_CTRL_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_INITIALVFS_REG(16bit):\n+ * SRIOV Initial VFs\n+ */\n+\n+#define\tPCR_CC_SRIOV_INITIALVFS_REG 0x0000016c\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_INITIALVFS_LBN 0\n+#define\tPCRF_CZ_VF_INITIALVFS_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_TOTALVFS_REG(10bit):\n+ * SRIOV Total VFs\n+ */\n+\n+#define\tPCR_CC_SRIOV_TOTALVFS_REG 0x0000016e\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_TOTALVFS_LBN 0\n+#define\tPCRF_CZ_VF_TOTALVFS_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_NUMVFS_REG(16bit):\n+ * SRIOV Number of VFs\n+ */\n+\n+#define\tPCR_CC_SRIOV_NUMVFS_REG 0x00000170\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_NUMVFS_REG 0x00000190\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_NUMVFS_LBN 0\n+#define\tPCRF_CZ_VF_NUMVFS_WIDTH 16\n+\n+\n+/*\n+ * PC_LANE23_EQU_CONTROL_REG(32bit):\n+ * Lanes 2,3 Equalization Control Register.\n+ */\n+\n+#define\tPCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LANE3_EQ_CTRL_LBN 16\n+#define\tPCRF_DZ_LANE3_EQ_CTRL_WIDTH 16\n+#define\tPCRF_DZ_LANE2_EQ_CTRL_LBN 0\n+#define\tPCRF_DZ_LANE2_EQ_CTRL_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_FN_DPND_LNK_REG(16bit):\n+ * SRIOV Function dependency link\n+ */\n+\n+#define\tPCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0\n+#define\tPCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8\n+\n+\n+/*\n+ * PC_SRIOV_1STVF_OFFSET_REG(16bit):\n+ * SRIOV First VF Offset\n+ */\n+\n+#define\tPCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_1STVF_OFFSET_LBN 0\n+#define\tPCRF_CZ_VF_1STVF_OFFSET_WIDTH 16\n+\n+\n+/*\n+ * PC_LANE45_EQU_CONTROL_REG(32bit):\n+ * Lanes 4,5 Equalization Control Register.\n+ */\n+\n+#define\tPCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LANE5_EQ_CTRL_LBN 16\n+#define\tPCRF_DZ_LANE5_EQ_CTRL_WIDTH 16\n+#define\tPCRF_DZ_LANE4_EQ_CTRL_LBN 0\n+#define\tPCRF_DZ_LANE4_EQ_CTRL_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_VFSTRIDE_REG(16bit):\n+ * SRIOV VF Stride\n+ */\n+\n+#define\tPCR_CC_SRIOV_VFSTRIDE_REG 0x00000176\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_VFSTRIDE_LBN 0\n+#define\tPCRF_CZ_VF_VFSTRIDE_WIDTH 16\n+\n+\n+/*\n+ * PC_LANE67_EQU_CONTROL_REG(32bit):\n+ * Lanes 6,7 Equalization Control Register.\n+ */\n+\n+#define\tPCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LANE7_EQ_CTRL_LBN 16\n+#define\tPCRF_DZ_LANE7_EQ_CTRL_WIDTH 16\n+#define\tPCRF_DZ_LANE6_EQ_CTRL_LBN 0\n+#define\tPCRF_DZ_LANE6_EQ_CTRL_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_DEVID_REG(16bit):\n+ * SRIOV VF Device ID\n+ */\n+\n+#define\tPCR_CC_SRIOV_DEVID_REG 0x0000017a\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_DEVID_REG 0x0000019a\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_DEVID_LBN 0\n+#define\tPCRF_CZ_VF_DEVID_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_SUP_PAGESZ_REG(16bit):\n+ * SRIOV Supported Page Sizes\n+ */\n+\n+#define\tPCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_SUP_PAGESZ_LBN 0\n+#define\tPCRF_CZ_VF_SUP_PAGESZ_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_SYS_PAGESZ_REG(32bit):\n+ * SRIOV System Page Size\n+ */\n+\n+#define\tPCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_SYS_PAGESZ_LBN 0\n+#define\tPCRF_CZ_VF_SYS_PAGESZ_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_BAR0_REG(32bit):\n+ * SRIOV VF Bar0\n+ */\n+\n+#define\tPCR_CC_SRIOV_BAR0_REG 0x00000184\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_BAR0_REG 0x000001a4\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CC_VF_BAR_ADDRESS_LBN 0\n+#define\tPCRF_CC_VF_BAR_ADDRESS_WIDTH 32\n+#define\tPCRF_DZ_VF_BAR0_ADDRESS_LBN 4\n+#define\tPCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28\n+#define\tPCRF_DZ_VF_BAR0_PREF_LBN 3\n+#define\tPCRF_DZ_VF_BAR0_PREF_WIDTH 1\n+#define\tPCRF_DZ_VF_BAR0_TYPE_LBN 1\n+#define\tPCRF_DZ_VF_BAR0_TYPE_WIDTH 2\n+#define\tPCRF_DZ_VF_BAR0_IOM_LBN 0\n+#define\tPCRF_DZ_VF_BAR0_IOM_WIDTH 1\n+\n+\n+/*\n+ * PC_SRIOV_BAR1_REG(32bit):\n+ * SRIOV Bar1\n+ */\n+\n+#define\tPCR_CC_SRIOV_BAR1_REG 0x00000188\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_BAR1_REG 0x000001a8\n+/* hunta0=pci_f0_config */\n+\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */\n+#define\tPCRF_DZ_VF_BAR1_ADDRESS_LBN 0\n+#define\tPCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32\n+\n+\n+/*\n+ * PC_SRIOV_BAR2_REG(32bit):\n+ * SRIOV Bar2\n+ */\n+\n+#define\tPCR_CC_SRIOV_BAR2_REG 0x0000018c\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_BAR2_REG 0x000001ac\n+/* hunta0=pci_f0_config */\n+\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */\n+#define\tPCRF_DZ_VF_BAR2_ADDRESS_LBN 4\n+#define\tPCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28\n+#define\tPCRF_DZ_VF_BAR2_PREF_LBN 3\n+#define\tPCRF_DZ_VF_BAR2_PREF_WIDTH 1\n+#define\tPCRF_DZ_VF_BAR2_TYPE_LBN 1\n+#define\tPCRF_DZ_VF_BAR2_TYPE_WIDTH 2\n+#define\tPCRF_DZ_VF_BAR2_IOM_LBN 0\n+#define\tPCRF_DZ_VF_BAR2_IOM_WIDTH 1\n+\n+\n+/*\n+ * PC_SRIOV_BAR3_REG(32bit):\n+ * SRIOV Bar3\n+ */\n+\n+#define\tPCR_CC_SRIOV_BAR3_REG 0x00000190\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_BAR3_REG 0x000001b0\n+/* hunta0=pci_f0_config */\n+\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */\n+#define\tPCRF_DZ_VF_BAR3_ADDRESS_LBN 0\n+#define\tPCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32\n+\n+\n+/*\n+ * PC_SRIOV_BAR4_REG(32bit):\n+ * SRIOV Bar4\n+ */\n+\n+#define\tPCR_CC_SRIOV_BAR4_REG 0x00000194\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_BAR4_REG 0x000001b4\n+/* hunta0=pci_f0_config */\n+\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */\n+#define\tPCRF_DZ_VF_BAR4_ADDRESS_LBN 0\n+#define\tPCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32\n+\n+\n+/*\n+ * PC_SRIOV_BAR5_REG(32bit):\n+ * SRIOV Bar5\n+ */\n+\n+#define\tPCR_CC_SRIOV_BAR5_REG 0x00000198\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_BAR5_REG 0x000001b8\n+/* hunta0=pci_f0_config */\n+\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */\n+/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */\n+#define\tPCRF_DZ_VF_BAR5_ADDRESS_LBN 0\n+#define\tPCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32\n+\n+\n+/*\n+ * PC_SRIOV_RSVD_REG(16bit):\n+ * Reserved register\n+ */\n+\n+#define\tPCR_DZ_SRIOV_RSVD_REG 0x00000198\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_VF_RSVD_LBN 0\n+#define\tPCRF_DZ_VF_RSVD_WIDTH 16\n+\n+\n+/*\n+ * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):\n+ * SRIOV VF Migration State Array Offset\n+ */\n+\n+#define\tPCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_CZ_VF_MIGR_OFFSET_LBN 3\n+#define\tPCRF_CZ_VF_MIGR_OFFSET_WIDTH 29\n+#define\tPCRF_CZ_VF_MIGR_BIR_LBN 0\n+#define\tPCRF_CZ_VF_MIGR_BIR_WIDTH 3\n+\n+\n+/*\n+ * PC_TPH_CAP_HDR_REG(32bit):\n+ * TPH Capability Header Register\n+ */\n+\n+#define\tPCR_DZ_TPH_CAP_HDR_REG 0x000001c0\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_TPH_NXT_PTR_LBN 20\n+#define\tPCRF_DZ_TPH_NXT_PTR_WIDTH 12\n+#define\tPCRF_DZ_TPH_VERSION_LBN 16\n+#define\tPCRF_DZ_TPH_VERSION_WIDTH 4\n+#define\tPCRF_DZ_TPH_EXT_CAP_ID_LBN 0\n+#define\tPCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_TPH_REQ_CAP_REG(32bit):\n+ * TPH Requester Capability Register\n+ */\n+\n+#define\tPCR_DZ_TPH_REQ_CAP_REG 0x000001c4\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_ST_TBLE_SIZE_LBN 16\n+#define\tPCRF_DZ_ST_TBLE_SIZE_WIDTH 11\n+#define\tPCRF_DZ_ST_TBLE_LOC_LBN 9\n+#define\tPCRF_DZ_ST_TBLE_LOC_WIDTH 2\n+#define\tPCRF_DZ_EXT_TPH_MODE_SUP_LBN 8\n+#define\tPCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1\n+#define\tPCRF_DZ_TPH_DEV_MODE_SUP_LBN 2\n+#define\tPCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1\n+#define\tPCRF_DZ_TPH_INT_MODE_SUP_LBN 1\n+#define\tPCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1\n+#define\tPCRF_DZ_TPH_NOST_MODE_SUP_LBN 0\n+#define\tPCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1\n+\n+\n+/*\n+ * PC_TPH_REQ_CTL_REG(32bit):\n+ * TPH Requester Control Register\n+ */\n+\n+#define\tPCR_DZ_TPH_REQ_CTL_REG 0x000001c8\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_TPH_REQ_ENABLE_LBN 8\n+#define\tPCRF_DZ_TPH_REQ_ENABLE_WIDTH 2\n+#define\tPCRF_DZ_TPH_ST_MODE_LBN 0\n+#define\tPCRF_DZ_TPH_ST_MODE_WIDTH 3\n+\n+\n+/*\n+ * PC_LTR_CAP_HDR_REG(32bit):\n+ * Latency Tolerance Reporting Cap Header Reg\n+ */\n+\n+#define\tPCR_DZ_LTR_CAP_HDR_REG 0x00000290\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LTR_NXT_PTR_LBN 20\n+#define\tPCRF_DZ_LTR_NXT_PTR_WIDTH 12\n+#define\tPCRF_DZ_LTR_VERSION_LBN 16\n+#define\tPCRF_DZ_LTR_VERSION_WIDTH 4\n+#define\tPCRF_DZ_LTR_EXT_CAP_ID_LBN 0\n+#define\tPCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16\n+\n+\n+/*\n+ * PC_LTR_MAX_SNOOP_REG(32bit):\n+ * LTR Maximum Snoop/No Snoop Register\n+ */\n+\n+#define\tPCR_DZ_LTR_MAX_SNOOP_REG 0x00000294\n+/* hunta0=pci_f0_config */\n+\n+#define\tPCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26\n+#define\tPCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3\n+#define\tPCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16\n+#define\tPCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10\n+#define\tPCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10\n+#define\tPCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3\n+#define\tPCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0\n+#define\tPCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10\n+\n+\n+/*\n+ * PC_ACK_LAT_TMR_REG(32bit):\n+ * ACK latency timer & replay timer register\n+ */\n+\n+#define\tPCR_AC_ACK_LAT_TMR_REG 0x00000700\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_RT_LBN 16\n+#define\tPCRF_AC_RT_WIDTH 16\n+#define\tPCRF_AC_ALT_LBN 0\n+#define\tPCRF_AC_ALT_WIDTH 16\n+\n+\n+/*\n+ * PC_OTHER_MSG_REG(32bit):\n+ * Other message register\n+ */\n+\n+#define\tPCR_AC_OTHER_MSG_REG 0x00000704\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_OM_CRPT3_LBN 24\n+#define\tPCRF_AC_OM_CRPT3_WIDTH 8\n+#define\tPCRF_AC_OM_CRPT2_LBN 16\n+#define\tPCRF_AC_OM_CRPT2_WIDTH 8\n+#define\tPCRF_AC_OM_CRPT1_LBN 8\n+#define\tPCRF_AC_OM_CRPT1_WIDTH 8\n+#define\tPCRF_AC_OM_CRPT0_LBN 0\n+#define\tPCRF_AC_OM_CRPT0_WIDTH 8\n+\n+\n+/*\n+ * PC_FORCE_LNK_REG(24bit):\n+ * Port force link register\n+ */\n+\n+#define\tPCR_AC_FORCE_LNK_REG 0x00000708\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_LFS_LBN 16\n+#define\tPCRF_AC_LFS_WIDTH 6\n+#define\tPCRF_AC_FL_LBN 15\n+#define\tPCRF_AC_FL_WIDTH 1\n+#define\tPCRF_AC_LN_LBN 0\n+#define\tPCRF_AC_LN_WIDTH 8\n+\n+\n+/*\n+ * PC_ACK_FREQ_REG(32bit):\n+ * ACK frequency register\n+ */\n+\n+#define\tPCR_AC_ACK_FREQ_REG 0x0000070c\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30\n+#define\tPCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1\n+#define\tPCRF_AC_L1_ENTR_LAT_LBN 27\n+#define\tPCRF_AC_L1_ENTR_LAT_WIDTH 3\n+#define\tPCRF_AC_L0_ENTR_LAT_LBN 24\n+#define\tPCRF_AC_L0_ENTR_LAT_WIDTH 3\n+#define\tPCRF_CC_COMM_NFTS_LBN 16\n+#define\tPCRF_CC_COMM_NFTS_WIDTH 8\n+#define\tPCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16\n+#define\tPCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3\n+#define\tPCRF_AC_MAX_FTS_LBN 8\n+#define\tPCRF_AC_MAX_FTS_WIDTH 8\n+#define\tPCRF_AC_ACK_FREQ_LBN 0\n+#define\tPCRF_AC_ACK_FREQ_WIDTH 8\n+\n+\n+/*\n+ * PC_PORT_LNK_CTL_REG(32bit):\n+ * Port link control register\n+ */\n+\n+#define\tPCR_AC_PORT_LNK_CTL_REG 0x00000710\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AB_LRE_LBN 27\n+#define\tPCRF_AB_LRE_WIDTH 1\n+#define\tPCRF_AB_ESYNC_LBN 26\n+#define\tPCRF_AB_ESYNC_WIDTH 1\n+#define\tPCRF_AB_CRPT_LBN 25\n+#define\tPCRF_AB_CRPT_WIDTH 1\n+#define\tPCRF_AB_XB_LBN 24\n+#define\tPCRF_AB_XB_WIDTH 1\n+#define\tPCRF_AC_LC_LBN 16\n+#define\tPCRF_AC_LC_WIDTH 6\n+#define\tPCRF_AC_LDR_LBN 8\n+#define\tPCRF_AC_LDR_WIDTH 4\n+#define\tPCRF_AC_FLM_LBN 7\n+#define\tPCRF_AC_FLM_WIDTH 1\n+#define\tPCRF_AC_LKD_LBN 6\n+#define\tPCRF_AC_LKD_WIDTH 1\n+#define\tPCRF_AC_DLE_LBN 5\n+#define\tPCRF_AC_DLE_WIDTH 1\n+#define\tPCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4\n+#define\tPCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1\n+#define\tPCRF_AC_RA_LBN 3\n+#define\tPCRF_AC_RA_WIDTH 1\n+#define\tPCRF_AC_LE_LBN 2\n+#define\tPCRF_AC_LE_WIDTH 1\n+#define\tPCRF_AC_SD_LBN 1\n+#define\tPCRF_AC_SD_WIDTH 1\n+#define\tPCRF_AC_OMR_LBN 0\n+#define\tPCRF_AC_OMR_WIDTH 1\n+\n+\n+/*\n+ * PC_LN_SKEW_REG(32bit):\n+ * Lane skew register\n+ */\n+\n+#define\tPCR_AC_LN_SKEW_REG 0x00000714\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_DIS_LBN 31\n+#define\tPCRF_AC_DIS_WIDTH 1\n+#define\tPCRF_AB_RST_LBN 30\n+#define\tPCRF_AB_RST_WIDTH 1\n+#define\tPCRF_AC_AD_LBN 25\n+#define\tPCRF_AC_AD_WIDTH 1\n+#define\tPCRF_AC_FCD_LBN 24\n+#define\tPCRF_AC_FCD_WIDTH 1\n+#define\tPCRF_AC_LS2_LBN 16\n+#define\tPCRF_AC_LS2_WIDTH 8\n+#define\tPCRF_AC_LS1_LBN 8\n+#define\tPCRF_AC_LS1_WIDTH 8\n+#define\tPCRF_AC_LS0_LBN 0\n+#define\tPCRF_AC_LS0_WIDTH 8\n+\n+\n+/*\n+ * PC_SYM_NUM_REG(16bit):\n+ * Symbol number register\n+ */\n+\n+#define\tPCR_AC_SYM_NUM_REG 0x00000718\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_CC_MAX_FUNCTIONS_LBN 29\n+#define\tPCRF_CC_MAX_FUNCTIONS_WIDTH 3\n+#define\tPCRF_CC_FC_WATCHDOG_TMR_LBN 24\n+#define\tPCRF_CC_FC_WATCHDOG_TMR_WIDTH 5\n+#define\tPCRF_CC_ACK_NAK_TMR_MOD_LBN 19\n+#define\tPCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5\n+#define\tPCRF_CC_REPLAY_TMR_MOD_LBN 14\n+#define\tPCRF_CC_REPLAY_TMR_MOD_WIDTH 5\n+#define\tPCRF_AB_ES_LBN 12\n+#define\tPCRF_AB_ES_WIDTH 3\n+#define\tPCRF_AB_SYM_NUM_REG_RSVD0_LBN 11\n+#define\tPCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1\n+#define\tPCRF_CC_NUM_SKP_SYMS_LBN 8\n+#define\tPCRF_CC_NUM_SKP_SYMS_WIDTH 3\n+#define\tPCRF_AB_TS2_LBN 4\n+#define\tPCRF_AB_TS2_WIDTH 4\n+#define\tPCRF_AC_TS1_LBN 0\n+#define\tPCRF_AC_TS1_WIDTH 4\n+\n+\n+/*\n+ * PC_SYM_TMR_FLT_MSK_REG(16bit):\n+ * Symbol timer and Filter Mask Register\n+ */\n+\n+#define\tPCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCRF_CC_DEFAULT_FLT_MSK1_LBN 16\n+#define\tPCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16\n+#define\tPCRF_CC_FC_WDOG_TMR_DIS_LBN 15\n+#define\tPCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1\n+#define\tPCRF_CC_SI1_LBN 8\n+#define\tPCRF_CC_SI1_WIDTH 3\n+#define\tPCRF_CC_SKIP_INT_VAL_LBN 0\n+#define\tPCRF_CC_SKIP_INT_VAL_WIDTH 11\n+#define\tPCRF_CC_SI0_LBN 0\n+#define\tPCRF_CC_SI0_WIDTH 8\n+\n+\n+/*\n+ * PC_SYM_TMR_REG(16bit):\n+ * Symbol timer register\n+ */\n+\n+#define\tPCR_AB_SYM_TMR_REG 0x0000071c\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCRF_AB_ET_LBN 11\n+#define\tPCRF_AB_ET_WIDTH 4\n+#define\tPCRF_AB_SI1_LBN 8\n+#define\tPCRF_AB_SI1_WIDTH 3\n+#define\tPCRF_AB_SI0_LBN 0\n+#define\tPCRF_AB_SI0_WIDTH 8\n+\n+\n+/*\n+ * PC_FLT_MSK_REG(32bit):\n+ * Filter Mask Register 2\n+ */\n+\n+#define\tPCR_CC_FLT_MSK_REG 0x00000720\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCRF_CC_DEFAULT_FLT_MSK2_LBN 0\n+#define\tPCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32\n+\n+\n+/*\n+ * PC_PHY_STAT_REG(32bit):\n+ * PHY status register\n+ */\n+\n+#define\tPCR_AB_PHY_STAT_REG 0x00000720\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CC_PHY_STAT_REG 0x00000810\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_SSL_LBN 3\n+#define\tPCRF_AC_SSL_WIDTH 1\n+#define\tPCRF_AC_SSR_LBN 2\n+#define\tPCRF_AC_SSR_WIDTH 1\n+#define\tPCRF_AC_SSCL_LBN 1\n+#define\tPCRF_AC_SSCL_WIDTH 1\n+#define\tPCRF_AC_SSCD_LBN 0\n+#define\tPCRF_AC_SSCD_WIDTH 1\n+\n+\n+/*\n+ * PC_PHY_CTL_REG(32bit):\n+ * PHY control register\n+ */\n+\n+#define\tPCR_AB_PHY_CTL_REG 0x00000724\n+/* falcona0,falconb0=pci_f0_config */\n+\n+#define\tPCR_CC_PHY_CTL_REG 0x00000814\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_BD_LBN 31\n+#define\tPCRF_AC_BD_WIDTH 1\n+#define\tPCRF_AC_CDS_LBN 30\n+#define\tPCRF_AC_CDS_WIDTH 1\n+#define\tPCRF_AC_DWRAP_LB_LBN 29\n+#define\tPCRF_AC_DWRAP_LB_WIDTH 1\n+#define\tPCRF_AC_EBD_LBN 28\n+#define\tPCRF_AC_EBD_WIDTH 1\n+#define\tPCRF_AC_SNR_LBN 27\n+#define\tPCRF_AC_SNR_WIDTH 1\n+#define\tPCRF_AC_RX_NOT_DET_LBN 2\n+#define\tPCRF_AC_RX_NOT_DET_WIDTH 1\n+#define\tPCRF_AC_FORCE_LOS_VAL_LBN 1\n+#define\tPCRF_AC_FORCE_LOS_VAL_WIDTH 1\n+#define\tPCRF_AC_FORCE_LOS_EN_LBN 0\n+#define\tPCRF_AC_FORCE_LOS_EN_WIDTH 1\n+\n+\n+/*\n+ * PC_DEBUG0_REG(32bit):\n+ * Debug register 0\n+ */\n+\n+#define\tPCR_AC_DEBUG0_REG 0x00000728\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_CDI03_LBN 24\n+#define\tPCRF_AC_CDI03_WIDTH 8\n+#define\tPCRF_AC_CDI0_LBN 0\n+#define\tPCRF_AC_CDI0_WIDTH 32\n+#define\tPCRF_AC_CDI02_LBN 16\n+#define\tPCRF_AC_CDI02_WIDTH 8\n+#define\tPCRF_AC_CDI01_LBN 8\n+#define\tPCRF_AC_CDI01_WIDTH 8\n+#define\tPCRF_AC_CDI00_LBN 0\n+#define\tPCRF_AC_CDI00_WIDTH 8\n+\n+\n+/*\n+ * PC_DEBUG1_REG(32bit):\n+ * Debug register 1\n+ */\n+\n+#define\tPCR_AC_DEBUG1_REG 0x0000072c\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_CDI13_LBN 24\n+#define\tPCRF_AC_CDI13_WIDTH 8\n+#define\tPCRF_AC_CDI1_LBN 0\n+#define\tPCRF_AC_CDI1_WIDTH 32\n+#define\tPCRF_AC_CDI12_LBN 16\n+#define\tPCRF_AC_CDI12_WIDTH 8\n+#define\tPCRF_AC_CDI11_LBN 8\n+#define\tPCRF_AC_CDI11_WIDTH 8\n+#define\tPCRF_AC_CDI10_LBN 0\n+#define\tPCRF_AC_CDI10_WIDTH 8\n+\n+\n+/*\n+ * PC_XPFCC_STAT_REG(24bit):\n+ * documentation to be written for sum_PC_XPFCC_STAT_REG\n+ */\n+\n+#define\tPCR_AC_XPFCC_STAT_REG 0x00000730\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_XPDC_LBN 12\n+#define\tPCRF_AC_XPDC_WIDTH 8\n+#define\tPCRF_AC_XPHC_LBN 0\n+#define\tPCRF_AC_XPHC_WIDTH 12\n+\n+\n+/*\n+ * PC_XNPFCC_STAT_REG(24bit):\n+ * documentation to be written for sum_PC_XNPFCC_STAT_REG\n+ */\n+\n+#define\tPCR_AC_XNPFCC_STAT_REG 0x00000734\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_XNPDC_LBN 12\n+#define\tPCRF_AC_XNPDC_WIDTH 8\n+#define\tPCRF_AC_XNPHC_LBN 0\n+#define\tPCRF_AC_XNPHC_WIDTH 12\n+\n+\n+/*\n+ * PC_XCFCC_STAT_REG(24bit):\n+ * documentation to be written for sum_PC_XCFCC_STAT_REG\n+ */\n+\n+#define\tPCR_AC_XCFCC_STAT_REG 0x00000738\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_XCDC_LBN 12\n+#define\tPCRF_AC_XCDC_WIDTH 8\n+#define\tPCRF_AC_XCHC_LBN 0\n+#define\tPCRF_AC_XCHC_WIDTH 12\n+\n+\n+/*\n+ * PC_Q_STAT_REG(8bit):\n+ * documentation to be written for sum_PC_Q_STAT_REG\n+ */\n+\n+#define\tPCR_AC_Q_STAT_REG 0x0000073c\n+/* falcona0,falconb0,sienaa0=pci_f0_config */\n+\n+#define\tPCRF_AC_RQNE_LBN 2\n+#define\tPCRF_AC_RQNE_WIDTH 1\n+#define\tPCRF_AC_XRNE_LBN 1\n+#define\tPCRF_AC_XRNE_WIDTH 1\n+#define\tPCRF_AC_RCNR_LBN 0\n+#define\tPCRF_AC_RCNR_WIDTH 1\n+\n+\n+/*\n+ * PC_VC_XMIT_ARB1_REG(32bit):\n+ * VC Transmit Arbitration Register 1\n+ */\n+\n+#define\tPCR_CC_VC_XMIT_ARB1_REG 0x00000740\n+/* sienaa0=pci_f0_config */\n+\n+\n+\n+/*\n+ * PC_VC_XMIT_ARB2_REG(32bit):\n+ * VC Transmit Arbitration Register 2\n+ */\n+\n+#define\tPCR_CC_VC_XMIT_ARB2_REG 0x00000744\n+/* sienaa0=pci_f0_config */\n+\n+\n+\n+/*\n+ * PC_VC0_P_RQ_CTL_REG(32bit):\n+ * VC0 Posted Receive Queue Control\n+ */\n+\n+#define\tPCR_CC_VC0_P_RQ_CTL_REG 0x00000748\n+/* sienaa0=pci_f0_config */\n+\n+\n+\n+/*\n+ * PC_VC0_NP_RQ_CTL_REG(32bit):\n+ * VC0 Non-Posted Receive Queue Control\n+ */\n+\n+#define\tPCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c\n+/* sienaa0=pci_f0_config */\n+\n+\n+\n+/*\n+ * PC_VC0_C_RQ_CTL_REG(32bit):\n+ * VC0 Completion Receive Queue Control\n+ */\n+\n+#define\tPCR_CC_VC0_C_RQ_CTL_REG 0x00000750\n+/* sienaa0=pci_f0_config */\n+\n+\n+\n+/*\n+ * PC_GEN2_REG(32bit):\n+ * Gen2 Register\n+ */\n+\n+#define\tPCR_CC_GEN2_REG 0x0000080c\n+/* sienaa0=pci_f0_config */\n+\n+#define\tPCRF_CC_SET_DE_EMPHASIS_LBN 20\n+#define\tPCRF_CC_SET_DE_EMPHASIS_WIDTH 1\n+#define\tPCRF_CC_CFG_TX_COMPLIANCE_LBN 19\n+#define\tPCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1\n+#define\tPCRF_CC_CFG_TX_SWING_LBN 18\n+#define\tPCRF_CC_CFG_TX_SWING_WIDTH 1\n+#define\tPCRF_CC_DIR_SPEED_CHANGE_LBN 17\n+#define\tPCRF_CC_DIR_SPEED_CHANGE_WIDTH 1\n+#define\tPCRF_CC_LANE_ENABLE_LBN 8\n+#define\tPCRF_CC_LANE_ENABLE_WIDTH 9\n+#define\tPCRF_CC_NUM_FTS_LBN 0\n+#define\tPCRF_CC_NUM_FTS_WIDTH 8\n+\n+\n+#ifdef\t__cplusplus\n+}\n+#endif\n+\n+#endif /* _SYS_EFX_REGS_PCI_H */\n",
    "prefixes": [
        "dpdk-dev",
        "03/56"
    ]
}