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{
    "id": 15300,
    "url": "http://patches.dpdk.org/api/patches/15300/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1472155518-853-4-git-send-email-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1472155518-853-4-git-send-email-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1472155518-853-4-git-send-email-qi.z.zhang@intel.com",
    "date": "2016-08-25T20:05:09",
    "name": "[dpdk-dev,03/12] net/i40e/base: define macros for PHY type cap",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "fc8757cd8ebe75b588889a08e69f3e5e94fef146",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 10,
        "url": "http://patches.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1472155518-853-4-git-send-email-qi.z.zhang@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/15300/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/15300/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 7C5775688;\n\tThu, 25 Aug 2016 10:06:11 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 4F49E5681\n\tfor <dev@dpdk.org>; Thu, 25 Aug 2016 10:06:06 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga101.fm.intel.com with ESMTP; 25 Aug 2016 01:06:06 -0700",
            "from unknown (HELO localhost.localdomain.sh.intel.com)\n\t([10.239.129.103])\n\tby FMSMGA003.fm.intel.com with ESMTP; 25 Aug 2016 01:06:04 -0700"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.28,574,1464678000\"; d=\"scan'208\";a=\"753271283\"",
        "From": "Zhang Qi <qi.z.zhang@intel.com>",
        "To": "jingjing.wu@intel.com,\n\thelin.zhang@intel.com",
        "Cc": "dev@dpdk.org,\n\tZhang Qi <qi.z.zhang@intel.com>",
        "Date": "Thu, 25 Aug 2016 16:05:09 -0400",
        "Message-Id": "<1472155518-853-4-git-send-email-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1472155518-853-1-git-send-email-qi.z.zhang@intel.com>",
        "References": "<1472155518-853-1-git-send-email-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 03/12] net/i40e/base: define macros for PHY type\n\tcap",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Define macros for PHY type capabilities to replace exist enum type.\n\nSigned-off-by: Zhang Qi <qi.z.zhang@intel.com>\n---\n drivers/net/i40e/base/i40e_type.h | 60 +++++++++++++++++++--------------------\n 1 file changed, 29 insertions(+), 31 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h\nindex 5349419..51abc37 100644\n--- a/drivers/net/i40e/base/i40e_type.h\n+++ b/drivers/net/i40e/base/i40e_type.h\n@@ -292,37 +292,6 @@ struct i40e_link_status {\n #define I40E_MODULE_TYPE_1000BASE_T\t0x08\n };\n \n-enum i40e_aq_capabilities_phy_type {\n-\tI40E_CAP_PHY_TYPE_SGMII\t\t\t= BIT(I40E_PHY_TYPE_SGMII),\n-\tI40E_CAP_PHY_TYPE_1000BASE_KX\t\t= BIT(I40E_PHY_TYPE_1000BASE_KX),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KX4\t\t= BIT(I40E_PHY_TYPE_10GBASE_KX4),\n-\tI40E_CAP_PHY_TYPE_10GBASE_KR\t\t= BIT(I40E_PHY_TYPE_10GBASE_KR),\n-\tI40E_CAP_PHY_TYPE_40GBASE_KR4\t\t= BIT(I40E_PHY_TYPE_40GBASE_KR4),\n-\tI40E_CAP_PHY_TYPE_XAUI\t\t\t= BIT(I40E_PHY_TYPE_XAUI),\n-\tI40E_CAP_PHY_TYPE_XFI\t\t\t= BIT(I40E_PHY_TYPE_XFI),\n-\tI40E_CAP_PHY_TYPE_SFI\t\t\t= BIT(I40E_PHY_TYPE_SFI),\n-\tI40E_CAP_PHY_TYPE_XLAUI\t\t\t= BIT(I40E_PHY_TYPE_XLAUI),\n-\tI40E_CAP_PHY_TYPE_XLPPI\t\t\t= BIT(I40E_PHY_TYPE_XLPPI),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4_CU\t= BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1_CU\t= BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_AOC\t\t= BIT(I40E_PHY_TYPE_10GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_40GBASE_AOC\t\t= BIT(I40E_PHY_TYPE_40GBASE_AOC),\n-\tI40E_CAP_PHY_TYPE_100BASE_TX\t\t= BIT(I40E_PHY_TYPE_100BASE_TX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T\t\t= BIT(I40E_PHY_TYPE_1000BASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_T\t\t= BIT(I40E_PHY_TYPE_10GBASE_T),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SR\t\t= BIT(I40E_PHY_TYPE_10GBASE_SR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_LR\t\t= BIT(I40E_PHY_TYPE_10GBASE_LR),\n-\tI40E_CAP_PHY_TYPE_10GBASE_SFPP_CU\t= BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),\n-\tI40E_CAP_PHY_TYPE_10GBASE_CR1\t\t= BIT(I40E_PHY_TYPE_10GBASE_CR1),\n-\tI40E_CAP_PHY_TYPE_40GBASE_CR4\t\t= BIT(I40E_PHY_TYPE_40GBASE_CR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_SR4\t\t= BIT(I40E_PHY_TYPE_40GBASE_SR4),\n-\tI40E_CAP_PHY_TYPE_40GBASE_LR4\t\t= BIT(I40E_PHY_TYPE_40GBASE_LR4),\n-\tI40E_CAP_PHY_TYPE_1000BASE_SX\t\t= BIT(I40E_PHY_TYPE_1000BASE_SX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_LX\t\t= BIT(I40E_PHY_TYPE_1000BASE_LX),\n-\tI40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL\t= BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),\n-\tI40E_CAP_PHY_TYPE_20GBASE_KR2\t\t= BIT(I40E_PHY_TYPE_20GBASE_KR2)\n-};\n-\n struct i40e_phy_info {\n \tstruct i40e_link_status link_info;\n \tstruct i40e_link_status link_info_old;\n@@ -332,6 +301,35 @@ struct i40e_phy_info {\n \tu32 phy_types;\n };\n \n+#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)\n+#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)\n+#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)\n+#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)\n+#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)\n+#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)\n+#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)\n+#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)\n+#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)\n+#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)\n+#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)\n+#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)\n+#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)\n+#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)\n+#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)\n+#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)\n+#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)\n #define I40E_HW_CAP_MAX_GPIO\t\t\t30\n #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO\t\t0\n #define I40E_HW_CAP_MDIO_PORT_MODE_I2C\t\t1\n",
    "prefixes": [
        "dpdk-dev",
        "03/12"
    ]
}