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GET /api/patches/139981/?format=api
{ "id": 139981, "url": "http://patches.dpdk.org/api/patches/139981/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-18-venkatkumar.ande@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240507124305.2318-18-venkatkumar.ande@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240507124305.2318-18-venkatkumar.ande@amd.com", "date": "2024-05-07T12:42:58", "name": "[v2,18/25] net/axgbe: add support for 10 Mbps speed", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8da44a2f436cfd122bede3922a22b3bf37299bf6", "submitter": { "id": 3256, "url": "http://patches.dpdk.org/api/people/3256/?format=api", "name": "Venkat Kumar Ande", "email": "venkatkumar.ande@amd.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-18-venkatkumar.ande@amd.com/mbox/", "series": [ { "id": 31890, "url": "http://patches.dpdk.org/api/series/31890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31890", "date": "2024-05-07T12:42:41", "name": "[v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs", "version": 2, "mbox": "http://patches.dpdk.org/series/31890/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139981/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/139981/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 736B943FC9;\n\tTue, 7 May 2024 14:45:46 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 97123433F4;\n\tTue, 7 May 2024 14:44:30 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2082.outbound.protection.outlook.com [40.107.223.82])\n by mails.dpdk.org (Postfix) with ESMTP id DC33F433ED\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Venkat Kumar Ande <venkatkumar.ande@amd.com>", "To": "<dev@dpdk.org>", "CC": "<Selwin.Sebastian@amd.com>, Venkat Kumar Ande <venkatkumar.ande@amd.com>", "Subject": "[PATCH v2 18/25] net/axgbe: add support for 10 Mbps speed", "Date": "Tue, 7 May 2024 18:12:58 +0530", "Message-ID": "<20240507124305.2318-18-venkatkumar.ande@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240507124305.2318-1-venkatkumar.ande@amd.com>", "References": "<20240412125013.10498-1-VenkatKumar.Ande@amd.com>\n <20240507124305.2318-1-venkatkumar.ande@amd.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF00036F42:EE_|IA1PR12MB8288:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d85f9fb7-3de1-4659-a0bd-08dc6e936ce0", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|376005|36860700004|82310400017|1800799015;", "X-Microsoft-Antispam-Message-Info": "\n LOz7p283Tw7NZHLjevTfPQzu37kaedcWtHZY5WSFI+L0bXu8m9bt0V0x0yAoch9xT7Ji/YjxYWiidNP22Ks7dqPoRB5kDks2omrN7rurVkZH4qReJhdTVSh13VxMO6JiFSAqq8Pg44uODSeW81k4/NnZfuDlDknqPUVDMtfUj7G9MowvErXgfkD4sVDLZPqGexZM2v1uK5S+rTy+KS72lIji/X19NsEVcyyNueVf1x5n6LPoyVpnNhuo2FFaoHz1HzHRMsQQ3oNGdoXdOtIxE+/tw1VljUOoJSLO7OIO1tnfp4OJ8GZz94+Jz9p6VX+LilnuuXk/LTrfYkoQP43WS/VTEQ78zmZ25dd/OYgWRKWvBPcmrDFrR0gBtxc6as77iEnvr+MpVgNomH6wPc6SvVXHiu21A+xtDQ63Lgib8SKtX9P1H/wVK+kY78a22OU52fSYThZkrAM/e3KfZ/vjMw1+JVkY/Ehf6krJFHfhyddUwzvqL86OoBBylcW4aB0Qmr0ybhBOBTeznNpoqA5RN91QDSTOwsYeJxOWTiIumz9WqEKjROzuJBD8QBn2AL06GXrcOO7P/YXbn7LF5IL6KUFukHtTjR3CIEJYs2Qjxxka3JmJofnUhG1wjRd1D/LS7EnHdJsbgXSH/63GL5xJfQtn927c6mttEbjb1anbLNpUwNIS5BKF9hzNP/a5QVV7A4VbHIzz77darqedAx2uXxMm5ArGLdd55eIdXMP6ypJYKQnRGo8AmDrlZpuwfnJ/kNQT+s9+rT5X2urOcbDzxX0gYIXQCIiviLWlRDSQhgD7NC6F9c/OjTR7tn2UiT5LJelHiGD/vfA8dX+NVjsXJLAMSP8Xgr6nHVVh7nqDoWEhKJCAWBMAUaZAj+8T0R44y4AACGKuCl8fQrAxH1GmsEl0C9F10LN2eXzDcvVLPQLMjHE84f7zuopeBlM2hxAk/mxRpCjMTbJMMoVm7o+P7iYeKhkBuW4ZjKN5vBnovle6U6aCYKP4SzO7tnrQmeM7gnXWT4GMFJo93KYLD3seB9KSQ0VjOpBPLgWSKmiHY0fAT32ITLR0wTYBxlFQLiR6+k7odootMob7DMT2b7awbYbtaVpjlOv1GKRPZ0yMN7RyLgAMoKQWvtmiMlEXNTTdCnWDqwyRHB5z52EB2B/1wcfhtw/OLe+rQQh1mr+tuiJ1NURP3n13tatr+rx/dqgkTiXFPzgOyjOUfObGnTQq5yzPLO4EbVXRr+XkPQC/K48y6o0DPl44htDqoz1zz9sVNVxXlRL+PHMD1VBsSHWdc0aeiTOuaJsQVO87fr7HygFBFMu337NcCpwj0knIP2U8bOvAIOz4QdIrikGKvtsfwaG6cb0FLCrARusVxFOvU/c=", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(376005)(36860700004)(82310400017)(1800799015); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2024 12:44:24.4894 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d85f9fb7-3de1-4659-a0bd-08dc6e936ce0", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF00036F42.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8288", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add the necessary changes to support 10 Mbps speed for BaseT and SFP\nport modes. This is supported in MAC ver >= 30H.\n\nSigned-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>\n---\n drivers/net/axgbe/axgbe_dev.c | 3 ++\n drivers/net/axgbe/axgbe_ethdev.h | 2 +\n drivers/net/axgbe/axgbe_mdio.c | 22 +++++++++\n drivers/net/axgbe/axgbe_phy.h | 2 +\n drivers/net/axgbe/axgbe_phy_impl.c | 75 ++++++++++++++++++++++++++++--\n 5 files changed, 100 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c\nindex 5233633a53..6b413160c2 100644\n--- a/drivers/net/axgbe/axgbe_dev.c\n+++ b/drivers/net/axgbe/axgbe_dev.c\n@@ -250,6 +250,9 @@ static int axgbe_set_speed(struct axgbe_port *pdata, int speed)\n \tunsigned int ss;\n \n \tswitch (speed) {\n+\tcase SPEED_10:\n+\t\tss = 0x07;\n+\t\tbreak;\n \tcase SPEED_1000:\n \t\tss = 0x03;\n \t\tbreak;\ndiff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h\nindex 6dc1c1274b..4dcbf6d9a2 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.h\n+++ b/drivers/net/axgbe/axgbe_ethdev.h\n@@ -115,6 +115,7 @@\n \n #define AXGBE_SGMII_AN_LINK_STATUS\tBIT(1)\n #define AXGBE_SGMII_AN_LINK_SPEED\t(BIT(2) | BIT(3))\n+#define AXGBE_SGMII_AN_LINK_SPEED_10\t0x00\n #define AXGBE_SGMII_AN_LINK_SPEED_100\t0x04\n #define AXGBE_SGMII_AN_LINK_SPEED_1000\t0x08\n #define AXGBE_SGMII_AN_LINK_DUPLEX\tBIT(4)\n@@ -214,6 +215,7 @@ enum axgbe_mode {\n \tAXGBE_MODE_KX_2500,\n \tAXGBE_MODE_KR,\n \tAXGBE_MODE_X,\n+\tAXGBE_MODE_SGMII_10,\n \tAXGBE_MODE_SGMII_100,\n \tAXGBE_MODE_SGMII_1000,\n \tAXGBE_MODE_SFI,\ndiff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c\nindex faa7cdbf0a..9fe30e83bc 100644\n--- a/drivers/net/axgbe/axgbe_mdio.c\n+++ b/drivers/net/axgbe/axgbe_mdio.c\n@@ -143,6 +143,15 @@ static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)\n \tpdata->phy_if.phy_impl.set_mode(pdata, AXGBE_MODE_SGMII_1000);\n }\n \n+static void axgbe_sgmii_10_mode(struct axgbe_port *pdata)\n+{\n+\t/* Set MAC to 10M speed */\n+\tpdata->hw_if.set_speed(pdata, SPEED_10);\n+\n+\t/* Call PHY implementation support to complete rate change */\n+\tpdata->phy_if.phy_impl.set_mode(pdata, AXGBE_MODE_SGMII_10);\n+}\n+\n static void axgbe_sgmii_100_mode(struct axgbe_port *pdata)\n {\n \n@@ -176,6 +185,9 @@ static void axgbe_change_mode(struct axgbe_port *pdata,\n \tcase AXGBE_MODE_KR:\n \t\taxgbe_kr_mode(pdata);\n \t\tbreak;\n+\tcase AXGBE_MODE_SGMII_10:\n+\t\taxgbe_sgmii_10_mode(pdata);\n+\t\tbreak;\n \tcase AXGBE_MODE_SGMII_100:\n \t\taxgbe_sgmii_100_mode(pdata);\n \t\tbreak;\n@@ -864,6 +876,7 @@ static int axgbe_phy_config_fixed(struct axgbe_port *pdata)\n \tcase AXGBE_MODE_KX_1000:\n \tcase AXGBE_MODE_KX_2500:\n \tcase AXGBE_MODE_KR:\n+\tcase AXGBE_MODE_SGMII_10:\n \tcase AXGBE_MODE_SGMII_100:\n \tcase AXGBE_MODE_SGMII_1000:\n \tcase AXGBE_MODE_X:\n@@ -923,6 +936,8 @@ static int __axgbe_phy_config_aneg(struct axgbe_port *pdata, bool set_mode)\n \t\t\taxgbe_set_mode(pdata, AXGBE_MODE_SGMII_1000);\n \t\t} else if (axgbe_use_mode(pdata, AXGBE_MODE_SGMII_100)) {\n \t\t\taxgbe_set_mode(pdata, AXGBE_MODE_SGMII_100);\n+\t\t} else if (axgbe_use_mode(pdata, AXGBE_MODE_SGMII_10)) {\n+\t\t\taxgbe_set_mode(pdata, AXGBE_MODE_SGMII_10);\n \t\t} else {\n \t\t\trte_intr_enable(pdata->pci_dev->intr_handle);\n \t\t\tret = -EINVAL;\n@@ -1025,6 +1040,9 @@ static void axgbe_phy_status_result(struct axgbe_port *pdata)\n \t\tmode = axgbe_phy_status_aneg(pdata);\n \n \tswitch (mode) {\n+\tcase AXGBE_MODE_SGMII_10:\n+\t\tpdata->phy.speed = SPEED_10;\n+\t\tbreak;\n \tcase AXGBE_MODE_SGMII_100:\n \t\tpdata->phy.speed = SPEED_100;\n \t\tbreak;\n@@ -1173,6 +1191,8 @@ static int axgbe_phy_start(struct axgbe_port *pdata)\n \t\taxgbe_sgmii_1000_mode(pdata);\n \t} else if (axgbe_use_mode(pdata, AXGBE_MODE_SGMII_100)) {\n \t\taxgbe_sgmii_100_mode(pdata);\n+\t} else if (axgbe_use_mode(pdata, AXGBE_MODE_SGMII_10)) {\n+\t\taxgbe_sgmii_10_mode(pdata);\n \t} else {\n \t\tret = -EINVAL;\n \t\tgoto err_stop;\n@@ -1220,6 +1240,8 @@ static int axgbe_phy_best_advertised_speed(struct axgbe_port *pdata)\n \t\treturn SPEED_1000;\n \telse if (pdata->phy.advertising & ADVERTISED_100baseT_Full)\n \t\treturn SPEED_100;\n+\telse if (pdata->phy.advertising & ADVERTISED_10baseT_Full)\n+\t\treturn SPEED_10;\n \n \treturn SPEED_UNKNOWN;\n }\ndiff --git a/drivers/net/axgbe/axgbe_phy.h b/drivers/net/axgbe/axgbe_phy.h\nindex 77ee20a31a..5b844e81cd 100644\n--- a/drivers/net/axgbe/axgbe_phy.h\n+++ b/drivers/net/axgbe/axgbe_phy.h\n@@ -168,6 +168,7 @@\n #define ADVERTISED_1000baseKX_Full\t(1 << 17)\n #define ADVERTISED_1000baseT_Full\t(1 << 5)\n #define ADVERTISED_100baseT_Full\t(1 << 3)\n+#define ADVERTISED_10baseT_Full\t\t(1 << 2)\n #define ADVERTISED_TP\t\t\t(1 << 7)\n #define ADVERTISED_FIBRE\t\t(1 << 10)\n #define ADVERTISED_Backplane (1 << 16)\n@@ -175,6 +176,7 @@\n #define SUPPORTED_1000baseKX_Full (1 << 17)\n #define SUPPORTED_10000baseKR_Full (1 << 19)\n #define SUPPORTED_2500baseX_Full\t(1 << 15)\n+#define SUPPORTED_10baseT_Full\t\t(1 << 3)\n #define SUPPORTED_100baseT_Full (1 << 2)\n #define SUPPORTED_1000baseT_Full (1 << 5)\n #define SUPPORTED_10000baseT_Full (1 << 12)\ndiff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c\nindex 67a18e7c55..9c2c411b4f 100644\n--- a/drivers/net/axgbe/axgbe_phy_impl.c\n+++ b/drivers/net/axgbe/axgbe_phy_impl.c\n@@ -7,6 +7,7 @@\n #include \"axgbe_common.h\"\n #include \"axgbe_phy.h\"\n \n+#define AXGBE_PHY_PORT_SPEED_10\t\tBIT(0)\n #define AXGBE_PHY_PORT_SPEED_100\tBIT(1)\n #define AXGBE_PHY_PORT_SPEED_1000\tBIT(2)\n #define AXGBE_PHY_PORT_SPEED_2500\tBIT(3)\n@@ -490,6 +491,8 @@ static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)\n \n \tswitch (phy_data->sfp_speed) {\n \tcase AXGBE_SFP_SPEED_100_1000:\n+\t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10)\n+\t\t\tpdata->phy.advertising |= ADVERTISED_10baseT_Full;\n \t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)\n \t\t\tpdata->phy.advertising |= ADVERTISED_100baseT_Full;\n \t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)\n@@ -511,6 +514,8 @@ static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata)\n \t\t\tpdata->phy.advertising |= ADVERTISED_1000baseT_Full;\n \t\telse if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100)\n \t\t\tpdata->phy.advertising |= ADVERTISED_100baseT_Full;\n+\t\telse if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10)\n+\t\t\tpdata->phy.advertising |= ADVERTISED_10baseT_Full;\n \t}\n }\n \n@@ -980,6 +985,14 @@ static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata)\n \t\taxgbe_phy_phydev_flowctrl(pdata);\n \n \tswitch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) {\n+\tcase AXGBE_SGMII_AN_LINK_SPEED_10:\n+\t\tif (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {\n+\t\t\tpdata->phy.lp_advertising |= ADVERTISED_10baseT_Full;\n+\t\t\tmode = AXGBE_MODE_SGMII_10;\n+\t\t} else {\n+\t\t\tmode = AXGBE_MODE_UNKNOWN;\n+\t\t}\n+\t\tbreak;\n \tcase AXGBE_SGMII_AN_LINK_SPEED_100:\n \t\tif (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {\n \t\t\tpdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;\n@@ -1347,6 +1360,18 @@ static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata)\n \tphy_data->cur_mode = AXGBE_MODE_SGMII_1000;\n }\n \n+static void axgbe_phy_sgmii_10_mode(struct axgbe_port *pdata)\n+{\n+\tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n+\n+\taxgbe_phy_set_redrv_mode(pdata);\n+\n+\t/* 10M/SGMII */\n+\taxgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_1G, AXGBE_MB_SUBCMD_10MBITS);\n+\n+\tphy_data->cur_mode = AXGBE_MODE_SGMII_10;\n+}\n+\n static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata)\n {\n \tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n@@ -1363,6 +1388,7 @@ static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata)\n \t\treturn axgbe_phy_cur_mode(pdata);\n \n \tswitch (axgbe_phy_cur_mode(pdata)) {\n+\tcase AXGBE_MODE_SGMII_10:\n \tcase AXGBE_MODE_SGMII_100:\n \tcase AXGBE_MODE_SGMII_1000:\n \t\treturn AXGBE_MODE_KR;\n@@ -1433,6 +1459,8 @@ static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data\n \t\t\t\t\t\tint speed)\n {\n \tswitch (speed) {\n+\tcase SPEED_10:\n+\t\treturn AXGBE_MODE_SGMII_10;\n \tcase SPEED_100:\n \t\treturn AXGBE_MODE_SGMII_100;\n \tcase SPEED_1000:\n@@ -1448,6 +1476,8 @@ static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data,\n \t\t\t\t\t int speed)\n {\n \tswitch (speed) {\n+\tcase SPEED_10:\n+\t\treturn AXGBE_MODE_SGMII_10;\n \tcase SPEED_100:\n \t\treturn AXGBE_MODE_SGMII_100;\n \tcase SPEED_1000:\n@@ -1525,6 +1555,9 @@ static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode)\n \tcase AXGBE_MODE_SGMII_1000:\n \t\taxgbe_phy_sgmii_1000_mode(pdata);\n \t\tbreak;\n+\tcase AXGBE_MODE_SGMII_10:\n+\t\taxgbe_phy_sgmii_10_mode(pdata);\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -1566,6 +1599,9 @@ static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata,\n \t\t\t\t enum axgbe_mode mode)\n {\n \tswitch (mode) {\n+\tcase AXGBE_MODE_SGMII_10:\n+\t\treturn axgbe_phy_check_mode(pdata, mode,\n+\t\t\t\t\t ADVERTISED_10baseT_Full);\n \tcase AXGBE_MODE_SGMII_100:\n \t\treturn axgbe_phy_check_mode(pdata, mode,\n \t\t\t\t\t ADVERTISED_100baseT_Full);\n@@ -1591,6 +1627,11 @@ static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata,\n \t\t\treturn false;\n \t\treturn axgbe_phy_check_mode(pdata, mode,\n \t\t\t\t\t ADVERTISED_1000baseT_Full);\n+\tcase AXGBE_MODE_SGMII_10:\n+\t\tif (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)\n+\t\t\treturn false;\n+\t\treturn axgbe_phy_check_mode(pdata, mode,\n+\t\t\t\t\t ADVERTISED_10baseT_Full);\n \tcase AXGBE_MODE_SGMII_100:\n \t\tif (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T)\n \t\t\treturn false;\n@@ -1803,6 +1844,12 @@ static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)\n static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)\n {\n \tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n+\tunsigned int ver;\n+\n+\t/* 10 Mbps speed is not supported in ver < 30H */\n+\tver = AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER);\n+\tif (ver < 0x30 && phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10)\n+\t\treturn true;\n \n \tswitch (phy_data->port_mode) {\n \tcase AXGBE_PORT_MODE_BACKPLANE:\n@@ -1816,7 +1863,8 @@ static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)\n \t\t\treturn false;\n \t\tbreak;\n \tcase AXGBE_PORT_MODE_1000BASE_T:\n-\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n+\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) ||\n+\t\t\t(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n \t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000))\n \t\t\treturn false;\n \t\tbreak;\n@@ -1825,13 +1873,15 @@ static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)\n \t\t\treturn false;\n \t\tbreak;\n \tcase AXGBE_PORT_MODE_NBASE_T:\n-\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n+\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) ||\n+\t\t\t(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n \t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||\n \t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500))\n \t\t\treturn false;\n \t\tbreak;\n \tcase AXGBE_PORT_MODE_10GBASE_T:\n-\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n+\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) ||\n+\t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n \t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||\n \t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))\n \t\t\treturn false;\n@@ -1841,7 +1891,8 @@ static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)\n \t\t\treturn false;\n \t\tbreak;\n \tcase AXGBE_PORT_MODE_SFP:\n-\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n+\t\tif ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) ||\n+\t\t\t(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) ||\n \t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||\n \t\t (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000))\n \t\t\treturn false;\n@@ -2150,6 +2201,10 @@ static int axgbe_phy_init(struct axgbe_port *pdata)\n \t\tpdata->phy.supported |= SUPPORTED_Autoneg;\n \t\tpdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;\n \t\tpdata->phy.supported |= SUPPORTED_TP;\n+\t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) {\n+\t\t\tpdata->phy.supported |= SUPPORTED_10baseT_Full;\n+\t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_10;\n+\t\t}\n \t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {\n \t\t\tpdata->phy.supported |= SUPPORTED_100baseT_Full;\n \t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_100;\n@@ -2178,6 +2233,10 @@ static int axgbe_phy_init(struct axgbe_port *pdata)\n \t\tpdata->phy.supported |= SUPPORTED_Autoneg;\n \t\tpdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;\n \t\tpdata->phy.supported |= SUPPORTED_TP;\n+\t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) {\n+\t\t\tpdata->phy.supported |= SUPPORTED_10baseT_Full;\n+\t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_10;\n+\t\t}\n \t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {\n \t\t\tpdata->phy.supported |= SUPPORTED_100baseT_Full;\n \t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_100;\n@@ -2199,6 +2258,10 @@ static int axgbe_phy_init(struct axgbe_port *pdata)\n \t\tpdata->phy.supported |= SUPPORTED_Autoneg;\n \t\tpdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;\n \t\tpdata->phy.supported |= SUPPORTED_TP;\n+\t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) {\n+\t\t\tpdata->phy.supported |= SUPPORTED_10baseT_Full;\n+\t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_10;\n+\t\t}\n \t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {\n \t\t\tpdata->phy.supported |= SUPPORTED_100baseT_Full;\n \t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_100;\n@@ -2234,6 +2297,10 @@ static int axgbe_phy_init(struct axgbe_port *pdata)\n \t\tpdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;\n \t\tpdata->phy.supported |= SUPPORTED_TP;\n \t\tpdata->phy.supported |= SUPPORTED_FIBRE;\n+\t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) {\n+\t\t\tpdata->phy.supported |= SUPPORTED_10baseT_Full;\n+\t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_10;\n+\t\t}\n \t\tif (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) {\n \t\t\tpdata->phy.supported |= SUPPORTED_100baseT_Full;\n \t\t\tphy_data->start_mode = AXGBE_MODE_SGMII_100;\n", "prefixes": [ "v2", "18/25" ] }