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GET /api/patches/139976/?format=api
{ "id": 139976, "url": "http://patches.dpdk.org/api/patches/139976/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-11-venkatkumar.ande@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240507124305.2318-11-venkatkumar.ande@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240507124305.2318-11-venkatkumar.ande@amd.com", "date": "2024-05-07T12:42:51", "name": "[v2,11/25] net/axgbe: flow Tx Ctrl Registers are h/w version dependent", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "baea71f55831d675029b3c2baa0fa6a0c7e07c58", "submitter": { "id": 3256, "url": "http://patches.dpdk.org/api/people/3256/?format=api", "name": "Venkat Kumar Ande", "email": "venkatkumar.ande@amd.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-11-venkatkumar.ande@amd.com/mbox/", "series": [ { "id": 31890, "url": "http://patches.dpdk.org/api/series/31890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31890", "date": "2024-05-07T12:42:41", "name": "[v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs", "version": 2, "mbox": "http://patches.dpdk.org/series/31890/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139976/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139976/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D926F43FC9;\n\tTue, 7 May 2024 14:45:15 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D9316433DB;\n\tTue, 7 May 2024 14:44:13 +0200 (CEST)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2057.outbound.protection.outlook.com [40.107.237.57])\n by mails.dpdk.org (Postfix) with ESMTP id F2F34433CF;\n Tue, 7 May 2024 14:44:09 +0200 (CEST)", "from SA9PR13CA0038.namprd13.prod.outlook.com (2603:10b6:806:22::13)\n by CH3PR12MB8972.namprd12.prod.outlook.com (2603:10b6:610:169::11)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.42; 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CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(1800799015)(82310400017)(376005)(36860700004); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2024 12:44:01.0683 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8d3b6a86-ee5e-4ba8-d8d7-08dc6e935eea", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF00036F3E.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8972", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "There is difference in the TX Flow Control registers (TFCR) between the\nrevisions of the hardware. The older revisions of hardware used to have\nsingle register per queue. Whereas, the newer revision of hardware (from\nver 30H onwards) have one register per priority.\n\nWithout the fix the user will face problem in TX operation on new 30H HW\n\nFixes: 7c4158a5b592 (\"net/axgbe: add DMA programming and start/stop\")\nCc: stable@dpdk.org\n\nSigned-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>\n---\n drivers/net/axgbe/axgbe_dev.c | 25 +++++++++++++++----------\n 1 file changed, 15 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c\nindex 9b0073eea6..5233633a53 100644\n--- a/drivers/net/axgbe/axgbe_dev.c\n+++ b/drivers/net/axgbe/axgbe_dev.c\n@@ -269,20 +269,28 @@ static int axgbe_set_speed(struct axgbe_port *pdata, int speed)\n \treturn 0;\n }\n \n+static unsigned int axgbe_get_fc_queue_count(struct axgbe_port *pdata)\n+{\n+\tunsigned int max_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;\n+\n+\t/* From MAC ver 30H the TFCR is per priority, instead of per queue */\n+\tif (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30)\n+\t\treturn max_q_count;\n+\telse\n+\t\treturn (RTE_MIN(pdata->tx_q_count, max_q_count));\n+}\n+\n static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata)\n {\n-\tunsigned int max_q_count, q_count;\n \tunsigned int reg, reg_val;\n-\tunsigned int i;\n+\tunsigned int i, q_count;\n \n \t/* Clear MTL flow control */\n \tfor (i = 0; i < pdata->rx_q_count; i++)\n \t\tAXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);\n \n \t/* Clear MAC flow control */\n-\tmax_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;\n-\tq_count = RTE_MIN(pdata->tx_q_count,\n-\t\t\tmax_q_count);\n+\tq_count = axgbe_get_fc_queue_count(pdata);\n \treg = MAC_Q0TFCR;\n \tfor (i = 0; i < q_count; i++) {\n \t\treg_val = AXGMAC_IOREAD(pdata, reg);\n@@ -297,9 +305,8 @@ static int axgbe_disable_tx_flow_control(struct axgbe_port *pdata)\n \n static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata)\n {\n-\tunsigned int max_q_count, q_count;\n \tunsigned int reg, reg_val;\n-\tunsigned int i;\n+\tunsigned int i, q_count;\n \n \t/* Set MTL flow control */\n \tfor (i = 0; i < pdata->rx_q_count; i++) {\n@@ -316,9 +323,7 @@ static int axgbe_enable_tx_flow_control(struct axgbe_port *pdata)\n \t}\n \n \t/* Set MAC flow control */\n-\tmax_q_count = AXGMAC_MAX_FLOW_CONTROL_QUEUES;\n-\tq_count = RTE_MIN(pdata->tx_q_count,\n-\t\t\tmax_q_count);\n+\tq_count = axgbe_get_fc_queue_count(pdata);\n \treg = MAC_Q0TFCR;\n \tfor (i = 0; i < q_count; i++) {\n \t\treg_val = AXGMAC_IOREAD(pdata, reg);\n", "prefixes": [ "v2", "11/25" ] }