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GET /api/patches/139967/?format=api
{ "id": 139967, "url": "http://patches.dpdk.org/api/patches/139967/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-4-venkatkumar.ande@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240507124305.2318-4-venkatkumar.ande@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240507124305.2318-4-venkatkumar.ande@amd.com", "date": "2024-05-07T12:42:44", "name": "[v2,04/25] net/axgbe: update DMA coherency values", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "48f5de059da847769f8b8fff09ff3642f480c6f8", "submitter": { "id": 3256, "url": "http://patches.dpdk.org/api/people/3256/?format=api", "name": "Venkat Kumar Ande", "email": "venkatkumar.ande@amd.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240507124305.2318-4-venkatkumar.ande@amd.com/mbox/", "series": [ { "id": 31890, "url": "http://patches.dpdk.org/api/series/31890/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31890", "date": "2024-05-07T12:42:41", "name": "[v2,01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs", "version": 2, "mbox": "http://patches.dpdk.org/series/31890/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139967/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139967/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 31F5343FC9;\n\tTue, 7 May 2024 14:44:06 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 30DF5433AA;\n\tTue, 7 May 2024 14:43:51 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2058.outbound.protection.outlook.com [40.107.243.58])\n by mails.dpdk.org (Postfix) with ESMTP id 6E5834338E;\n Tue, 7 May 2024 14:43:45 +0200 (CEST)", "from PH7P220CA0041.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:32b::27)\n by SA1PR12MB8118.namprd12.prod.outlook.com (2603:10b6:806:333::9)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7544.42; 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CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230031)(82310400017)(1800799015)(36860700004)(376005); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 May 2024 12:43:43.0904 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 90a2984c-677f-412a-a222-08dc6e935433", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF00036F43.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8118", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Based on the IOMMU configuration, the current cache control settings can\nresult in possible coherency issues. The hardware team has recommended\nnew settings for the PCI device path to eliminate the issue.\n\nWithout the fix the user will get incorrect data in TSO functionality\n\nFixes: 7c4158a5b592 (\"net/axgbe: add DMA programming and start/stop\")\nCc: stable@dpdk.org\n\nSigned-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>\n---\n drivers/net/axgbe/axgbe_dev.c | 20 +++++++++-----------\n 1 file changed, 9 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c\nindex 3389954aa6..9b0073eea6 100644\n--- a/drivers/net/axgbe/axgbe_dev.c\n+++ b/drivers/net/axgbe/axgbe_dev.c\n@@ -647,23 +647,21 @@ static void axgbe_config_dma_cache(struct axgbe_port *pdata)\n \tunsigned int arcache, awcache, arwcache;\n \n \tarcache = 0;\n-\tAXGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, 0x3);\n+\tAXGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, 0xf);\n+\tAXGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, 0xf);\n+\tAXGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, 0xf);\n \tAXGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);\n \n \tawcache = 0;\n-\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, 0x3);\n-\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, 0x3);\n-\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, 0x1);\n-\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, 0x3);\n-\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, 0x1);\n-\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDC, 0x3);\n-\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDD, 0x1);\n+\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, 0xf);\n+\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, 0xf);\n+\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, 0xf);\n+\tAXGMAC_SET_BITS(awcache, DMA_AXIAWCR, RDC, 0xf);\n \tAXGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);\n \n \tarwcache = 0;\n-\tAXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWD, 0x1);\n-\tAXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWC, 0x3);\n-\tAXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, RDRC, 0x3);\n+\tAXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, TDWC, 0xf);\n+\tAXGMAC_SET_BITS(arwcache, DMA_AXIAWRCR, RDRC, 0xf);\n \tAXGMAC_IOWRITE(pdata, DMA_AXIAWRCR, arwcache);\n }\n \n", "prefixes": [ "v2", "04/25" ] }