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GET /api/patches/139439/?format=api
{ "id": 139439, "url": "http://patches.dpdk.org/api/patches/139439/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240417072708.322-3-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240417072708.322-3-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240417072708.322-3-anoobj@marvell.com", "date": "2024-04-17T07:27:03", "name": "[v2,2/7] dma/odm: add hardware defines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "4cd78e9afe4c8615fa485ce61cd8f1fff7897d28", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240417072708.322-3-anoobj@marvell.com/mbox/", "series": [ { "id": 31766, "url": "http://patches.dpdk.org/api/series/31766/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31766", "date": "2024-04-17T07:27:01", "name": "Add ODM DMA device", "version": 2, "mbox": "http://patches.dpdk.org/series/31766/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139439/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139439/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 89BB543E8E;\n\tWed, 17 Apr 2024 09:27:41 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9E50B40A76;\n\tWed, 17 Apr 2024 09:27:35 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id E149D40A6D\n for <dev@dpdk.org>; Wed, 17 Apr 2024 09:27:33 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 43GK1xui017063; Wed, 17 Apr 2024 00:27:33 -0700", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3xhfdn5btq-11\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Wed, 17 Apr 2024 00:27:33 -0700 (PDT)", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.4; Wed, 17 Apr 2024 00:27:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend\n Transport; Wed, 17 Apr 2024 00:27:19 -0700", "from BG-LT92004.corp.innovium.com (unknown [10.193.69.67])\n by maili.marvell.com (Postfix) with ESMTP id 79BCF3F70B9;\n Wed, 17 Apr 2024 00:27:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=PRstuv4EVxhyeCwDL3JKaUbzJyl6lJrzq7BGhHnYDVw=; b=kMi\n WDW3Di9Cfdex8vNnyBCep4XjJ404C5fMNsi/ixu1zNp4CH9j2fvlOt8Xp02tbP3u\n Fix3Jl2q5U1/K6Zet5k9GlfOS6NrUL5rZA/PSlmYgWJnnaDTe+NfM1Drrm7Xmd3w\n O0BaBEnsM9qvc31EYt4U9XxqrRY7Hs1CMPqccg2sidt3talUhHnhrL2Zin7dV0rC\n y5XiAm0ow3g1KyQN8y5QTIAUwR8BTNtU84rSzZZG2krFmiIFqiRpfSzJDoK3RS6m\n mO+jM1FIHTu4dkRliwnGK/Na73kxmqtoT8Nw2UkTxXe8wGpGjwcR+yG4nwAnk77C\n 1ha+072abW1LAG0YQiA==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Chengwen Feng <fengchengwen@huawei.com>, Kevin Laatz\n <kevin.laatz@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,\n \"Jerin Jacob\" <jerinj@marvell.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>, \"Vidya Sagar\n Velumuri\" <vvelumuri@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 2/7] dma/odm: add hardware defines", "Date": "Wed, 17 Apr 2024 12:57:03 +0530", "Message-ID": "<20240417072708.322-3-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240417072708.322-1-anoobj@marvell.com>", "References": "<20240415153159.86-1-anoobj@marvell.com>\n <20240417072708.322-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ver0oKTF9RVW5HQigLXkKNpYXAOyEQQQ", "X-Proofpoint-ORIG-GUID": "ver0oKTF9RVW5HQigLXkKNpYXAOyEQQQ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-04-17_06,2024-04-16_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add ODM registers and structures. Add mailbox structs as well.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n drivers/dma/odm/odm.h | 116 +++++++++++++++++++++++++++++++++++++\n drivers/dma/odm/odm_priv.h | 49 ++++++++++++++++\n 2 files changed, 165 insertions(+)\n create mode 100644 drivers/dma/odm/odm_priv.h", "diff": "diff --git a/drivers/dma/odm/odm.h b/drivers/dma/odm/odm.h\nindex aeeb6f9e9a..7564ffbed4 100644\n--- a/drivers/dma/odm/odm.h\n+++ b/drivers/dma/odm/odm.h\n@@ -9,6 +9,47 @@\n \n extern int odm_logtype;\n \n+/* ODM VF register offsets from VF_BAR0 */\n+#define ODM_VDMA_EN(x)\t\t(0x00 | (x << 3))\n+#define ODM_VDMA_REQQ_CTL(x)\t(0x80 | (x << 3))\n+#define ODM_VDMA_DBELL(x)\t(0x100 | (x << 3))\n+#define ODM_VDMA_RING_CFG(x)\t(0x180 | (x << 3))\n+#define ODM_VDMA_IRING_BADDR(x) (0x200 | (x << 3))\n+#define ODM_VDMA_CRING_BADDR(x) (0x280 | (x << 3))\n+#define ODM_VDMA_COUNTS(x)\t(0x300 | (x << 3))\n+#define ODM_VDMA_IRING_NADDR(x) (0x380 | (x << 3))\n+#define ODM_VDMA_CRING_NADDR(x) (0x400 | (x << 3))\n+#define ODM_VDMA_IRING_DBG(x)\t(0x480 | (x << 3))\n+#define ODM_VDMA_CNT(x)\t\t(0x580 | (x << 3))\n+#define ODM_VF_INT\t\t(0x1000)\n+#define ODM_VF_INT_W1S\t\t(0x1008)\n+#define ODM_VF_INT_ENA_W1C\t(0x1010)\n+#define ODM_VF_INT_ENA_W1S\t(0x1018)\n+#define ODM_MBOX_VF_PF_DATA(i)\t(0x2000 | (i << 3))\n+\n+#define ODM_MBOX_RETRY_CNT\t(0xfffffff)\n+#define ODM_MBOX_ERR_CODE_MAX\t(0xf)\n+#define ODM_IRING_IDLE_WAIT_CNT (0xfffffff)\n+\n+/**\n+ * Enumeration odm_hdr_xtype_e\n+ *\n+ * ODM Transfer Type Enumeration\n+ * Enumerates the pointer type in ODM_DMA_INSTR_HDR_S[XTYPE]\n+ */\n+#define ODM_XTYPE_INTERNAL 2\n+#define ODM_XTYPE_FILL0\t 4\n+#define ODM_XTYPE_FILL1\t 5\n+\n+/**\n+ * ODM Header completion type enumeration\n+ * Enumerates the completion type in ODM_DMA_INSTR_HDR_S[CT]\n+ */\n+#define ODM_HDR_CT_CW_CA 0x0\n+#define ODM_HDR_CT_CW_NC 0x1\n+\n+#define ODM_MAX_QUEUES_PER_DEV 16\n+\n #define odm_err(...) \\\n \trte_log(RTE_LOG_ERR, odm_logtype, \\\n \t\tRTE_FMT(\"%s(): %u\" RTE_FMT_HEAD(__VA_ARGS__, ), __func__, __LINE__, \\\n@@ -18,6 +59,81 @@ extern int odm_logtype;\n \t\tRTE_FMT(\"%s(): %u\" RTE_FMT_HEAD(__VA_ARGS__, ), __func__, __LINE__, \\\n \t\t\tRTE_FMT_TAIL(__VA_ARGS__, )))\n \n+/**\n+ * Structure odm_instr_hdr_s for ODM\n+ *\n+ * ODM DMA Instruction Header Format\n+ */\n+union odm_instr_hdr_s {\n+\tuint64_t u;\n+\tstruct odm_instr_hdr {\n+\t\tuint64_t nfst : 3;\n+\t\tuint64_t reserved_3 : 1;\n+\t\tuint64_t nlst : 3;\n+\t\tuint64_t reserved_7_9 : 3;\n+\t\tuint64_t ct : 2;\n+\t\tuint64_t stse : 1;\n+\t\tuint64_t reserved_13_28 : 16;\n+\t\tuint64_t sts : 1;\n+\t\tuint64_t reserved_30_49 : 20;\n+\t\tuint64_t xtype : 3;\n+\t\tuint64_t reserved_53_63 : 11;\n+\t} s;\n+};\n+\n+/**\n+ * ODM Completion Entry Structure\n+ *\n+ */\n+union odm_cmpl_ent_s {\n+\tuint32_t u;\n+\tstruct odm_cmpl_ent {\n+\t\tuint32_t cmp_code : 8;\n+\t\tuint32_t rsvd : 23;\n+\t\tuint32_t valid : 1;\n+\t} s;\n+};\n+\n+/**\n+ * ODM DMA Ring Configuration Register\n+ */\n+union odm_vdma_ring_cfg_s {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t isize : 8;\n+\t\tuint64_t rsvd_8_15 : 8;\n+\t\tuint64_t csize : 8;\n+\t\tuint64_t rsvd_24_63 : 40;\n+\t} s;\n+};\n+\n+/**\n+ * ODM DMA Instruction Ring DBG\n+ */\n+union odm_vdma_iring_dbg_s {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t dbell_cnt : 32;\n+\t\tuint64_t offset : 16;\n+\t\tuint64_t rsvd_48_62 : 15;\n+\t\tuint64_t iwbusy : 1;\n+\t} s;\n+};\n+\n+/**\n+ * ODM DMA Counts\n+ */\n+union odm_vdma_counts_s {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t dbell : 32;\n+\t\tuint64_t buf_used_cnt : 9;\n+\t\tuint64_t rsvd_41_43 : 3;\n+\t\tuint64_t rsvd_buf_used_cnt : 3;\n+\t\tuint64_t rsvd_47_63 : 17;\n+\t} s;\n+};\n+\n struct __rte_cache_aligned odm_dev {\n \tstruct rte_pci_device *pci_dev;\n \tuint8_t *rbase;\ndiff --git a/drivers/dma/odm/odm_priv.h b/drivers/dma/odm/odm_priv.h\nnew file mode 100644\nindex 0000000000..1878f4d9a6\n--- /dev/null\n+++ b/drivers/dma/odm/odm_priv.h\n@@ -0,0 +1,49 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#ifndef _ODM_PRIV_H_\n+#define _ODM_PRIV_H_\n+\n+#define ODM_MAX_VFS 16\n+#define ODM_MAX_QUEUES 32\n+\n+#define ODM_CMD_QUEUE_SIZE 4096\n+\n+#define ODM_DEV_INIT\t0x1\n+#define ODM_DEV_CLOSE\t0x2\n+#define ODM_QUEUE_OPEN\t0x3\n+#define ODM_QUEUE_CLOSE 0x4\n+#define ODM_REG_DUMP\t0x5\n+\n+struct odm_mbox_dev_msg {\n+\t/* Response code */\n+\tuint64_t rsp : 8;\n+\t/* Number of VFs */\n+\tuint64_t nvfs : 2;\n+\t/* Error code */\n+\tuint64_t err : 6;\n+\t/* Reserved */\n+\tuint64_t rsvd_16_63 : 48;\n+};\n+\n+struct odm_mbox_queue_msg {\n+\t/* Command code */\n+\tuint64_t cmd : 8;\n+\t/* VF ID to configure */\n+\tuint64_t vfid : 8;\n+\t/* Queue index in the VF */\n+\tuint64_t qidx : 8;\n+\t/* Reserved */\n+\tuint64_t rsvd_24_63 : 40;\n+};\n+\n+union odm_mbox_msg {\n+\tuint64_t u[2];\n+\tstruct {\n+\t\tstruct odm_mbox_dev_msg d;\n+\t\tstruct odm_mbox_queue_msg q;\n+\t};\n+};\n+\n+#endif /* _ODM_PRIV_H_ */\n", "prefixes": [ "v2", "2/7" ] }