Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/139366/?format=api
{ "id": 139366, "url": "http://patches.dpdk.org/api/patches/139366/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-53-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1713211485-9021-53-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1713211485-9021-53-git-send-email-roretzla@linux.microsoft.com", "date": "2024-04-15T20:04:14", "name": "[v2,52/83] crypto/qat: move alignment attribute on types", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "e482fa90506a53f904302e13671e416ba694e56e", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-53-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31746, "url": "http://patches.dpdk.org/api/series/31746/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31746", "date": "2024-04-15T20:03:22", "name": "move alignment attribute on types", "version": 2, "mbox": "http://patches.dpdk.org/series/31746/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139366/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/139366/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A4BBA43E7E;\n\tMon, 15 Apr 2024 22:13:07 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F2F3342E40;\n\tMon, 15 Apr 2024 22:06:32 +0200 (CEST)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id 7EBF840E36\n for <dev@dpdk.org>; Mon, 15 Apr 2024 22:05:06 +0200 (CEST)", "by linux.microsoft.com (Postfix, from userid 1086)\n id B576820FD937; Mon, 15 Apr 2024 13:04:47 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com B576820FD937", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1713211491;\n bh=3XR0tIXklwL8Wwg/mawV+aIA7/pDQzqhFXkOiHvcMdc=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=hm9DQGR2CsNE/2gsj6ceHTS1YnZvy54zuoy8uExyQpmcLwX84pgwRz+7lD7nG1bq2\n EF0eZcFyyGM6lANOc4L0cQKfmDNiTpHlAlgHx31iflCc1Kc+/jg0XwM9mrtrES2C9i\n o2jsuJNSHjMPkJpDKfvE+6gGMMkwr0ikZerYu+DM=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>,\n \"Min Hu (Connor)\" <humin29@huawei.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Ajit Khaparde <ajit.khaparde@broadcom.com>, Akhil Goyal <gakhil@marvell.com>,\n Alok Prasad <palok@marvell.com>, Amit Bernstein <amitbern@amazon.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Andrew Boyer <andrew.boyer@amd.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Ashwin Sekhar T K <asekhar@marvell.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Byron Marohn <byron.marohn@intel.com>,\n Chaoyong He <chaoyong.he@corigine.com>, Chas Williams <chas3@att.com>,\n Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,\n Conor Walsh <conor.walsh@intel.com>,\n Cristian Dumitrescu <cristian.dumitrescu@intel.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>,\n Devendra Singh Rawat <dsinghrawat@marvell.com>,\n Ed Czeck <ed.czeck@atomicrules.com>, Evgeny Schemeilin <evgenys@amazon.com>,\n Fan Zhang <fanzhang.oss@gmail.com>, Gagandeep Singh <g.singh@nxp.com>,\n Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>,\n Harry van Haaren <harry.van.haaren@intel.com>,\n Hemant Agrawal <hemant.agrawal@nxp.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Hyong Youb Kim <hyonkim@cisco.com>, Jakub Grajciar <jgrajcia@cisco.com>,\n Jerin Jacob <jerinj@marvell.com>, Jian Wang <jianwang@trustnetic.com>,\n Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>,\n Jingjing Wu <jingjing.wu@intel.com>, John Daley <johndale@cisco.com>,\n John Miller <john.miller@atomicrules.com>, Joyce Kong <joyce.kong@arm.com>,\n Kai Ji <kai.ji@intel.com>, Kevin Laatz <kevin.laatz@intel.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Lee Daly <lee.daly@intel.com>, Liang Ma <liangma@liangbit.com>,\n Liron Himi <lironh@marvell.com>, Long Li <longli@microsoft.com>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Matt Peters <matt.peters@windriver.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Michael Shamis <michaelsh@marvell.com>,\n Nagadheeraj Rottela <rnagadheeraj@marvell.com>,\n Nicolas Chautru <nicolas.chautru@intel.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,\n Pablo de Lara <pablo.de.lara.guarch@intel.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>,\n Peter Mccarthy <peter.mccarthy@intel.com>,\n Radu Nicolau <radu.nicolau@intel.com>,\n Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,\n Rakesh Kudurumalla <rkudurumalla@marvell.com>,\n Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>,\n Reshma Pattan <reshma.pattan@intel.com>, Ron Beider <rbeider@amazon.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Sachin Saxena <sachin.saxena@nxp.com>,\n Selwin Sebastian <selwin.sebastian@amd.com>,\n Shai Brandes <shaibran@amazon.com>,\n Shepard Siegel <shepard.siegel@atomicrules.com>,\n Shijith Thotton <sthotton@marvell.com>,\n Sivaprasad Tummala <sivaprasad.tummala@amd.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Srikanth Yalavarthi <syalavarthi@marvell.com>,\n Stephen Hemminger <stephen@networkplumber.org>,\n Steven Webster <steven.webster@windriver.com>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>,\n Sunila Sahu <ssahu@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Vikas Gupta <vikas.gupta@broadcom.com>,\n Volodymyr Fialko <vfialko@marvell.com>, Wajeeh Atrash <atrwajee@amazon.com>,\n Wisam Jaddo <wisamm@nvidia.com>, Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>,\n Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>,\n Zhangfei Gao <zhangfei.gao@linaro.org>, Zhirun Yan <yanzhirun_163@163.com>,\n Ziyang Xuan <xuanziyang2@huawei.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v2 52/83] crypto/qat: move alignment attribute on types", "Date": "Mon, 15 Apr 2024 13:04:14 -0700", "Message-Id": "<1713211485-9021-53-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com>\n <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Move location of __rte_aligned(a) to new conventional location. The new\nplacement between {struct,union} and the tag allows the desired\nalignment to be imparted on the type regardless of the toolchain being\nused for both C and C++. Additionally, it avoids confusion by Doxygen\nwhen generating documentation.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\n---\n drivers/crypto/qat/qat_asym.h | 15 +++++++--------\n drivers/crypto/qat/qat_sym.h | 8 ++++----\n drivers/crypto/qat/qat_sym_session.h | 10 +++++-----\n 3 files changed, 16 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h\nindex 6628656..00275fa 100644\n--- a/drivers/crypto/qat/qat_asym.h\n+++ b/drivers/crypto/qat/qat_asym.h\n@@ -18,7 +18,6 @@\n typedef uint64_t large_int_ptr;\n #define MAX_PKE_PARAMS\t8\n #define QAT_PKE_MAX_LN_SIZE 512\n-#define _PKE_ALIGN_ __rte_aligned(8)\n \n #define QAT_ASYM_MAX_PARAMS\t\t\t8\n #define QAT_ASYM_MODINV_NUM_IN_PARAMS\t\t2\n@@ -57,20 +56,20 @@\n \t\t}\t\t\t\t\t\t\t\\\n \t}\n \n-struct qat_asym_op_cookie {\n+struct __rte_aligned(8) qat_asym_op_cookie {\n \tuint64_t error;\n \tuint32_t alg_bytesize; /*< Bytesize of algorithm */\n \tuint32_t qat_func_alignsize; /*< Aligned bytesize of qat function */\n \trte_iova_t input_addr;\n \trte_iova_t output_addr;\n-\tlarge_int_ptr input_params_ptrs[MAX_PKE_PARAMS] _PKE_ALIGN_;\n-\tlarge_int_ptr output_params_ptrs[MAX_PKE_PARAMS] _PKE_ALIGN_;\n-\tunion {\n+\talignas(8) large_int_ptr input_params_ptrs[MAX_PKE_PARAMS];\n+\talignas(8) large_int_ptr output_params_ptrs[MAX_PKE_PARAMS];\n+\tunion __rte_aligned(8) {\n \t\tuint8_t input_array[MAX_PKE_PARAMS][QAT_PKE_MAX_LN_SIZE];\n \t\tuint8_t input_buffer[MAX_PKE_PARAMS * QAT_PKE_MAX_LN_SIZE];\n-\t} _PKE_ALIGN_;\n-\tuint8_t output_array[MAX_PKE_PARAMS][QAT_PKE_MAX_LN_SIZE] _PKE_ALIGN_;\n-} _PKE_ALIGN_;\n+\t};\n+\talignas(8) uint8_t output_array[MAX_PKE_PARAMS][QAT_PKE_MAX_LN_SIZE];\n+};\n \n struct qat_asym_session {\n \tstruct icp_qat_fw_pke_request req_tmpl;\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex 6616064..eedf5de 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -103,10 +103,10 @@\n \n struct qat_sym_session;\n \n-struct qat_sym_sgl {\n+struct __rte_cache_aligned qat_sym_sgl {\n \tqat_sgl_hdr;\n \tstruct qat_flat_buf buffers[QAT_SYM_SGL_MAX_NUMBER];\n-} __rte_packed __rte_cache_aligned;\n+} __rte_packed;\n \n struct qat_sym_op_cookie {\n \tstruct qat_sym_sgl qat_sgl_src;\n@@ -116,8 +116,8 @@ struct qat_sym_op_cookie {\n \tunion {\n \t\t/* Used for Single-Pass AES-GMAC only */\n \t\tstruct {\n-\t\t\tstruct icp_qat_hw_cipher_algo_blk cd_cipher\n-\t\t\t\t\t__rte_packed __rte_cache_aligned;\n+\t\t\talignas(RTE_CACHE_LINE_SIZE) struct icp_qat_hw_cipher_algo_blk cd_cipher\n+\t\t\t\t\t__rte_packed;\n \t\t\tphys_addr_t cd_phys_addr;\n \t\t} spc_gmac;\n \t} opt;\ndiff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h\nindex c41f8cc..f263477 100644\n--- a/drivers/crypto/qat/qat_sym_session.h\n+++ b/drivers/crypto/qat/qat_sym_session.h\n@@ -92,7 +92,7 @@ typedef int (*qat_sym_build_request_t)(void *in_op, struct qat_sym_session *ctx,\n \t\tuint8_t *out_msg, void *op_cookie);\n \n /* Common content descriptor */\n-struct qat_sym_cd {\n+struct __rte_cache_aligned qat_sym_cd {\n \tstruct icp_qat_hw_cipher_algo_blk cipher;\n \tunion {\n \t\tstruct icp_qat_hw_auth_algo_blk hash;\n@@ -100,7 +100,7 @@ struct qat_sym_cd {\n \t\tstruct icp_qat_hw_gen3_crc_cd crc_gen3;\n \t\tstruct icp_qat_hw_gen4_crc_cd crc_gen4;\n \t};\n-} __rte_packed __rte_cache_aligned;\n+} __rte_packed;\n \n struct qat_sym_session {\n \tenum icp_qat_fw_la_cmd_id qat_cmd;\n@@ -115,7 +115,7 @@ struct qat_sym_session {\n \t\tstruct qat_sym_cd cd;\n \t\tuint8_t key_array[32];\n \t};\n-\tuint8_t prefix_state[QAT_PREFIX_TBL_SIZE] __rte_cache_aligned;\n+\talignas(RTE_CACHE_LINE_SIZE) uint8_t prefix_state[QAT_PREFIX_TBL_SIZE];\n \tuint8_t *cd_cur_ptr;\n \tunion {\n \t\tphys_addr_t cd_paddr;\n@@ -153,8 +153,8 @@ struct qat_sym_session {\n \tqat_sym_build_request_t build_request[2];\n #ifndef RTE_QAT_OPENSSL\n \tIMB_MGR *mb_mgr;\n-\tuint64_t expkey[4*15] __rte_aligned(16);\n-\tuint32_t dust[4*15] __rte_aligned(16);\n+\talignas(16) uint64_t expkey[4 * 15];\n+\talignas(16) uint32_t dust[4 * 15];\n \tuint8_t docsis_key_len;\n #endif\n };\n", "prefixes": [ "v2", "52/83" ] }