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GET /api/patches/139362/?format=api
{ "id": 139362, "url": "http://patches.dpdk.org/api/patches/139362/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-50-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1713211485-9021-50-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1713211485-9021-50-git-send-email-roretzla@linux.microsoft.com", "date": "2024-04-15T20:04:11", "name": "[v2,49/83] dma/idxd: move alignment attribute on types", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "848762d11699bf0235ed813f88ad7e6ac05c7ea5", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-50-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31746, "url": "http://patches.dpdk.org/api/series/31746/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31746", "date": "2024-04-15T20:03:22", "name": "move alignment attribute on types", "version": 2, "mbox": "http://patches.dpdk.org/series/31746/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139362/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139362/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1C95343E7E;\n\tMon, 15 Apr 2024 22:12:46 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9A00F42E0F;\n\tMon, 15 Apr 2024 22:06:27 +0200 (CEST)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id B82A840E03\n for <dev@dpdk.org>; Mon, 15 Apr 2024 22:05:05 +0200 (CEST)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 7CF9E20FD921; Mon, 15 Apr 2024 13:04:47 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 7CF9E20FD921", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1713211491;\n bh=a9jRplBePU7zkBQJohHFDWy0Hw4/hG7qQJ7vhcxRkD8=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=eIUxgFhiqTA0pHQRe7kXUzPyY4QEaEXHdSgVzhCcNjwVzpGh5Vm5H2g51B9dlOv/X\n 9Ix76UFZ3ORcof+mWc6aMnSiJeMW+enioava8vyLOlkuhqzanuxuhpA8kb3IjPEfnr\n qlQyMriiJpAn8jA6uA07/dq3d1mJsF0se8Q49CgI=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>,\n \"Min Hu (Connor)\" <humin29@huawei.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Ajit Khaparde <ajit.khaparde@broadcom.com>, Akhil Goyal <gakhil@marvell.com>,\n Alok Prasad <palok@marvell.com>, Amit Bernstein <amitbern@amazon.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Andrew Boyer <andrew.boyer@amd.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Ashwin Sekhar T K <asekhar@marvell.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Byron Marohn <byron.marohn@intel.com>,\n Chaoyong He <chaoyong.he@corigine.com>, Chas Williams <chas3@att.com>,\n Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,\n Conor Walsh <conor.walsh@intel.com>,\n Cristian Dumitrescu <cristian.dumitrescu@intel.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>,\n Devendra Singh Rawat <dsinghrawat@marvell.com>,\n Ed Czeck <ed.czeck@atomicrules.com>, Evgeny Schemeilin <evgenys@amazon.com>,\n Fan Zhang <fanzhang.oss@gmail.com>, Gagandeep Singh <g.singh@nxp.com>,\n Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>,\n Harry van Haaren <harry.van.haaren@intel.com>,\n Hemant Agrawal <hemant.agrawal@nxp.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Hyong Youb Kim <hyonkim@cisco.com>, Jakub Grajciar <jgrajcia@cisco.com>,\n Jerin Jacob <jerinj@marvell.com>, Jian Wang <jianwang@trustnetic.com>,\n Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>,\n Jingjing Wu <jingjing.wu@intel.com>, John Daley <johndale@cisco.com>,\n John Miller <john.miller@atomicrules.com>, Joyce Kong <joyce.kong@arm.com>,\n Kai Ji <kai.ji@intel.com>, Kevin Laatz <kevin.laatz@intel.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Lee Daly <lee.daly@intel.com>, Liang Ma <liangma@liangbit.com>,\n Liron Himi <lironh@marvell.com>, Long Li <longli@microsoft.com>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Matt Peters <matt.peters@windriver.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Michael Shamis <michaelsh@marvell.com>,\n Nagadheeraj Rottela <rnagadheeraj@marvell.com>,\n Nicolas Chautru <nicolas.chautru@intel.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,\n Pablo de Lara <pablo.de.lara.guarch@intel.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>,\n Peter Mccarthy <peter.mccarthy@intel.com>,\n Radu Nicolau <radu.nicolau@intel.com>,\n Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,\n Rakesh Kudurumalla <rkudurumalla@marvell.com>,\n Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>,\n Reshma Pattan <reshma.pattan@intel.com>, Ron Beider <rbeider@amazon.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Sachin Saxena <sachin.saxena@nxp.com>,\n Selwin Sebastian <selwin.sebastian@amd.com>,\n Shai Brandes <shaibran@amazon.com>,\n Shepard Siegel <shepard.siegel@atomicrules.com>,\n Shijith Thotton <sthotton@marvell.com>,\n Sivaprasad Tummala <sivaprasad.tummala@amd.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Srikanth Yalavarthi <syalavarthi@marvell.com>,\n Stephen Hemminger <stephen@networkplumber.org>,\n Steven Webster <steven.webster@windriver.com>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>,\n Sunila Sahu <ssahu@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Vikas Gupta <vikas.gupta@broadcom.com>,\n Volodymyr Fialko <vfialko@marvell.com>, Wajeeh Atrash <atrwajee@amazon.com>,\n Wisam Jaddo <wisamm@nvidia.com>, Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>,\n Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>,\n Zhangfei Gao <zhangfei.gao@linaro.org>, Zhirun Yan <yanzhirun_163@163.com>,\n Ziyang Xuan <xuanziyang2@huawei.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v2 49/83] dma/idxd: move alignment attribute on types", "Date": "Mon, 15 Apr 2024 13:04:11 -0700", "Message-Id": "<1713211485-9021-50-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com>\n <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Move location of __rte_aligned(a) to new conventional location. The new\nplacement between {struct,union} and the tag allows the desired\nalignment to be imparted on the type regardless of the toolchain being\nused for both C and C++. Additionally, it avoids confusion by Doxygen\nwhen generating documentation.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\n---\n drivers/dma/idxd/idxd_hw_defs.h | 38 +++++++++++++++++++-------------------\n 1 file changed, 19 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/dma/idxd/idxd_hw_defs.h b/drivers/dma/idxd/idxd_hw_defs.h\nindex 7113d22..435c1cd 100644\n--- a/drivers/dma/idxd/idxd_hw_defs.h\n+++ b/drivers/dma/idxd/idxd_hw_defs.h\n@@ -26,7 +26,7 @@ enum rte_idxd_ops {\n * Hardware descriptor used by DSA hardware, for both bursts and\n * for individual operations.\n */\n-struct idxd_hw_desc {\n+struct __rte_aligned(64) idxd_hw_desc {\n \tuint32_t pasid;\n \tuint32_t op_flags;\n \trte_iova_t completion;\n@@ -43,7 +43,7 @@ struct idxd_hw_desc {\n \n \t/* remaining 26 bytes are reserved */\n \tuint16_t reserved[13];\n-} __rte_aligned(64);\n+};\n \n #define IDXD_COMP_STATUS_INCOMPLETE 0\n #define IDXD_COMP_STATUS_SUCCESS 1\n@@ -55,7 +55,7 @@ struct idxd_hw_desc {\n /**\n * Completion record structure written back by DSA\n */\n-struct idxd_completion {\n+struct __rte_aligned(32) idxd_completion {\n \tuint8_t status;\n \tuint8_t result;\n \t/* 16-bits pad here */\n@@ -63,7 +63,7 @@ struct idxd_completion {\n \n \trte_iova_t fault_address;\n \tuint32_t invalid_flags;\n-} __rte_aligned(32);\n+};\n \n /*** Definitions for Intel(R) Data Streaming Accelerator ***/\n \n@@ -83,20 +83,20 @@ enum rte_idxd_cmds {\n \n /* General bar0 registers */\n struct rte_idxd_bar0 {\n-\tuint32_t __rte_cache_aligned version; /* offset 0x00 */\n-\tuint64_t __rte_aligned(0x10) gencap; /* offset 0x10 */\n-\tuint64_t __rte_aligned(0x10) wqcap; /* offset 0x20 */\n-\tuint64_t __rte_aligned(0x10) grpcap; /* offset 0x30 */\n-\tuint64_t __rte_aligned(0x08) engcap; /* offset 0x38 */\n-\tuint64_t __rte_aligned(0x10) opcap; /* offset 0x40 */\n-\tuint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */\n-\tuint32_t __rte_aligned(0x20) gencfg; /* offset 0x80 */\n-\tuint32_t __rte_aligned(0x08) genctrl; /* offset 0x88 */\n-\tuint32_t __rte_aligned(0x10) gensts; /* offset 0x90 */\n-\tuint32_t __rte_aligned(0x08) intcause; /* offset 0x98 */\n-\tuint32_t __rte_aligned(0x10) cmd; /* offset 0xA0 */\n-\tuint32_t __rte_aligned(0x08) cmdstatus; /* offset 0xA8 */\n-\tuint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */\n+\talignas(RTE_CACHE_LINE_SIZE) uint32_t version; /* offset 0x00 */\n+\talignas(0x10) uint64_t gencap; /* offset 0x10 */\n+\talignas(0x10) uint64_t wqcap; /* offset 0x20 */\n+\talignas(0x10) uint64_t grpcap; /* offset 0x30 */\n+\talignas(0x08) uint64_t engcap; /* offset 0x38 */\n+\talignas(0x10) uint64_t opcap; /* offset 0x40 */\n+\talignas(0x20) uint64_t offsets[2]; /* offset 0x60 */\n+\talignas(0x20) uint32_t gencfg; /* offset 0x80 */\n+\talignas(0x08) uint32_t genctrl; /* offset 0x88 */\n+\talignas(0x10) uint32_t gensts; /* offset 0x90 */\n+\talignas(0x08) uint32_t intcause; /* offset 0x98 */\n+\talignas(0x10) uint32_t cmd; /* offset 0xA0 */\n+\talignas(0x08) uint32_t cmdstatus; /* offset 0xA8 */\n+\talignas(0x20) uint64_t swerror[4]; /* offset 0xC0 */\n };\n \n /* workqueue config is provided by array of uint32_t. */\n@@ -118,7 +118,7 @@ enum rte_idxd_wqcfg {\n #define WQ_STATE_MASK 0x3\n \n struct rte_idxd_grpcfg {\n-\tuint64_t grpwqcfg[4] __rte_cache_aligned; /* 64-byte register set */\n+\talignas(RTE_CACHE_LINE_SIZE) uint64_t grpwqcfg[4]; /* 64-byte register set */\n \tuint64_t grpengcfg; /* offset 32 */\n \tuint32_t grpflags; /* offset 40 */\n };\n", "prefixes": [ "v2", "49/83" ] }