Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/139350/?format=api
{ "id": 139350, "url": "http://patches.dpdk.org/api/patches/139350/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-81-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1713211485-9021-81-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1713211485-9021-81-git-send-email-roretzla@linux.microsoft.com", "date": "2024-04-15T20:04:42", "name": "[v2,80/83] app/test-eventdev: move alignment attribute on types", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "62b84178a1095659c01b1409340d64ef1a83b7e6", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-81-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31746, "url": "http://patches.dpdk.org/api/series/31746/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31746", "date": "2024-04-15T20:03:22", "name": "move alignment attribute on types", "version": 2, "mbox": "http://patches.dpdk.org/series/31746/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139350/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139350/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B1D0343E7E;\n\tMon, 15 Apr 2024 22:11:12 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 60CA740DF5;\n\tMon, 15 Apr 2024 22:06:05 +0200 (CEST)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id 9801140C35\n for <dev@dpdk.org>; Mon, 15 Apr 2024 22:05:02 +0200 (CEST)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 8863820FD896; Mon, 15 Apr 2024 13:04:48 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 8863820FD896", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1713211490;\n bh=oeLNh4oPizN4MSMDQMUbKr1A92nden66/3a+d2szccY=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=b7alsULgjYppMToS3OfdMLPACJ/v+13yRMP/kLAnWOF6ZTDtQ3gUr02IiTWpxjDpU\n 5Zhm1oubN71onOFW4R5sOLAYcf+I02eZtBKeH8Vo3sfDIQZeFtJ0xjJ4DpB6e86Byd\n jHuxBL96fUxFJGYqOnqBOrg8IUaKdhz+Ro2dUXjA=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>,\n \"Min Hu (Connor)\" <humin29@huawei.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Ajit Khaparde <ajit.khaparde@broadcom.com>, Akhil Goyal <gakhil@marvell.com>,\n Alok Prasad <palok@marvell.com>, Amit Bernstein <amitbern@amazon.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Andrew Boyer <andrew.boyer@amd.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Ashwin Sekhar T K <asekhar@marvell.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Byron Marohn <byron.marohn@intel.com>,\n Chaoyong He <chaoyong.he@corigine.com>, Chas Williams <chas3@att.com>,\n Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,\n Conor Walsh <conor.walsh@intel.com>,\n Cristian Dumitrescu <cristian.dumitrescu@intel.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>,\n Devendra Singh Rawat <dsinghrawat@marvell.com>,\n Ed Czeck <ed.czeck@atomicrules.com>, Evgeny Schemeilin <evgenys@amazon.com>,\n Fan Zhang <fanzhang.oss@gmail.com>, Gagandeep Singh <g.singh@nxp.com>,\n Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>,\n Harry van Haaren <harry.van.haaren@intel.com>,\n Hemant Agrawal <hemant.agrawal@nxp.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Hyong Youb Kim <hyonkim@cisco.com>, Jakub Grajciar <jgrajcia@cisco.com>,\n Jerin Jacob <jerinj@marvell.com>, Jian Wang <jianwang@trustnetic.com>,\n Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>,\n Jingjing Wu <jingjing.wu@intel.com>, John Daley <johndale@cisco.com>,\n John Miller <john.miller@atomicrules.com>, Joyce Kong <joyce.kong@arm.com>,\n Kai Ji <kai.ji@intel.com>, Kevin Laatz <kevin.laatz@intel.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Lee Daly <lee.daly@intel.com>, Liang Ma <liangma@liangbit.com>,\n Liron Himi <lironh@marvell.com>, Long Li <longli@microsoft.com>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Matt Peters <matt.peters@windriver.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Michael Shamis <michaelsh@marvell.com>,\n Nagadheeraj Rottela <rnagadheeraj@marvell.com>,\n Nicolas Chautru <nicolas.chautru@intel.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,\n Pablo de Lara <pablo.de.lara.guarch@intel.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>,\n Peter Mccarthy <peter.mccarthy@intel.com>,\n Radu Nicolau <radu.nicolau@intel.com>,\n Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,\n Rakesh Kudurumalla <rkudurumalla@marvell.com>,\n Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>,\n Reshma Pattan <reshma.pattan@intel.com>, Ron Beider <rbeider@amazon.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Sachin Saxena <sachin.saxena@nxp.com>,\n Selwin Sebastian <selwin.sebastian@amd.com>,\n Shai Brandes <shaibran@amazon.com>,\n Shepard Siegel <shepard.siegel@atomicrules.com>,\n Shijith Thotton <sthotton@marvell.com>,\n Sivaprasad Tummala <sivaprasad.tummala@amd.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Srikanth Yalavarthi <syalavarthi@marvell.com>,\n Stephen Hemminger <stephen@networkplumber.org>,\n Steven Webster <steven.webster@windriver.com>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>,\n Sunila Sahu <ssahu@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Vikas Gupta <vikas.gupta@broadcom.com>,\n Volodymyr Fialko <vfialko@marvell.com>, Wajeeh Atrash <atrwajee@amazon.com>,\n Wisam Jaddo <wisamm@nvidia.com>, Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>,\n Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>,\n Zhangfei Gao <zhangfei.gao@linaro.org>, Zhirun Yan <yanzhirun_163@163.com>,\n Ziyang Xuan <xuanziyang2@huawei.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v2 80/83] app/test-eventdev: move alignment attribute on types", "Date": "Mon, 15 Apr 2024 13:04:42 -0700", "Message-Id": "<1713211485-9021-81-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com>\n <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Move location of __rte_aligned(a) to new conventional location. The new\nplacement between {struct,union} and the tag allows the desired\nalignment to be imparted on the type regardless of the toolchain being\nused for both C and C++. Additionally, it avoids confusion by Doxygen\nwhen generating documentation.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\n---\n app/test-eventdev/test_order_common.h | 4 ++--\n app/test-eventdev/test_perf_common.h | 24 ++++++++++++------------\n app/test-eventdev/test_pipeline_common.h | 18 +++++++++---------\n 3 files changed, 23 insertions(+), 23 deletions(-)", "diff": "diff --git a/app/test-eventdev/test_order_common.h b/app/test-eventdev/test_order_common.h\nindex 1507265..d4cbc5c 100644\n--- a/app/test-eventdev/test_order_common.h\n+++ b/app/test-eventdev/test_order_common.h\n@@ -39,7 +39,7 @@ struct prod_data {\n \tstruct test_order *t;\n };\n \n-struct test_order {\n+struct __rte_cache_aligned test_order {\n \t/* Don't change the offset of \"err\". Signal handler use this memory\n \t * to terminate all lcores work.\n \t */\n@@ -60,7 +60,7 @@ struct test_order {\n \tuint32_t *producer_flow_seq;\n \tuint32_t *expected_flow_seq;\n \tstruct evt_options *opt;\n-} __rte_cache_aligned;\n+};\n \n static inline void\n order_flow_id_copy_from_mbuf(struct test_order *t, struct rte_event *event)\ndiff --git a/app/test-eventdev/test_perf_common.h b/app/test-eventdev/test_perf_common.h\nindex 2b4f572..bc627de 100644\n--- a/app/test-eventdev/test_perf_common.h\n+++ b/app/test-eventdev/test_perf_common.h\n@@ -31,13 +31,13 @@\n \n struct test_perf;\n \n-struct worker_data {\n+struct __rte_cache_aligned worker_data {\n \tuint64_t processed_pkts;\n \tuint64_t latency;\n \tuint8_t dev_id;\n \tuint8_t port_id;\n \tstruct test_perf *t;\n-} __rte_cache_aligned;\n+};\n \n struct crypto_adptr_data {\n \tuint8_t cdev_id;\n@@ -51,16 +51,16 @@ struct dma_adptr_data {\n \tvoid **dma_op;\n };\n \n-struct prod_data {\n+struct __rte_cache_aligned prod_data {\n \tuint8_t dev_id;\n \tuint8_t port_id;\n \tuint8_t queue_id;\n \tstruct crypto_adptr_data ca;\n \tstruct dma_adptr_data da;\n \tstruct test_perf *t;\n-} __rte_cache_aligned;\n+};\n \n-struct test_perf {\n+struct __rte_cache_aligned test_perf {\n \t/* Don't change the offset of \"done\". Signal handler use this memory\n \t * to terminate all lcores work.\n \t */\n@@ -74,17 +74,17 @@ struct test_perf {\n \tstruct prod_data prod[EVT_MAX_PORTS];\n \tstruct worker_data worker[EVT_MAX_PORTS];\n \tstruct evt_options *opt;\n-\tuint8_t sched_type_list[EVT_MAX_STAGES] __rte_cache_aligned;\n-\tstruct rte_event_timer_adapter *timer_adptr[\n-\t\tRTE_EVENT_TIMER_ADAPTER_NUM_MAX] __rte_cache_aligned;\n+\talignas(RTE_CACHE_LINE_SIZE) uint8_t sched_type_list[EVT_MAX_STAGES];\n+\talignas(RTE_CACHE_LINE_SIZE) struct rte_event_timer_adapter *timer_adptr[\n+\t\tRTE_EVENT_TIMER_ADAPTER_NUM_MAX];\n \tstruct rte_mempool *ca_op_pool;\n \tstruct rte_mempool *ca_sess_pool;\n \tstruct rte_mempool *ca_asym_sess_pool;\n \tstruct rte_mempool *ca_vector_pool;\n \tstruct rte_mempool *da_op_pool;\n-} __rte_cache_aligned;\n+};\n \n-struct perf_elt {\n+struct __rte_cache_aligned perf_elt {\n \tunion {\n \t\tstruct rte_event_timer tim;\n \t\tstruct {\n@@ -92,7 +92,7 @@ struct perf_elt {\n \t\t\tuint64_t timestamp;\n \t\t};\n \t};\n-} __rte_cache_aligned;\n+};\n \n #define BURST_SIZE 16\n #define MAX_PROD_ENQ_BURST_SIZE 128\n@@ -111,7 +111,7 @@ struct perf_elt {\n \tconst uint8_t nb_stages = t->opt->nb_stages;\\\n \tconst uint8_t laststage = nb_stages - 1;\\\n \tuint8_t cnt = 0;\\\n-\tvoid *bufs[16] __rte_cache_aligned;\\\n+\talignas(RTE_CACHE_LINE_SIZE) void *bufs[16];\\\n \tint const sz = RTE_DIM(bufs);\\\n \tuint8_t stage;\\\n \tstruct perf_elt *pe = NULL;\\\ndiff --git a/app/test-eventdev/test_pipeline_common.h b/app/test-eventdev/test_pipeline_common.h\nindex 2b7f3e7..cb6375f 100644\n--- a/app/test-eventdev/test_pipeline_common.h\n+++ b/app/test-eventdev/test_pipeline_common.h\n@@ -31,14 +31,14 @@\n \n struct test_pipeline;\n \n-struct worker_data {\n+struct __rte_cache_aligned worker_data {\n \tuint64_t processed_pkts;\n \tuint8_t dev_id;\n \tuint8_t port_id;\n \tstruct test_pipeline *t;\n-} __rte_cache_aligned;\n+};\n \n-struct test_pipeline {\n+struct __rte_cache_aligned test_pipeline {\n \t/* Don't change the offset of \"done\". Signal handler use this memory\n \t * to terminate all lcores work.\n \t */\n@@ -52,8 +52,8 @@ struct test_pipeline {\n \tstruct rte_mempool *pool[RTE_MAX_ETHPORTS];\n \tstruct worker_data worker[EVT_MAX_PORTS];\n \tstruct evt_options *opt;\n-\tuint8_t sched_type_list[EVT_MAX_STAGES] __rte_cache_aligned;\n-} __rte_cache_aligned;\n+\talignas(RTE_CACHE_LINE_SIZE) uint8_t sched_type_list[EVT_MAX_STAGES];\n+};\n \n #define BURST_SIZE 16\n \n@@ -62,7 +62,7 @@ struct test_pipeline {\n \tstruct test_pipeline *t = w->t; \\\n \tconst uint8_t dev = w->dev_id; \\\n \tconst uint8_t port = w->port_id; \\\n-\tstruct rte_event ev __rte_cache_aligned\n+\talignas(RTE_CACHE_LINE_SIZE) struct rte_event ev\n \n #define PIPELINE_WORKER_SINGLE_STAGE_BURST_INIT \\\n \tint i; \\\n@@ -70,7 +70,7 @@ struct test_pipeline {\n \tstruct test_pipeline *t = w->t; \\\n \tconst uint8_t dev = w->dev_id; \\\n \tconst uint8_t port = w->port_id; \\\n-\tstruct rte_event ev[BURST_SIZE + 1] __rte_cache_aligned\n+\talignas(RTE_CACHE_LINE_SIZE) struct rte_event ev[BURST_SIZE + 1]\n \n #define PIPELINE_WORKER_MULTI_STAGE_INIT \\\n \tstruct worker_data *w = arg; \\\n@@ -81,7 +81,7 @@ struct test_pipeline {\n \tconst uint8_t last_queue = t->opt->nb_stages - 1; \\\n \tuint8_t *const sched_type_list = &t->sched_type_list[0]; \\\n \tconst uint8_t nb_stages = t->opt->nb_stages + 1;\t \\\n-\tstruct rte_event ev __rte_cache_aligned\n+\talignas(RTE_CACHE_LINE_SIZE) struct rte_event ev\n \n #define PIPELINE_WORKER_MULTI_STAGE_BURST_INIT \\\n \tint i; \\\n@@ -93,7 +93,7 @@ struct test_pipeline {\n \tconst uint8_t last_queue = t->opt->nb_stages - 1; \\\n \tuint8_t *const sched_type_list = &t->sched_type_list[0]; \\\n \tconst uint8_t nb_stages = t->opt->nb_stages + 1;\t \\\n-\tstruct rte_event ev[BURST_SIZE + 1] __rte_cache_aligned\n+\talignas(RTE_CACHE_LINE_SIZE) struct rte_event ev[BURST_SIZE + 1]\n \n static __rte_always_inline void\n pipeline_fwd_event(struct rte_event *ev, uint8_t sched)\n", "prefixes": [ "v2", "80/83" ] }