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GET /api/patches/139318/?format=api
{ "id": 139318, "url": "http://patches.dpdk.org/api/patches/139318/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-22-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1713211485-9021-22-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1713211485-9021-22-git-send-email-roretzla@linux.microsoft.com", "date": "2024-04-15T20:03:43", "name": "[v2,21/83] net/mlx5: move alignment attribute on types", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "6e024616e85f6c4768910f3c5776b04ad7343639", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1713211485-9021-22-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31746, "url": "http://patches.dpdk.org/api/series/31746/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31746", "date": "2024-04-15T20:03:22", "name": "move alignment attribute on types", "version": 2, "mbox": "http://patches.dpdk.org/series/31746/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139318/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139318/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 524F243E7E;\n\tMon, 15 Apr 2024 22:07:41 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2F85C410F1;\n\tMon, 15 Apr 2024 22:05:22 +0200 (CEST)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id B54274069F\n for <dev@dpdk.org>; Mon, 15 Apr 2024 22:04:53 +0200 (CEST)", "by linux.microsoft.com (Postfix, from userid 1086)\n id CC27120FD469; Mon, 15 Apr 2024 13:04:46 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com CC27120FD469", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1713211487;\n bh=OjGdrxlVKMXgFq5WIyDbp/5i/ZnwuEm40pZrp/jft7c=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=W9kmeyMn3M1+fWt+UXA9xZu235AHcBKaX2pJgvRhTlUNENfo9BwKn3obY4ry2JEnl\n DY2xc7rJiHH02QfCE6KlxfyrojsD0tmmX5/BevpVw7gTx0lr1cMoeBNncmbTsM/tli\n 0CZIUgIaKPQ9M7Wz3/xlWqOVq2fWTrXXWEmg+ZBY=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>,\n \"Min Hu (Connor)\" <humin29@huawei.com>,\n =?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Ajit Khaparde <ajit.khaparde@broadcom.com>, Akhil Goyal <gakhil@marvell.com>,\n Alok Prasad <palok@marvell.com>, Amit Bernstein <amitbern@amazon.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Andrew Boyer <andrew.boyer@amd.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Ashwin Sekhar T K <asekhar@marvell.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Byron Marohn <byron.marohn@intel.com>,\n Chaoyong He <chaoyong.he@corigine.com>, Chas Williams <chas3@att.com>,\n Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>,\n Conor Walsh <conor.walsh@intel.com>,\n Cristian Dumitrescu <cristian.dumitrescu@intel.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>,\n Devendra Singh Rawat <dsinghrawat@marvell.com>,\n Ed Czeck <ed.czeck@atomicrules.com>, Evgeny Schemeilin <evgenys@amazon.com>,\n Fan Zhang <fanzhang.oss@gmail.com>, Gagandeep Singh <g.singh@nxp.com>,\n Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>,\n Harry van Haaren <harry.van.haaren@intel.com>,\n Hemant Agrawal <hemant.agrawal@nxp.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Hyong Youb Kim <hyonkim@cisco.com>, Jakub Grajciar <jgrajcia@cisco.com>,\n Jerin Jacob <jerinj@marvell.com>, Jian Wang <jianwang@trustnetic.com>,\n Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>,\n Jingjing Wu <jingjing.wu@intel.com>, John Daley <johndale@cisco.com>,\n John Miller <john.miller@atomicrules.com>, Joyce Kong <joyce.kong@arm.com>,\n Kai Ji <kai.ji@intel.com>, Kevin Laatz <kevin.laatz@intel.com>,\n Kiran Kumar K <kirankumark@marvell.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Lee Daly <lee.daly@intel.com>, Liang Ma <liangma@liangbit.com>,\n Liron Himi <lironh@marvell.com>, Long Li <longli@microsoft.com>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Matt Peters <matt.peters@windriver.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Michael Shamis <michaelsh@marvell.com>,\n Nagadheeraj Rottela <rnagadheeraj@marvell.com>,\n Nicolas Chautru <nicolas.chautru@intel.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>,\n Pablo de Lara <pablo.de.lara.guarch@intel.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>,\n Peter Mccarthy <peter.mccarthy@intel.com>,\n Radu Nicolau <radu.nicolau@intel.com>,\n Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,\n Rakesh Kudurumalla <rkudurumalla@marvell.com>,\n Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>,\n Reshma Pattan <reshma.pattan@intel.com>, Ron Beider <rbeider@amazon.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Sachin Saxena <sachin.saxena@nxp.com>,\n Selwin Sebastian <selwin.sebastian@amd.com>,\n Shai Brandes <shaibran@amazon.com>,\n Shepard Siegel <shepard.siegel@atomicrules.com>,\n Shijith Thotton <sthotton@marvell.com>,\n Sivaprasad Tummala <sivaprasad.tummala@amd.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Srikanth Yalavarthi <syalavarthi@marvell.com>,\n Stephen Hemminger <stephen@networkplumber.org>,\n Steven Webster <steven.webster@windriver.com>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>,\n Sunila Sahu <ssahu@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Vikas Gupta <vikas.gupta@broadcom.com>,\n Volodymyr Fialko <vfialko@marvell.com>, Wajeeh Atrash <atrwajee@amazon.com>,\n Wisam Jaddo <wisamm@nvidia.com>, Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>,\n Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>,\n Zhangfei Gao <zhangfei.gao@linaro.org>, Zhirun Yan <yanzhirun_163@163.com>,\n Ziyang Xuan <xuanziyang2@huawei.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v2 21/83] net/mlx5: move alignment attribute on types", "Date": "Mon, 15 Apr 2024 13:03:43 -0700", "Message-Id": "<1713211485-9021-22-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com>\n <1713211485-9021-1-git-send-email-roretzla@linux.microsoft.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Move location of __rte_aligned(a) to new conventional location. The new\nplacement between {struct,union} and the tag allows the desired\nalignment to be imparted on the type regardless of the toolchain being\nused for both C and C++. Additionally, it avoids confusion by Doxygen\nwhen generating documentation.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\nAcked-by: Morten Brørup <mb@smartsharesystems.com>\n---\n drivers/net/mlx5/hws/mlx5dr_send.h | 4 ++--\n drivers/net/mlx5/mlx5.h | 6 +++---\n drivers/net/mlx5/mlx5_flow.h | 4 ++--\n drivers/net/mlx5/mlx5_hws_cnt.h | 14 +++++++-------\n drivers/net/mlx5/mlx5_rx.h | 4 ++--\n drivers/net/mlx5/mlx5_rxtx.c | 6 +++---\n drivers/net/mlx5/mlx5_tx.h | 10 +++++-----\n drivers/net/mlx5/mlx5_utils.h | 2 +-\n 8 files changed, 25 insertions(+), 25 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_send.h b/drivers/net/mlx5/hws/mlx5dr_send.h\nindex c4eaea5..0c67a9e 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.h\n@@ -144,7 +144,7 @@ struct mlx5dr_completed_poll {\n \tuint16_t mask;\n };\n \n-struct mlx5dr_send_engine {\n+struct __rte_cache_aligned mlx5dr_send_engine {\n \tstruct mlx5dr_send_ring send_ring[MLX5DR_NUM_SEND_RINGS]; /* For now 1:1 mapping */\n \tstruct mlx5dv_devx_uar *uar; /* Uar is shared between rings of a queue */\n \tstruct mlx5dr_completed_poll completed;\n@@ -153,7 +153,7 @@ struct mlx5dr_send_engine {\n \tuint16_t rings;\n \tuint16_t num_entries;\n \tbool err;\n-} __rte_cache_aligned;\n+};\n \n struct mlx5dr_send_engine_post_ctrl {\n \tstruct mlx5dr_send_engine *queue;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0091a24..3646d20 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -415,7 +415,7 @@ struct mlx5_hw_q_job {\n };\n \n /* HW steering job descriptor LIFO pool. */\n-struct mlx5_hw_q {\n+struct __rte_cache_aligned mlx5_hw_q {\n \tuint32_t job_idx; /* Free job index. */\n \tuint32_t size; /* Job LIFO queue size. */\n \tuint32_t ongoing_flow_ops; /* Number of ongoing flow operations. */\n@@ -424,7 +424,7 @@ struct mlx5_hw_q {\n \tstruct rte_ring *indir_iq; /* Indirect action SW in progress queue. */\n \tstruct rte_ring *flow_transfer_pending;\n \tstruct rte_ring *flow_transfer_completed;\n-} __rte_cache_aligned;\n+};\n \n \n #define MLX5_COUNTER_POOLS_MAX_NUM (1 << 15)\n@@ -1405,7 +1405,7 @@ struct mlx5_hws_cnt_svc_mng {\n \tuint32_t query_interval;\n \trte_thread_t service_thread;\n \tuint8_t svc_running;\n-\tstruct mlx5_hws_aso_mng aso_mng __rte_cache_aligned;\n+\talignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_aso_mng aso_mng;\n };\n \n #define MLX5_FLOW_HW_TAGS_MAX 12\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 0065727..cc1e8cf 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1654,9 +1654,9 @@ struct mlx5_matcher_info {\n \tRTE_ATOMIC(uint32_t) refcnt;\n };\n \n-struct mlx5_dr_rule_action_container {\n+struct __rte_cache_aligned mlx5_dr_rule_action_container {\n \tstruct mlx5dr_rule_action acts[MLX5_HW_MAX_ACTS];\n-} __rte_cache_aligned;\n+};\n \n struct rte_flow_template_table {\n \tLIST_ENTRY(rte_flow_template_table) next;\ndiff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h\nindex e005960..1cb0564 100644\n--- a/drivers/net/mlx5/mlx5_hws_cnt.h\n+++ b/drivers/net/mlx5/mlx5_hws_cnt.h\n@@ -97,11 +97,11 @@ struct mlx5_hws_cnt_pool_caches {\n \tstruct rte_ring *qcache[];\n };\n \n-struct mlx5_hws_cnt_pool {\n+struct __rte_cache_aligned mlx5_hws_cnt_pool {\n \tLIST_ENTRY(mlx5_hws_cnt_pool) next;\n-\tstruct mlx5_hws_cnt_pool_cfg cfg __rte_cache_aligned;\n-\tstruct mlx5_hws_cnt_dcs_mng dcs_mng __rte_cache_aligned;\n-\tuint32_t query_gen __rte_cache_aligned;\n+\talignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_cnt_pool_cfg cfg;\n+\talignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_cnt_dcs_mng dcs_mng;\n+\talignas(RTE_CACHE_LINE_SIZE) uint32_t query_gen;\n \tstruct mlx5_hws_cnt *pool;\n \tstruct mlx5_hws_cnt_raw_data_mng *raw_mng;\n \tstruct rte_ring *reuse_list;\n@@ -110,7 +110,7 @@ struct mlx5_hws_cnt_pool {\n \tstruct mlx5_hws_cnt_pool_caches *cache;\n \tuint64_t time_of_last_age_check;\n \tstruct mlx5_priv *priv;\n-} __rte_cache_aligned;\n+};\n \n /* HWS AGE status. */\n enum {\n@@ -133,7 +133,7 @@ enum {\n };\n \n /* HWS counter age parameter. */\n-struct mlx5_hws_age_param {\n+struct __rte_cache_aligned mlx5_hws_age_param {\n \tuint32_t timeout; /* Aging timeout in seconds (atomically accessed). */\n \tuint32_t sec_since_last_hit;\n \t/* Time in seconds since last hit (atomically accessed). */\n@@ -149,7 +149,7 @@ struct mlx5_hws_age_param {\n \tcnt_id_t own_cnt_index;\n \t/* Counter action created specifically for this AGE action. */\n \tvoid *context; /* Flow AGE context. */\n-} __rte_packed __rte_cache_aligned;\n+} __rte_packed;\n \n \n /**\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 2fce908..fb4d8e6 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -79,7 +79,7 @@ struct mlx5_eth_rxseg {\n };\n \n /* RX queue descriptor. */\n-struct mlx5_rxq_data {\n+struct __rte_cache_aligned mlx5_rxq_data {\n \tunsigned int csum:1; /* Enable checksum offloading. */\n \tunsigned int hw_timestamp:1; /* Enable HW timestamp. */\n \tunsigned int rt_timestamp:1; /* Realtime timestamp format. */\n@@ -146,7 +146,7 @@ struct mlx5_rxq_data {\n \tuint32_t rxseg_n; /* Number of split segment descriptions. */\n \tstruct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG];\n \t/* Buffer split segment descriptions - sizes, offsets, pools. */\n-} __rte_cache_aligned;\n+};\n \n /* RX queue control descriptor. */\n struct mlx5_rxq_ctrl {\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 54d410b..d3d4470 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -77,12 +77,12 @@\n static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,\n \t\t\"invalid WQE size\");\n \n-uint32_t mlx5_ptype_table[] __rte_cache_aligned = {\n+alignas(RTE_CACHE_LINE_SIZE) uint32_t mlx5_ptype_table[] = {\n \t[0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */\n };\n \n-uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;\n-uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;\n+alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_cksum_table[1 << 10];\n+alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_swp_types_table[1 << 10];\n \n uint64_t rte_net_mlx5_dynf_inline_mask;\n \ndiff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex b1e8ea1..107d7ab 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -83,9 +83,9 @@ enum mlx5_txcmp_code {\n extern uint64_t rte_net_mlx5_dynf_inline_mask;\n #define RTE_MBUF_F_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask\n \n-extern uint32_t mlx5_ptype_table[] __rte_cache_aligned;\n-extern uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;\n-extern uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;\n+extern alignas(RTE_CACHE_LINE_SIZE) uint32_t mlx5_ptype_table[];\n+extern alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_cksum_table[1 << 10];\n+extern alignas(RTE_CACHE_LINE_SIZE) uint8_t mlx5_swp_types_table[1 << 10];\n \n struct mlx5_txq_stats {\n #ifdef MLX5_PMD_SOFT_COUNTERS\n@@ -112,7 +112,7 @@ struct mlx5_txq_local {\n \n /* TX queue descriptor. */\n __extension__\n-struct mlx5_txq_data {\n+struct __rte_cache_aligned mlx5_txq_data {\n \tuint16_t elts_head; /* Current counter in (*elts)[]. */\n \tuint16_t elts_tail; /* Counter of first element awaiting completion. */\n \tuint16_t elts_comp; /* elts index since last completion request. */\n@@ -173,7 +173,7 @@ struct mlx5_txq_data {\n \tstruct mlx5_uar_data uar_data;\n \tstruct rte_mbuf *elts[];\n \t/* Storage for queued packets, must be the last field. */\n-} __rte_cache_aligned;\n+};\n \n /* TX queue control descriptor. */\n __extension__\ndiff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h\nindex f3c0d76..b51d977 100644\n--- a/drivers/net/mlx5/mlx5_utils.h\n+++ b/drivers/net/mlx5/mlx5_utils.h\n@@ -235,7 +235,7 @@ struct mlx5_indexed_trunk {\n \tuint32_t next; /* Next free trunk in free list. */\n \tuint32_t free; /* Free entries available */\n \tstruct rte_bitmap *bmp;\n-\tuint8_t data[] __rte_cache_aligned; /* Entry data start. */\n+\talignas(RTE_CACHE_LINE_SIZE) uint8_t data[]; /* Entry data start. */\n };\n \n struct mlx5_indexed_cache {\n", "prefixes": [ "v2", "21/83" ] }