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GET /api/patches/139245/?format=api
{ "id": 139245, "url": "http://patches.dpdk.org/api/patches/139245/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240412115722.3709194-3-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240412115722.3709194-3-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240412115722.3709194-3-gakhil@marvell.com", "date": "2024-04-12T11:57:21", "name": "[v2,2/3] crypto/cnxk: support queue pair depth API", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "252c83af30e7fd6610dbd7f4eb34bef9836d128c", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240412115722.3709194-3-gakhil@marvell.com/mbox/", "series": [ { "id": 31731, "url": "http://patches.dpdk.org/api/series/31731/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31731", "date": "2024-04-12T11:57:19", "name": "cryptodev: add API to get used queue pair depth", "version": 2, "mbox": "http://patches.dpdk.org/series/31731/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/139245/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/139245/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9C81043E51;\n\tFri, 12 Apr 2024 13:57:53 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 301A140A8A;\n\tFri, 12 Apr 2024 13:57:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 9DA5A40A89\n for <dev@dpdk.org>; Fri, 12 Apr 2024 13:57:50 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 43CBkeTW032123; Fri, 12 Apr 2024 04:57:45 -0700", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3xexsah49n-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Fri, 12 Apr 2024 04:57:44 -0700 (PDT)", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.4; Fri, 12 Apr 2024 04:57:43 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend\n Transport; Fri, 12 Apr 2024 04:57:43 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id A7AD03F7077;\n Fri, 12 Apr 2024 04:57:37 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=v24LFyT2GxbvrqyINn/3Y1odwRHEruGtfX72+uEmG7w=; b=H2J\n gZfYG/GoXXCW5ThF5TmlkfEByiHB8pTM/tVn08e9vvLz3Kwzc5m366zK+WnWdtZQ\n oRQAtUfAXx8Bp58B15A63xJTHcInKjB7+HcpysQG1eU95iyUDmOeLIyr9zgIT1KK\n MxNXDmRvRv9Vm63zgJvrA4nWLjVuLLdibD8OREXEXkxaOkBLiRE55NyNjL5OIjYu\n hzM2gH+kr26onjV8yB58tZm0RXwj3tblKoArM2uWpC5v/WTECWA5r9jCTlWLHu1L\n PxPxuRmfS2mUSsqFf8Ll2UYOBumzuSynrT+AtdF1BXJwi9UYAONHPthty6Io1GG1\n eWINa2G26M57Po43Z3w==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <david.marchand@redhat.com>,\n <hemant.agrawal@nxp.com>, <anoobj@marvell.com>,\n <pablo.de.lara.guarch@intel.com>, <fiona.trahe@intel.com>,\n <declan.doherty@intel.com>, <matan@nvidia.com>, <g.singh@nxp.com>,\n <fanzhang.oss@gmail.com>, <jianjay.zhou@huawei.com>,\n <asomalap@amd.com>, <ruifeng.wang@arm.com>,\n <konstantin.v.ananyev@yandex.ru>, <radu.nicolau@intel.com>,\n <ajit.khaparde@broadcom.com>, <rnagadheeraj@marvell.com>,\n <ciara.power@intel.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH v2 2/3] crypto/cnxk: support queue pair depth API", "Date": "Fri, 12 Apr 2024 17:27:21 +0530", "Message-ID": "<20240412115722.3709194-3-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240412115722.3709194-1-gakhil@marvell.com>", "References": "<20240411082232.3495883-1-gakhil@marvell.com>\n <20240412115722.3709194-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "gRRgyqEi7JlvtRG2NKdoVe_iOlfZWbI1", "X-Proofpoint-ORIG-GUID": "gRRgyqEi7JlvtRG2NKdoVe_iOlfZWbI1", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-04-12_08,2024-04-09_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added support to get the used queue pair depth\nfor a specific queue on cn10k platform.\n\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev.c | 1 +\n drivers/crypto/cnxk/cn9k_cryptodev.c | 2 ++\n drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 16 ++++++++++++++++\n drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 2 ++\n 4 files changed, 21 insertions(+)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev.c b/drivers/crypto/cnxk/cn10k_cryptodev.c\nindex 5ed918e18e..70bef13cda 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev.c\n@@ -99,6 +99,7 @@ cn10k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->driver_id = cn10k_cryptodev_driver_id;\n \tdev->feature_flags = cnxk_cpt_default_ff_get();\n \n+\tdev->qp_depth_used = cnxk_cpt_qp_depth_used;\n \tcn10k_cpt_set_enqdeq_fns(dev, vf);\n \tcn10k_sec_ops_override();\n \ndiff --git a/drivers/crypto/cnxk/cn9k_cryptodev.c b/drivers/crypto/cnxk/cn9k_cryptodev.c\nindex 47b0874185..818458bd6f 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev.c\n@@ -15,6 +15,7 @@\n #include \"cn9k_ipsec.h\"\n #include \"cnxk_cryptodev.h\"\n #include \"cnxk_cryptodev_capabilities.h\"\n+#include \"cnxk_cryptodev_ops.h\"\n #include \"cnxk_cryptodev_sec.h\"\n \n #include \"roc_api.h\"\n@@ -96,6 +97,7 @@ cn9k_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tdev->dev_ops = &cn9k_cpt_ops;\n \tdev->driver_id = cn9k_cryptodev_driver_id;\n \tdev->feature_flags = cnxk_cpt_default_ff_get();\n+\tdev->qp_depth_used = cnxk_cpt_qp_depth_used;\n \n \tcnxk_cpt_caps_populate(vf);\n \ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\nindex 1dd1dbac9a..d7f5780637 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c\n@@ -496,6 +496,22 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \treturn ret;\n }\n \n+uint32_t\n+cnxk_cpt_qp_depth_used(void *qptr)\n+{\n+\tstruct cnxk_cpt_qp *qp = qptr;\n+\tstruct pending_queue *pend_q;\n+\tunion cpt_fc_write_s fc;\n+\n+\tpend_q = &qp->pend_q;\n+\n+\tfc.u64[0] = rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)(qp->lmtline.fc_addr),\n+\t\t\trte_memory_order_relaxed);\n+\n+\treturn RTE_MAX(pending_queue_infl_cnt(pend_q->head, pend_q->tail, pend_q->pq_mask),\n+\t\t fc.s.qsize);\n+}\n+\n unsigned int\n cnxk_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)\n {\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\nindex e7bba25cb8..708fad910d 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n@@ -142,6 +142,8 @@ int cnxk_ae_session_cfg(struct rte_cryptodev *dev,\n void cnxk_cpt_dump_on_err(struct cnxk_cpt_qp *qp);\n int cnxk_cpt_queue_pair_event_error_query(struct rte_cryptodev *dev, uint16_t qp_id);\n \n+uint32_t cnxk_cpt_qp_depth_used(void *qptr);\n+\n static __rte_always_inline void\n pending_queue_advance(uint64_t *index, const uint64_t mask)\n {\n", "prefixes": [ "v2", "2/3" ] }