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GET /api/patches/138929/?format=api
{ "id": 138929, "url": "http://patches.dpdk.org/api/patches/138929/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1711580958-20808-7-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1711580958-20808-7-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1711580958-20808-7-git-send-email-roretzla@linux.microsoft.com", "date": "2024-03-27T23:09:09", "name": "[v2,06/15] common/mlx5: pack structures when building with MSVC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "d58c6e19ea0a35cf60db0800d324677db4344b13", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1711580958-20808-7-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31634, "url": "http://patches.dpdk.org/api/series/31634/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31634", "date": "2024-03-27T23:09:03", "name": "fix packing of structs when building with MSVC", "version": 2, "mbox": "http://patches.dpdk.org/series/31634/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/138929/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/138929/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7FCEE43D5B;\n\tThu, 28 Mar 2024 00:10:09 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2390B42D45;\n\tThu, 28 Mar 2024 00:09:34 +0100 (CET)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id 0E6A7406BC\n for <dev@dpdk.org>; Thu, 28 Mar 2024 00:09:21 +0100 (CET)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 8179C20E6948; Wed, 27 Mar 2024 16:09:19 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 8179C20E6948", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1711580959;\n bh=ooRKZKpQqT6Xz3T4PN3KAauYAiKEPc2MXyayPWFB/FY=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=b/z7B3r0fxdTou4rn89ZNDpXF8imGe/TonCEoRZ7RURxjlAVM2MMEy+mZTtIrK6y4\n h7j5aHnm5YRkMVZNopEfd/T0KVKkU3uLCYFKpm5goEWa70kvC8csFEb6hUc0F2kVhA\n 8SfDv4TtqscPUgDSCn+UK7IMO5iL8LLY0L5h8Wxs=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "Akhil Goyal <gakhil@marvell.com>, Aman Singh <aman.deep.singh@intel.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Byron Marohn <byron.marohn@intel.com>, Conor Walsh <conor.walsh@intel.com>,\n Cristian Dumitrescu <cristian.dumitrescu@intel.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>,\n David Hunt <david.hunt@intel.com>, Jerin Jacob <jerinj@marvell.com>,\n Jingjing Wu <jingjing.wu@intel.com>,\n Kirill Rybalchenko <kirill.rybalchenko@intel.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Matan Azrad <matan@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Radu Nicolau <radu.nicolau@intel.com>, Ruifeng Wang <ruifeng.wang@arm.com>,\n Sameh Gobriel <sameh.gobriel@intel.com>,\n Sivaprasad Tummala <sivaprasad.tummala@amd.com>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Vamsi Attunuru <vattunuru@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Vladimir Medvedkin <vladimir.medvedkin@intel.com>,\n Yipeng Wang <yipeng1.wang@intel.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>,\n Yuying Zhang <yuying.zhang@intel.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v2 06/15] common/mlx5: pack structures when building with MSVC", "Date": "Wed, 27 Mar 2024 16:09:09 -0700", "Message-Id": "<1711580958-20808-7-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1711580958-20808-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1710968771-16435-1-git-send-email-roretzla@linux.microsoft.com>\n <1711580958-20808-1-git-send-email-roretzla@linux.microsoft.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add __rte_msvc_pushpack(1) to all __rte_packed structs to cause packing\nwhen building with MSVC.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\n---\n drivers/common/mlx5/mlx5_common_mr.h | 4 ++++\n drivers/common/mlx5/mlx5_common_utils.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 28 ++++++++++++++++++++++++++++\n 3 files changed, 33 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_common_mr.h b/drivers/common/mlx5/mlx5_common_mr.h\nindex 8789d40..4f4bd73 100644\n--- a/drivers/common/mlx5/mlx5_common_mr.h\n+++ b/drivers/common/mlx5/mlx5_common_mr.h\n@@ -49,6 +49,7 @@ struct mlx5_mr {\n };\n \n /* Cache entry for Memory Region. */\n+__rte_msvc_pack\n struct mr_cache_entry {\n \tuintptr_t start; /* Start address of MR. */\n \tuintptr_t end; /* End address of MR. */\n@@ -56,6 +57,7 @@ struct mr_cache_entry {\n } __rte_packed;\n \n /* MR Cache table for Binary search. */\n+__rte_msvc_pack\n struct mlx5_mr_btree {\n \tuint32_t len; /* Number of entries. */\n \tuint32_t size; /* Total number of entries. */\n@@ -65,6 +67,7 @@ struct mlx5_mr_btree {\n struct mlx5_common_device;\n \n /* Per-queue MR control descriptor. */\n+__rte_msvc_pack\n struct mlx5_mr_ctrl {\n \tuint32_t *dev_gen_ptr; /* Generation number of device to poll. */\n \tuint32_t cur_gen; /* Generation number saved to flush caches. */\n@@ -78,6 +81,7 @@ struct mlx5_mr_ctrl {\n LIST_HEAD(mlx5_mempool_reg_list, mlx5_mempool_reg);\n \n /* Global per-device MR cache. */\n+__rte_msvc_pack\n struct mlx5_mr_share_cache {\n \tuint32_t dev_gen; /* Generation number to flush local caches. */\n \trte_rwlock_t rwlock; /* MR cache Lock. */\ndiff --git a/drivers/common/mlx5/mlx5_common_utils.h b/drivers/common/mlx5/mlx5_common_utils.h\nindex ae15119..a44975c 100644\n--- a/drivers/common/mlx5/mlx5_common_utils.h\n+++ b/drivers/common/mlx5/mlx5_common_utils.h\n@@ -27,6 +27,7 @@\n * Structure of the entry in the mlx5 list, user should define its own struct\n * that contains this in order to store the data.\n */\n+__rte_msvc_pack\n struct mlx5_list_entry {\n \tLIST_ENTRY(mlx5_list_entry) next; /* Entry pointers in the list. */\n \tuint32_t ref_cnt __rte_aligned(8); /* 0 means, entry is invalid. */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex c671c75..bf9ecd1 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -319,6 +319,7 @@ enum mlx5_mpw_mode {\n };\n \n /* WQE Control segment. */\n+__rte_msvc_pack\n struct mlx5_wqe_cseg {\n \tuint32_t opcode;\n \tuint32_t sq_ds;\n@@ -336,10 +337,12 @@ struct mlx5_wqe_cseg {\n #define WQE_CSEG_WQE_INDEX_OFFSET\t 8\n \n /* Header of data segment. Minimal size Data Segment */\n+__rte_msvc_pack\n struct mlx5_wqe_dseg {\n \tuint32_t bcount;\n \tunion {\n \t\tuint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];\n+\t\t__rte_msvc_pack\n \t\tstruct {\n \t\t\tuint32_t lkey;\n \t\t\tuint64_t pbuf;\n@@ -348,8 +351,10 @@ struct mlx5_wqe_dseg {\n } __rte_packed;\n \n /* Subset of struct WQE Ethernet Segment. */\n+__rte_msvc_pack\n struct mlx5_wqe_eseg {\n \tunion {\n+\t\t__rte_msvc_pack\n \t\tstruct {\n \t\t\tuint32_t swp_offs;\n \t\t\tuint8_t\tcs_flags;\n@@ -362,6 +367,7 @@ struct mlx5_wqe_eseg {\n \t\t\t\tuint16_t vlan_tag;\n \t\t\t};\n \t\t} __rte_packed;\n+\t\t__rte_msvc_pack\n \t\tstruct {\n \t\t\tuint32_t offsets;\n \t\t\tuint32_t flags;\n@@ -371,6 +377,7 @@ struct mlx5_wqe_eseg {\n \t};\n } __rte_packed;\n \n+__rte_msvc_pack\n struct mlx5_wqe_qseg {\n \tuint32_t reserved0;\n \tuint32_t reserved1;\n@@ -378,6 +385,7 @@ struct mlx5_wqe_qseg {\n \tuint32_t qpn_cqn;\n } __rte_packed;\n \n+__rte_msvc_pack\n struct mlx5_wqe_wseg {\n \tuint32_t operation;\n \tuint32_t lkey;\n@@ -388,6 +396,7 @@ struct mlx5_wqe_wseg {\n } __rte_packed;\n \n /* The title WQEBB, header of WQE. */\n+__rte_msvc_pack\n struct mlx5_wqe {\n \tunion {\n \t\tstruct mlx5_wqe_cseg cseg;\n@@ -437,6 +446,7 @@ struct mlx5_cqe {\n \tuint8_t lro_num_seg;\n \tunion {\n \t\tuint8_t user_index_bytes[3];\n+\t\t__rte_msvc_pack\n \t\tstruct {\n \t\t\tuint8_t user_index_hi;\n \t\t\tuint16_t user_index_low;\n@@ -460,6 +470,7 @@ struct mlx5_cqe_ts {\n \tuint8_t op_own;\n };\n \n+__rte_msvc_pack\n struct mlx5_wqe_rseg {\n \tuint64_t raddr;\n \tuint32_t rkey;\n@@ -479,6 +490,7 @@ struct mlx5_wqe_rseg {\n #define MLX5_UMR_KLM_NUM_ALIGN \\\n \t(MLX5_UMR_KLM_PTR_ALIGN / sizeof(struct mlx5_klm))\n \n+__rte_msvc_pack\n struct mlx5_wqe_umr_cseg {\n \tuint32_t if_cf_toe_cq_res;\n \tuint32_t ko_to_bs;\n@@ -486,6 +498,7 @@ struct mlx5_wqe_umr_cseg {\n \tuint32_t rsvd1[8];\n } __rte_packed;\n \n+__rte_msvc_pack\n struct mlx5_wqe_mkey_cseg {\n \tuint32_t fr_res_af_sf;\n \tuint32_t qpn_mkey;\n@@ -549,6 +562,7 @@ enum {\n #define MLX5_CRYPTO_MMO_TYPE_OFFSET 24\n #define MLX5_CRYPTO_MMO_OP_OFFSET 20\n \n+__rte_msvc_pack\n struct mlx5_wqe_umr_bsf_seg {\n \t/*\n \t * bs_bpt_eo_es contains:\n@@ -582,6 +596,7 @@ struct mlx5_wqe_umr_bsf_seg {\n #pragma GCC diagnostic ignored \"-Wpedantic\"\n #endif\n \n+__rte_msvc_pack\n struct mlx5_umr_wqe {\n \tstruct mlx5_wqe_cseg ctr;\n \tstruct mlx5_wqe_umr_cseg ucseg;\n@@ -592,18 +607,21 @@ struct mlx5_umr_wqe {\n \t};\n } __rte_packed;\n \n+__rte_msvc_pack\n struct mlx5_rdma_write_wqe {\n \tstruct mlx5_wqe_cseg ctr;\n \tstruct mlx5_wqe_rseg rseg;\n \tstruct mlx5_wqe_dseg dseg[];\n } __rte_packed;\n \n+__rte_msvc_pack\n struct mlx5_wqe_send_en_seg {\n \tuint32_t reserve[2];\n \tuint32_t sqnpc;\n \tuint32_t qpn;\n } __rte_packed;\n \n+__rte_msvc_pack\n struct mlx5_wqe_send_en_wqe {\n \tstruct mlx5_wqe_cseg ctr;\n \tstruct mlx5_wqe_send_en_seg sseg;\n@@ -650,6 +668,7 @@ struct mlx5_wqe_metadata_seg {\n \tuint64_t addr;\n };\n \n+__rte_msvc_pack\n struct mlx5_gga_wqe {\n \tuint32_t opcode;\n \tuint32_t sq_ds;\n@@ -663,16 +682,19 @@ struct mlx5_gga_wqe {\n } __rte_packed;\n \n union mlx5_gga_compress_opaque {\n+\t__rte_msvc_pack\n \tstruct {\n \t\tuint32_t syndrome;\n \t\tuint32_t reserved0;\n \t\tuint32_t scattered_length;\n \t\tunion {\n+\t\t\t__rte_msvc_pack\n \t\t\tstruct {\n \t\t\t\tuint32_t reserved1[5];\n \t\t\t\tuint32_t crc32;\n \t\t\t\tuint32_t adler32;\n \t\t\t} v1 __rte_packed;\n+\t\t\t__rte_msvc_pack\n \t\t\tstruct {\n \t\t\t\tuint32_t crc32;\n \t\t\t\tuint32_t adler32;\n@@ -685,9 +707,11 @@ struct mlx5_gga_wqe {\n };\n \n union mlx5_gga_crypto_opaque {\n+\t__rte_msvc_pack\n \tstruct {\n \t\tuint32_t syndrome;\n \t\tuint32_t reserved0[2];\n+\t\t__rte_msvc_pack\n \t\tstruct {\n \t\t\tuint32_t iv[3];\n \t\t\tuint32_t tag_size;\n@@ -4134,6 +4158,7 @@ enum mlx5_aso_op {\n #define MLX5_ASO_CSEG_READ_ENABLE 1\n \n /* ASO WQE CTRL segment. */\n+__rte_msvc_pack\n struct mlx5_aso_cseg {\n \tuint32_t va_h;\n \tuint32_t va_l_r;\n@@ -4150,6 +4175,7 @@ struct mlx5_aso_cseg {\n #define MLX5_MTR_MAX_TOKEN_VALUE INT32_MAX\n \n /* A meter data segment - 2 per ASO WQE. */\n+__rte_msvc_pack\n struct mlx5_aso_mtr_dseg {\n \tuint32_t v_bo_sc_bbog_mm;\n \t/*\n@@ -4191,6 +4217,7 @@ struct mlx5_aso_mtr_dseg {\n #define MLX5_ASO_MTRS_PER_POOL 128\n \n /* ASO WQE data segment. */\n+__rte_msvc_pack\n struct mlx5_aso_dseg {\n \tunion {\n \t\tuint8_t data[MLX5_ASO_WQE_DSEG_SIZE];\n@@ -4199,6 +4226,7 @@ struct mlx5_aso_dseg {\n } __rte_packed;\n \n /* ASO WQE. */\n+__rte_msvc_pack\n struct mlx5_aso_wqe {\n \tstruct mlx5_wqe_cseg general_cseg;\n \tstruct mlx5_aso_cseg aso_cseg;\n", "prefixes": [ "v2", "06/15" ] }