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GET /api/patches/138910/?format=api
{ "id": 138910, "url": "http://patches.dpdk.org/api/patches/138910/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1711579078-10624-35-git-send-email-roretzla@linux.microsoft.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1711579078-10624-35-git-send-email-roretzla@linux.microsoft.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1711579078-10624-35-git-send-email-roretzla@linux.microsoft.com", "date": "2024-03-27T22:37:47", "name": "[v3,34/45] event/dlb2: use rte stdatomic API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "6d38e422668a5aa9e81664e5626a6b99103b30a7", "submitter": { "id": 2077, "url": "http://patches.dpdk.org/api/people/2077/?format=api", "name": "Tyler Retzlaff", "email": "roretzla@linux.microsoft.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1711579078-10624-35-git-send-email-roretzla@linux.microsoft.com/mbox/", "series": [ { "id": 31633, "url": "http://patches.dpdk.org/api/series/31633/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31633", "date": "2024-03-27T22:37:13", "name": "use stdatomic API", "version": 3, "mbox": "http://patches.dpdk.org/series/31633/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/138910/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/138910/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 78F7143D55;\n\tWed, 27 Mar 2024 23:41:29 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 37FA542E2F;\n\tWed, 27 Mar 2024 23:38:47 +0100 (CET)", "from linux.microsoft.com (linux.microsoft.com [13.77.154.182])\n by mails.dpdk.org (Postfix) with ESMTP id D4A9F4161A\n for <dev@dpdk.org>; Wed, 27 Mar 2024 23:38:08 +0100 (CET)", "by linux.microsoft.com (Postfix, from userid 1086)\n id 417D420E6F20; Wed, 27 Mar 2024 15:38:00 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 417D420E6F20", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1711579082;\n bh=W1m3HXXaHh0A9laGg098WGuAz4FWoW1wcCOh+Adtqfw=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=VTdCLN+azyYmc5ljqMN46/YWGfTIVM57Fz8kf0orFosnrJnBVPCozULXqPtzqcQ6K\n P/hwUI4M+rUpcdCbO4C1XCXwGHNnIXo8chZDnS8qlYCVKsNEd7wYEHvuttdSjRjaRQ\n SSxdGgwx//VrNA04KoN0xBiEOwnDq/jvi/BkncQo=", "From": "Tyler Retzlaff <roretzla@linux.microsoft.com>", "To": "dev@dpdk.org", "Cc": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>,\n\t=?utf-8?q?Morten_Br=C3=B8rup?= <mb@smartsharesystems.com>,\n Abdullah Sevincer <abdullah.sevincer@intel.com>,\n Ajit Khaparde <ajit.khaparde@broadcom.com>, Alok Prasad <palok@marvell.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>,\n Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,\n Anoob Joseph <anoobj@marvell.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Byron Marohn <byron.marohn@intel.com>, Chenbo Xia <chenbox@nvidia.com>,\n Chengwen Feng <fengchengwen@huawei.com>,\n Ciara Loftus <ciara.loftus@intel.com>, Ciara Power <ciara.power@intel.com>,\n Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>,\n Devendra Singh Rawat <dsinghrawat@marvell.com>,\n Erik Gabriel Carrillo <erik.g.carrillo@intel.com>,\n Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>,\n Harry van Haaren <harry.van.haaren@intel.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Jakub Grajciar <jgrajcia@cisco.com>, Jerin Jacob <jerinj@marvell.com>,\n Jeroen de Borst <jeroendb@google.com>, Jian Wang <jianwang@trustnetic.com>,\n Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>,\n Jingjing Wu <jingjing.wu@intel.com>, Joshua Washington <joshwash@google.com>,\n Joyce Kong <joyce.kong@arm.com>, Junfeng Guo <junfeng.guo@intel.com>,\n Kevin Laatz <kevin.laatz@intel.com>,\n Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>,\n Liang Ma <liangma@liangbit.com>, Long Li <longli@microsoft.com>,\n Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Nicolas Chautru <nicolas.chautru@intel.com>, Ori Kam <orika@nvidia.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>,\n Peter Mccarthy <peter.mccarthy@intel.com>,\n Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>,\n Reshma Pattan <reshma.pattan@intel.com>, Rosen Xu <rosen.xu@intel.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Rushil Gupta <rushilg@google.com>,\n Sameh Gobriel <sameh.gobriel@intel.com>,\n Sivaprasad Tummala <sivaprasad.tummala@amd.com>,\n Somnath Kotur <somnath.kotur@broadcom.com>,\n Stephen Hemminger <stephen@networkplumber.org>,\n Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>,\n Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>,\n Tetsuya Mukawa <mtetsuyah@gmail.com>, Vamsi Attunuru <vattunuru@marvell.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Vladimir Medvedkin <vladimir.medvedkin@intel.com>,\n Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>,\n Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>,\n Yuying Zhang <Yuying.Zhang@intel.com>, Yuying Zhang <yuying.zhang@intel.com>,\n Ziyang Xuan <xuanziyang2@huawei.com>,\n Tyler Retzlaff <roretzla@linux.microsoft.com>", "Subject": "[PATCH v3 34/45] event/dlb2: use rte stdatomic API", "Date": "Wed, 27 Mar 2024 15:37:47 -0700", "Message-Id": "<1711579078-10624-35-git-send-email-roretzla@linux.microsoft.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1711579078-10624-1-git-send-email-roretzla@linux.microsoft.com>", "References": "<1710967892-7046-1-git-send-email-roretzla@linux.microsoft.com>\n <1711579078-10624-1-git-send-email-roretzla@linux.microsoft.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Replace the use of gcc builtin __atomic_xxx intrinsics with\ncorresponding rte_atomic_xxx optional rte stdatomic API.\n\nSigned-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>\nAcked-by: Stephen Hemminger <stephen@networkplumber.org>\n---\n drivers/event/dlb2/dlb2.c | 34 +++++++++++++++++-----------------\n drivers/event/dlb2/dlb2_priv.h | 15 +++++++--------\n drivers/event/dlb2/dlb2_xstats.c | 2 +-\n 3 files changed, 25 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 628ddef..0b91f03 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -1005,7 +1005,7 @@ struct process_local_port_data\n \t}\n \n \tdlb2->new_event_limit = config->nb_events_limit;\n-\t__atomic_store_n(&dlb2->inflights, 0, __ATOMIC_SEQ_CST);\n+\trte_atomic_store_explicit(&dlb2->inflights, 0, rte_memory_order_seq_cst);\n \n \t/* Save number of ports/queues for this event dev */\n \tdlb2->num_ports = config->nb_event_ports;\n@@ -2668,10 +2668,10 @@ static int dlb2_num_dir_queues_setup(struct dlb2_eventdev *dlb2)\n \t\tbatch_size = credits;\n \n \tif (likely(credits &&\n-\t\t __atomic_compare_exchange_n(\n+\t\t rte_atomic_compare_exchange_strong_explicit(\n \t\t\tqm_port->credit_pool[type],\n-\t\t\t&credits, credits - batch_size, false,\n-\t\t\t__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST)))\n+\t\t\t&credits, credits - batch_size,\n+\t\t\trte_memory_order_seq_cst, rte_memory_order_seq_cst)))\n \t\treturn batch_size;\n \telse\n \t\treturn 0;\n@@ -2687,7 +2687,7 @@ static int dlb2_num_dir_queues_setup(struct dlb2_eventdev *dlb2)\n \t\t/* Replenish credits, saving one quanta for enqueues */\n \t\tuint16_t val = ev_port->inflight_credits - quanta;\n \n-\t\t__atomic_fetch_sub(&dlb2->inflights, val, __ATOMIC_SEQ_CST);\n+\t\trte_atomic_fetch_sub_explicit(&dlb2->inflights, val, rte_memory_order_seq_cst);\n \t\tev_port->inflight_credits -= val;\n \t}\n }\n@@ -2696,8 +2696,8 @@ static int dlb2_num_dir_queues_setup(struct dlb2_eventdev *dlb2)\n dlb2_check_enqueue_sw_credits(struct dlb2_eventdev *dlb2,\n \t\t\t struct dlb2_eventdev_port *ev_port)\n {\n-\tuint32_t sw_inflights = __atomic_load_n(&dlb2->inflights,\n-\t\t\t\t\t\t__ATOMIC_SEQ_CST);\n+\tuint32_t sw_inflights = rte_atomic_load_explicit(&dlb2->inflights,\n+\t\t\t\t\t\trte_memory_order_seq_cst);\n \tconst int num = 1;\n \n \tif (unlikely(ev_port->inflight_max < sw_inflights)) {\n@@ -2719,8 +2719,8 @@ static int dlb2_num_dir_queues_setup(struct dlb2_eventdev *dlb2)\n \t\t\treturn 1;\n \t\t}\n \n-\t\t__atomic_fetch_add(&dlb2->inflights, credit_update_quanta,\n-\t\t\t\t __ATOMIC_SEQ_CST);\n+\t\trte_atomic_fetch_add_explicit(&dlb2->inflights, credit_update_quanta,\n+\t\t\t\t rte_memory_order_seq_cst);\n \t\tev_port->inflight_credits += (credit_update_quanta);\n \n \t\tif (ev_port->inflight_credits < num) {\n@@ -3234,17 +3234,17 @@ static int dlb2_num_dir_queues_setup(struct dlb2_eventdev *dlb2)\n \t\tif (qm_port->dlb2->version == DLB2_HW_V2) {\n \t\t\tqm_port->cached_ldb_credits += num;\n \t\t\tif (qm_port->cached_ldb_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n+\t\t\t\trte_atomic_fetch_add_explicit(\n \t\t\t\t\tqm_port->credit_pool[DLB2_LDB_QUEUE],\n-\t\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\t\tbatch_size, rte_memory_order_seq_cst);\n \t\t\t\tqm_port->cached_ldb_credits -= batch_size;\n \t\t\t}\n \t\t} else {\n \t\t\tqm_port->cached_credits += num;\n \t\t\tif (qm_port->cached_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n+\t\t\t\trte_atomic_fetch_add_explicit(\n \t\t\t\t qm_port->credit_pool[DLB2_COMBINED_POOL],\n-\t\t\t\t batch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\t batch_size, rte_memory_order_seq_cst);\n \t\t\t\tqm_port->cached_credits -= batch_size;\n \t\t\t}\n \t\t}\n@@ -3252,17 +3252,17 @@ static int dlb2_num_dir_queues_setup(struct dlb2_eventdev *dlb2)\n \t\tif (qm_port->dlb2->version == DLB2_HW_V2) {\n \t\t\tqm_port->cached_dir_credits += num;\n \t\t\tif (qm_port->cached_dir_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n+\t\t\t\trte_atomic_fetch_add_explicit(\n \t\t\t\t\tqm_port->credit_pool[DLB2_DIR_QUEUE],\n-\t\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\t\tbatch_size, rte_memory_order_seq_cst);\n \t\t\t\tqm_port->cached_dir_credits -= batch_size;\n \t\t\t}\n \t\t} else {\n \t\t\tqm_port->cached_credits += num;\n \t\t\tif (qm_port->cached_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n+\t\t\t\trte_atomic_fetch_add_explicit(\n \t\t\t\t qm_port->credit_pool[DLB2_COMBINED_POOL],\n-\t\t\t\t batch_size, __ATOMIC_SEQ_CST);\n+\t\t\t\t batch_size, rte_memory_order_seq_cst);\n \t\t\t\tqm_port->cached_credits -= batch_size;\n \t\t\t}\n \t\t}\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 31a3bee..4ff340d 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -348,7 +348,7 @@ struct dlb2_port {\n \tuint32_t dequeue_depth;\n \tenum dlb2_token_pop_mode token_pop_mode;\n \tunion dlb2_port_config cfg;\n-\tuint32_t *credit_pool[DLB2_NUM_QUEUE_TYPES]; /* use __atomic builtins */\n+\tRTE_ATOMIC(uint32_t) *credit_pool[DLB2_NUM_QUEUE_TYPES];\n \tunion {\n \t\tstruct {\n \t\t\tuint16_t cached_ldb_credits;\n@@ -586,7 +586,7 @@ struct dlb2_eventdev {\n \tuint32_t xstats_count_mode_dev;\n \tuint32_t xstats_count_mode_port;\n \tuint32_t xstats_count;\n-\tuint32_t inflights; /* use __atomic builtins */\n+\tRTE_ATOMIC(uint32_t) inflights;\n \tuint32_t new_event_limit;\n \tint max_num_events_override;\n \tint num_dir_credits_override;\n@@ -623,15 +623,14 @@ struct dlb2_eventdev {\n \t\tstruct {\n \t\t\tuint16_t max_ldb_credits;\n \t\t\tuint16_t max_dir_credits;\n-\t\t\t/* use __atomic builtins */ /* shared hw cred */\n-\t\t\tuint32_t ldb_credit_pool __rte_cache_aligned;\n-\t\t\t/* use __atomic builtins */ /* shared hw cred */\n-\t\t\tuint32_t dir_credit_pool __rte_cache_aligned;\n+\t\t\tRTE_ATOMIC(uint32_t) ldb_credit_pool\n+\t\t\t\t__rte_cache_aligned;\n+\t\t\tRTE_ATOMIC(uint32_t) dir_credit_pool\n+\t\t\t\t__rte_cache_aligned;\n \t\t};\n \t\tstruct {\n \t\t\tuint16_t max_credits;\n-\t\t\t/* use __atomic builtins */ /* shared hw cred */\n-\t\t\tuint32_t credit_pool __rte_cache_aligned;\n+\t\t\tRTE_ATOMIC(uint32_t) credit_pool __rte_cache_aligned;\n \t\t};\n \t};\n \tuint32_t cos_ports[DLB2_COS_NUM_VALS]; /* total ldb ports in each class */\ndiff --git a/drivers/event/dlb2/dlb2_xstats.c b/drivers/event/dlb2/dlb2_xstats.c\nindex ff15271..22094f3 100644\n--- a/drivers/event/dlb2/dlb2_xstats.c\n+++ b/drivers/event/dlb2/dlb2_xstats.c\n@@ -173,7 +173,7 @@ struct dlb2_xstats_entry {\n \tcase nb_events_limit:\n \t\treturn dlb2->new_event_limit;\n \tcase inflight_events:\n-\t\treturn __atomic_load_n(&dlb2->inflights, __ATOMIC_SEQ_CST);\n+\t\treturn rte_atomic_load_explicit(&dlb2->inflights, rte_memory_order_seq_cst);\n \tcase ldb_pool_size:\n \t\treturn dlb2->num_ldb_credits;\n \tcase dir_pool_size:\n", "prefixes": [ "v3", "34/45" ] }