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GET /api/patches/138413/?format=api
{ "id": 138413, "url": "http://patches.dpdk.org/api/patches/138413/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240315054213.540-2-vvelumuri@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240315054213.540-2-vvelumuri@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240315054213.540-2-vvelumuri@marvell.com", "date": "2024-03-15T05:42:06", "name": "[v3,1/8] crypto/cnxk: multi seg support block ciphers in tls", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6b6e294f103b00ce763756d064c9ccfd32ef4254", "submitter": { "id": 2363, "url": "http://patches.dpdk.org/api/people/2363/?format=api", "name": "Vidya Sagar Velumuri", "email": "vvelumuri@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240315054213.540-2-vvelumuri@marvell.com/mbox/", "series": [ { "id": 31530, "url": "http://patches.dpdk.org/api/series/31530/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31530", "date": "2024-03-15T05:42:05", "name": "Fixes and minor improvements for Crypto cnxk", "version": 3, "mbox": "http://patches.dpdk.org/series/31530/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/138413/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/138413/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 61CFB43CA6;\n\tFri, 15 Mar 2024 06:43:09 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B451642EB4;\n\tFri, 15 Mar 2024 06:43:04 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7AC4A410FC\n for <dev@dpdk.org>; Fri, 15 Mar 2024 06:42:21 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 42EMJhqw001277 for <dev@dpdk.org>; Thu, 14 Mar 2024 22:42:20 -0700", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wv9xa12h2-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 14 Mar 2024 22:42:19 -0700 (PDT)", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Thu, 14 Mar\n 2024 22:42:19 -0700", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id\n 15.0.1497.48; Thu, 14 Mar 2024 22:42:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend\n Transport; Thu, 14 Mar 2024 22:42:19 -0700", "from BG-LT92004.corp.innovium.com (unknown [10.193.69.194])\n by maili.marvell.com (Postfix) with ESMTP id 06EB13F703F;\n Thu, 14 Mar 2024 22:42:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=7JSvnPB0H3WkxjmMnSHOy7OOUi9298WXLFwlZLsZojg=; b=j8z\n hMyeD3fFXTI/0obIzR34SMsYa2hM9mucj15EFUchjJqkrTf4ocBOg1E+YDbW1HX4\n 9hwozeYBJJx0SI4O2nE2hez2BdGMTvbVUSSeyOslmR3glN/jVCeS7LgEDV+J6zXz\n RNKHPTMIk2u/l6eRZQ04aNLodPi96f9yadYFi3N2cw6ebbGmq4XaY7Fk43dO9PY4\n 62s684ALfLVp2qL3AplXeS/5BHs/AR8EwG7uV+cCUtyfN31CJ2UJX+B79YVKN9Qt\n nJkHgJ0Tc9M3DtZKJxfbbBmCQlq6L3beJTlHTVboTFYRfwbAWVX4OpvqboZah2MU\n /lz0aT6HCuHjqkR4JYg==", "From": "Vidya Sagar Velumuri <vvelumuri@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Jerin Jacob <jerinj@marvell.com>, <dev@dpdk.org>, Aakash Sasidharan\n <asasidharan@marvell.com>, Anoob Joseph <anoobj@marvell.com>", "Subject": "[PATCH v3 1/8] crypto/cnxk: multi seg support block ciphers in tls", "Date": "Fri, 15 Mar 2024 11:12:06 +0530", "Message-ID": "<20240315054213.540-2-vvelumuri@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240315054213.540-1-vvelumuri@marvell.com>", "References": "<20240314131839.3362494-1-vvelumuri@marvell.com>\n <20240315054213.540-1-vvelumuri@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "5Rg-4KFD-AN3b8LG1P5u7fs9oZfCndeL", "X-Proofpoint-GUID": "5Rg-4KFD-AN3b8LG1P5u7fs9oZfCndeL", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-03-14_13,2024-03-13_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for Scatter-Gather mode for block ciphers in TLS-1.2\n\nSigned-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_sec.h | 3 +-\n drivers/crypto/cnxk/cn10k_tls.c | 5 +++\n drivers/crypto/cnxk/cn10k_tls_ops.h | 48 ++++++++++++++++++-----\n 3 files changed, 45 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h\nindex 1efed3c4cf..881a0276cc 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_sec.h\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_sec.h\n@@ -33,7 +33,8 @@ struct cn10k_sec_session {\n \t\t} ipsec;\n \t\tstruct {\n \t\t\tuint8_t enable_padding : 1;\n-\t\t\tuint8_t rvsd : 7;\n+\t\t\tuint8_t tail_fetch_len : 2;\n+\t\t\tuint8_t rvsd : 5;\n \t\t\tbool is_write;\n \t\t} tls;\n \t};\ndiff --git a/drivers/crypto/cnxk/cn10k_tls.c b/drivers/crypto/cnxk/cn10k_tls.c\nindex 879e0ea978..b46904d3f8 100644\n--- a/drivers/crypto/cnxk/cn10k_tls.c\n+++ b/drivers/crypto/cnxk/cn10k_tls.c\n@@ -639,6 +639,11 @@ cn10k_tls_read_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \tif ((sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_12) ||\n \t (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_DTLS_12)) {\n \t\tinst_w4.s.opcode_major = ROC_IE_OT_TLS_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT;\n+\t\tsec_sess->tls.tail_fetch_len = 0;\n+\t\tif (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_3DES)\n+\t\t\tsec_sess->tls.tail_fetch_len = 1;\n+\t\telse if (sa_dptr->w2.s.cipher_select == ROC_IE_OT_TLS_CIPHER_AES_CBC)\n+\t\t\tsec_sess->tls.tail_fetch_len = 2;\n \t} else if (sa_dptr->w2.s.version_select == ROC_IE_OT_TLS_VERSION_TLS_13) {\n \t\tinst_w4.s.opcode_major =\n \t\t\tROC_IE_OT_TLS13_MAJOR_OP_RECORD_DEC | ROC_IE_OT_INPLACE_BIT;\ndiff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h\nindex 7c8ac14ab2..6fd74927ee 100644\n--- a/drivers/crypto/cnxk/cn10k_tls_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_tls_ops.h\n@@ -234,7 +234,10 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n \t\tinst->w4.u64 = w4.u64;\n \t} else if (is_sg_ver2 == false) {\n \t\tstruct roc_sglist_comp *scatter_comp, *gather_comp;\n+\t\tint tail_len = sess->tls.tail_fetch_len * 16;\n+\t\tint pkt_len = rte_pktmbuf_pkt_len(m_src);\n \t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tuint16_t *sg_hdr;\n \t\tuint32_t dlen;\n \t\tint i;\n \n@@ -244,16 +247,25 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n \t\t\treturn -ENOMEM;\n \t\t}\n \n-\t\tin_buffer = (uint8_t *)m_data;\n-\t\t((uint16_t *)in_buffer)[0] = 0;\n-\t\t((uint16_t *)in_buffer)[1] = 0;\n-\n \t\t/* Input Gather List */\n+\t\tin_buffer = (uint8_t *)m_data;\n+\t\tsg_hdr = (uint16_t *)(in_buffer + 32);\n+\t\tgather_comp = (struct roc_sglist_comp *)((uint8_t *)sg_hdr + 8);\n \t\ti = 0;\n-\t\tgather_comp = (struct roc_sglist_comp *)((uint8_t *)in_buffer + 8);\n+\t\t/* Add the last blocks as first gather component for tail fetch. */\n+\t\tif (tail_len) {\n+\t\t\tconst uint8_t *output;\n+\n+\t\t\toutput = rte_pktmbuf_read(m_src, pkt_len - tail_len, tail_len, in_buffer);\n+\t\t\tif (output != in_buffer)\n+\t\t\t\trte_memcpy(in_buffer, output, tail_len);\n+\t\t\ti = fill_sg_comp(gather_comp, i, (uint64_t)in_buffer, tail_len);\n+\t\t}\n \n+\t\tsg_hdr[0] = 0;\n+\t\tsg_hdr[1] = 0;\n \t\ti = fill_sg_comp_from_pkt(gather_comp, i, m_src);\n-\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tsg_hdr[2] = rte_cpu_to_be_16(i);\n \n \t\tg_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n \n@@ -261,7 +273,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n \t\tscatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);\n \n \t\ti = fill_sg_comp_from_pkt(scatter_comp, i, m_src);\n-\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\tsg_hdr[3] = rte_cpu_to_be_16(i);\n \n \t\ts_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);\n \n@@ -273,10 +285,12 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n \t\tw4.u64 = sess->inst.w4;\n \t\tw4.s.dlen = dlen;\n \t\tw4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;\n-\t\tw4.s.param1 = rte_pktmbuf_pkt_len(m_src);\n+\t\tw4.s.param1 = pkt_len;\n \t\tinst->w4.u64 = w4.u64;\n \t} else {\n \t\tstruct roc_sg2list_comp *scatter_comp, *gather_comp;\n+\t\tint tail_len = sess->tls.tail_fetch_len * 16;\n+\t\tint pkt_len = rte_pktmbuf_pkt_len(m_src);\n \t\tunion cpt_inst_w5 cpt_inst_w5;\n \t\tunion cpt_inst_w6 cpt_inst_w6;\n \t\tuint32_t g_size_bytes;\n@@ -292,7 +306,21 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n \t\t/* Input Gather List */\n \t\ti = 0;\n \n-\t\tgather_comp = (struct roc_sg2list_comp *)((uint8_t *)in_buffer);\n+\t\t/* First 32 bytes in m_data are rsvd for tail fetch.\n+\t\t * SG list start from 32 byte onwards.\n+\t\t */\n+\t\tgather_comp = (struct roc_sg2list_comp *)((uint8_t *)(in_buffer + 32));\n+\n+\t\t/* Add the last blocks as first gather component for tail fetch. */\n+\t\tif (tail_len) {\n+\t\t\tconst uint8_t *output;\n+\n+\t\t\toutput = rte_pktmbuf_read(m_src, pkt_len - tail_len, tail_len, in_buffer);\n+\t\t\tif (output != in_buffer)\n+\t\t\t\trte_memcpy(in_buffer, output, tail_len);\n+\t\t\ti = fill_sg2_comp(gather_comp, i, (uint64_t)in_buffer, tail_len);\n+\t\t}\n+\n \t\ti = fill_sg2_comp_from_pkt(gather_comp, i, m_src);\n \n \t\tcpt_inst_w5.s.gather_sz = ((i + 2) / 3);\n@@ -311,7 +339,7 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,\n \t\tinst->w5.u64 = cpt_inst_w5.u64;\n \t\tinst->w6.u64 = cpt_inst_w6.u64;\n \t\tw4.u64 = sess->inst.w4;\n-\t\tw4.s.dlen = rte_pktmbuf_pkt_len(m_src);\n+\t\tw4.s.dlen = pkt_len + tail_len;\n \t\tw4.s.param1 = w4.s.dlen;\n \t\tw4.s.opcode_major &= (~(ROC_IE_OT_INPLACE_BIT));\n \t\tinst->w4.u64 = w4.u64;\n", "prefixes": [ "v3", "1/8" ] }