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GET /api/patches/138202/?format=api
{ "id": 138202, "url": "http://patches.dpdk.org/api/patches/138202/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240312075238.3319480-2-huangdengdui@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240312075238.3319480-2-huangdengdui@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240312075238.3319480-2-huangdengdui@huawei.com", "date": "2024-03-12T07:52:36", "name": "[1/3] ethdev: support setting lanes", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9f8ce05e27363fd39751479fe58b1a63a7891dc1", "submitter": { "id": 3066, "url": "http://patches.dpdk.org/api/people/3066/?format=api", "name": "huangdengdui", "email": "huangdengdui@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240312075238.3319480-2-huangdengdui@huawei.com/mbox/", "series": [ { "id": 31471, "url": "http://patches.dpdk.org/api/series/31471/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31471", "date": "2024-03-12T07:52:35", "name": "support setting lanes", "version": 1, "mbox": "http://patches.dpdk.org/series/31471/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/138202/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/138202/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 83AE243C8E;\n\tTue, 12 Mar 2024 08:52:47 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B36784114B;\n\tTue, 12 Mar 2024 08:52:44 +0100 (CET)", "from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188])\n by mails.dpdk.org (Postfix) with ESMTP id CAC6B40C35\n for <dev@dpdk.org>; Tue, 12 Mar 2024 08:52:40 +0100 (CET)", "from mail.maildlp.com (unknown [172.19.88.194])\n by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Tv5Sp18BTzbclq;\n Tue, 12 Mar 2024 15:51:54 +0800 (CST)", "from dggpeml500011.china.huawei.com (unknown [7.185.36.84])\n by mail.maildlp.com (Postfix) with ESMTPS id 2F12C14040D;\n Tue, 12 Mar 2024 15:52:39 +0800 (CST)", "from localhost.huawei.com (10.50.165.33) by\n dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.1.2507.35; Tue, 12 Mar 2024 15:52:38 +0800" ], "From": "Dengdui Huang <huangdengdui@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@amd.com>, <aman.deep.singh@intel.com>,\n <yuying.zhang@intel.com>, <thomas@monjalon.net>,\n <andrew.rybchenko@oktetlabs.ru>, <liuyonglong@huawei.com>,\n <fengchengwen@huawei.com>, <haijie1@huawei.com>, <lihuisong@huawei.com>", "Subject": "[PATCH 1/3] ethdev: support setting lanes", "Date": "Tue, 12 Mar 2024 15:52:36 +0800", "Message-ID": "<20240312075238.3319480-2-huangdengdui@huawei.com>", "X-Mailer": "git-send-email 2.33.0", "In-Reply-To": "<20240312075238.3319480-1-huangdengdui@huawei.com>", "References": "<20240312075238.3319480-1-huangdengdui@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.50.165.33]", "X-ClientProxiedBy": "dggems706-chm.china.huawei.com (10.3.19.183) To\n dggpeml500011.china.huawei.com (7.185.36.84)", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Some speeds can be achieved with different number of lanes. For example,\n100Gbps can be achieved using two lanes of 50Gbps or four lanes of 25Gbps.\nWhen use different lanes, the port cannot be up. This patch add support\nfor setting lanes and report lanes.\n\nSigned-off-by: Dengdui Huang <huangdengdui@huawei.com>\n---\n doc/guides/rel_notes/release_24_03.rst | 8 +-\n drivers/net/bnxt/bnxt_ethdev.c | 3 +-\n drivers/net/hns3/hns3_ethdev.c | 1 +\n lib/ethdev/ethdev_driver.h | 1 -\n lib/ethdev/ethdev_linux_ethtool.c | 101 ++++++++-\n lib/ethdev/ethdev_private.h | 4 +\n lib/ethdev/ethdev_trace.h | 4 +-\n lib/ethdev/meson.build | 2 +\n lib/ethdev/rte_ethdev.c | 272 +++++++++++++++++++++++--\n lib/ethdev/rte_ethdev.h | 99 +++++++--\n lib/ethdev/version.map | 7 +\n 11 files changed, 466 insertions(+), 36 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 932688ca4d..75d93ee965 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -76,6 +76,10 @@ New Features\n * Added a fath path function ``rte_eth_tx_queue_count``\n to get the number of used descriptors of a Tx queue.\n \n+* **Support setting lanes for ethdev.**\n+ * Support setting lanes by extended ``RTE_ETH_LINK_SPEED_*``.\n+ * Added function to convert bitmap flag to the struct of link speed info.\n+\n * **Added hash calculation of an encapsulated packet as done by the HW.**\n \n Added function to calculate hash when doing tunnel encapsulation:\n@@ -240,9 +244,11 @@ ABI Changes\n This section is a comment. Do not overwrite or remove it.\n Also, make sure to start the actual text at the margin.\n =======================================================\n-\n * No ABI change that would break compatibility with 23.11.\n \n+* ethdev: Convert a numerical speed to a bitmap flag with lanes:\n+ The function ``rte_eth_speed_bitflag`` add lanes parameters.\n+\n \n Known Issues\n ------------\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex ba31ae9286..e881a7f3cc 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -711,7 +711,8 @@ static int bnxt_update_phy_setting(struct bnxt *bp)\n \t}\n \n \t/* convert to speedbit flag */\n-\tcurr_speed_bit = rte_eth_speed_bitflag((uint32_t)link->link_speed, 1);\n+\tcurr_speed_bit = rte_eth_speed_bitflag((uint32_t)link->link_speed,\n+\t\t\t\t\t RTE_ETH_LANES_UNKNOWN, 1);\n \n \t/*\n \t * Device is not obliged link down in certain scenarios, even\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex b10d1216d2..ecd3b2ef64 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -5969,6 +5969,7 @@ hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,\n \tfor (i = 0; i < RTE_DIM(speed_fec_capa_tbl); i++) {\n \t\tspeed_bit =\n \t\t\trte_eth_speed_bitflag(speed_fec_capa_tbl[i].speed,\n+\t\t\t\t\t RTE_ETH_LANES_UNKNOWN,\n \t\t\t\t\t RTE_ETH_LINK_FULL_DUPLEX);\n \t\tif ((speed_capa & speed_bit) == 0)\n \t\t\tcontinue;\ndiff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h\nindex 0dbf2dd6a2..bb7dc7acb7 100644\n--- a/lib/ethdev/ethdev_driver.h\n+++ b/lib/ethdev/ethdev_driver.h\n@@ -2003,7 +2003,6 @@ __rte_internal\n int\n rte_eth_ip_reassembly_dynfield_register(int *field_offset, int *flag);\n \n-\n /*\n * Legacy ethdev API used internally by drivers.\n */\ndiff --git a/lib/ethdev/ethdev_linux_ethtool.c b/lib/ethdev/ethdev_linux_ethtool.c\nindex e792204b01..b776ec6173 100644\n--- a/lib/ethdev/ethdev_linux_ethtool.c\n+++ b/lib/ethdev/ethdev_linux_ethtool.c\n@@ -111,10 +111,107 @@ static const uint32_t link_modes[] = {\n \t[101] = 11, /* ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT */\n };\n \n+/*\n+ * Link modes sorted with index as defined in ethtool.\n+ * Values are lanes.\n+ */\n+static const uint32_t link_modes_lanes[] = {\n+\t [0] = 1, /* ETHTOOL_LINK_MODE_10baseT_Half_BIT */\n+\t [1] = 1, /* ETHTOOL_LINK_MODE_10baseT_Full_BIT */\n+\t [2] = 1, /* ETHTOOL_LINK_MODE_100baseT_Half_BIT */\n+\t [3] = 1, /* ETHTOOL_LINK_MODE_100baseT_Full_BIT */\n+\t [4] = 1, /* ETHTOOL_LINK_MODE_1000baseT_Half_BIT */\n+\t [5] = 1, /* ETHTOOL_LINK_MODE_1000baseT_Full_BIT */\n+\t [12] = 1, /* ETHTOOL_LINK_MODE_10000baseT_Full_BIT */\n+\t [15] = 1, /* ETHTOOL_LINK_MODE_2500baseX_Full_BIT */\n+\t [17] = 1, /* ETHTOOL_LINK_MODE_1000baseKX_Full_BIT */\n+\t [18] = 4, /* ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT */\n+\t [19] = 1, /* ETHTOOL_LINK_MODE_10000baseKR_Full_BIT */\n+\t [20] = 1, /* ETHTOOL_LINK_MODE_10000baseR_FEC_BIT */\n+\t [21] = 2, /* ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT */\n+\t [22] = 2, /* ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT */\n+\t [23] = 4, /* ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT */\n+\t [24] = 4, /* ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT */\n+\t [25] = 4, /* ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT */\n+\t [26] = 4, /* ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT */\n+\t [27] = 4, /* ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT */\n+\t [28] = 4, /* ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT */\n+\t [29] = 4, /* ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT */\n+\t [30] = 4, /* ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT */\n+\t [31] = 1, /* ETHTOOL_LINK_MODE_25000baseCR_Full_BIT */\n+\t [32] = 1, /* ETHTOOL_LINK_MODE_25000baseKR_Full_BIT */\n+\t [33] = 1, /* ETHTOOL_LINK_MODE_25000baseSR_Full_BIT */\n+\t [34] = 2, /* ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT */\n+\t [35] = 2, /* ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT */\n+\t [36] = 4, /* ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT */\n+\t [37] = 4, /* ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT */\n+\t [38] = 4, /* ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT */\n+\t [39] = 4, /* ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT */\n+\t [40] = 2, /* ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT */\n+\t [41] = 1, /* ETHTOOL_LINK_MODE_1000baseX_Full_BIT */\n+\t [42] = 1, /* ETHTOOL_LINK_MODE_10000baseCR_Full_BIT */\n+\t [43] = 1, /* ETHTOOL_LINK_MODE_10000baseSR_Full_BIT */\n+\t [44] = 1, /* ETHTOOL_LINK_MODE_10000baseLR_Full_BIT */\n+\t [45] = 1, /* ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT */\n+\t [46] = 1, /* ETHTOOL_LINK_MODE_10000baseER_Full_BIT */\n+\t [47] = 1, /* ETHTOOL_LINK_MODE_2500baseT_Full_BIT */\n+\t [48] = 1, /* ETHTOOL_LINK_MODE_5000baseT_Full_BIT */\n+\t [52] = 1, /* ETHTOOL_LINK_MODE_50000baseKR_Full_BIT */\n+\t [53] = 1, /* ETHTOOL_LINK_MODE_50000baseSR_Full_BIT */\n+\t [54] = 1, /* ETHTOOL_LINK_MODE_50000baseCR_Full_BIT */\n+\t [55] = 1, /* ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT */\n+\t [56] = 1, /* ETHTOOL_LINK_MODE_50000baseDR_Full_BIT */\n+\t [57] = 2, /* ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT */\n+\t [58] = 2, /* ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT */\n+\t [59] = 2, /* ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT */\n+\t [60] = 2, /* ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT */\n+\t [61] = 2, /* ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT */\n+\t [62] = 4, /* ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT */\n+\t [63] = 4, /* ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT */\n+\t [64] = 4, /* ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT */\n+\t [65] = 4, /* ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT */\n+\t [66] = 4, /* ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT */\n+\t [67] = 1, /* ETHTOOL_LINK_MODE_100baseT1_Full_BIT */\n+\t [68] = 1, /* ETHTOOL_LINK_MODE_1000baseT1_Full_BIT */\n+\t [69] = 8, /* ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT */\n+\t [70] = 8, /* ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT */\n+\t [71] = 8, /* ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT */\n+\t [72] = 8, /* ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT */\n+\t [73] = 8, /* ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT */\n+\t [75] = 1, /* ETHTOOL_LINK_MODE_100000baseKR_Full_BIT */\n+\t [76] = 1, /* ETHTOOL_LINK_MODE_100000baseSR_Full_BIT */\n+\t [77] = 1, /* ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT */\n+\t [78] = 1, /* ETHTOOL_LINK_MODE_100000baseCR_Full_BIT */\n+\t [79] = 1, /* ETHTOOL_LINK_MODE_100000baseDR_Full_BIT */\n+\t [80] = 2, /* ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT */\n+\t [81] = 2, /* ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT */\n+\t [82] = 2, /* ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT */\n+\t [83] = 2, /* ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT */\n+\t [84] = 2, /* ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT */\n+\t [85] = 4, /* ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT */\n+\t [86] = 4, /* ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT */\n+\t [87] = 4, /* ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT */\n+\t [88] = 4, /* ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT */\n+\t [89] = 4, /* ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT */\n+\t [90] = 1, /* ETHTOOL_LINK_MODE_100baseFX_Half_BIT */\n+\t [91] = 1, /* ETHTOOL_LINK_MODE_100baseFX_Full_BIT */\n+\t [92] = 1, /* ETHTOOL_LINK_MODE_10baseT1L_Full_BIT */\n+\t [93] = 8, /* ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT */\n+\t [94] = 8, /* ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT */\n+\t [95] = 8, /* ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT */\n+\t [96] = 8, /* ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT */\n+\t [97] = 8, /* ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT */\n+\t [98] = 8, /* ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT */\n+\t [99] = 1, /* ETHTOOL_LINK_MODE_10baseT1S_Full_BIT */\n+\t[100] = 1, /* ETHTOOL_LINK_MODE_10baseT1S_Half_BIT */\n+\t[101] = 1, /* ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT */\n+};\n+\n uint32_t\n rte_eth_link_speed_ethtool(enum ethtool_link_mode_bit_indices bit)\n {\n \tuint32_t speed;\n+\tuint8_t lanes;\n \tint duplex;\n \n \t/* get mode from array */\n@@ -131,7 +228,9 @@ rte_eth_link_speed_ethtool(enum ethtool_link_mode_bit_indices bit)\n \t\t\tRTE_ETH_LINK_FULL_DUPLEX;\n \tspeed &= RTE_GENMASK32(31, 1);\n \n-\treturn rte_eth_speed_bitflag(speed, duplex);\n+\tlanes = link_modes_lanes[bit];\n+\n+\treturn rte_eth_speed_bitflag(speed, lanes, duplex);\n }\n \n uint32_t\ndiff --git a/lib/ethdev/ethdev_private.h b/lib/ethdev/ethdev_private.h\nindex 0d36b9c30f..9092ab3a9e 100644\n--- a/lib/ethdev/ethdev_private.h\n+++ b/lib/ethdev/ethdev_private.h\n@@ -79,4 +79,8 @@ void eth_dev_txq_release(struct rte_eth_dev *dev, uint16_t qid);\n int eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues);\n int eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues);\n \n+/* versioned functions */\n+uint32_t rte_eth_speed_bitflag_v24(uint32_t speed, int duplex);\n+uint32_t rte_eth_speed_bitflag_v25(uint32_t speed, uint8_t lanes, int duplex);\n+\n #endif /* _ETH_PRIVATE_H_ */\ndiff --git a/lib/ethdev/ethdev_trace.h b/lib/ethdev/ethdev_trace.h\nindex 3bec87bfdb..5547b49cab 100644\n--- a/lib/ethdev/ethdev_trace.h\n+++ b/lib/ethdev/ethdev_trace.h\n@@ -183,8 +183,10 @@ RTE_TRACE_POINT(\n \n RTE_TRACE_POINT(\n \trte_eth_trace_speed_bitflag,\n-\tRTE_TRACE_POINT_ARGS(uint32_t speed, int duplex, uint32_t ret),\n+\tRTE_TRACE_POINT_ARGS(uint32_t speed, uint8_t lanes, int duplex,\n+\t\t\t uint32_t ret),\n \trte_trace_point_emit_u32(speed);\n+\trte_trace_point_emit_u8(lanes);\n \trte_trace_point_emit_int(duplex);\n \trte_trace_point_emit_u32(ret);\n )\ndiff --git a/lib/ethdev/meson.build b/lib/ethdev/meson.build\nindex f1d2586591..2c9588d0b3 100644\n--- a/lib/ethdev/meson.build\n+++ b/lib/ethdev/meson.build\n@@ -62,3 +62,5 @@ endif\n if get_option('buildtype').contains('debug')\n cflags += ['-DRTE_FLOW_DEBUG']\n endif\n+\n+use_function_versioning = true\ndiff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c\nindex f1c658f49e..522f8796b1 100644\n--- a/lib/ethdev/rte_ethdev.c\n+++ b/lib/ethdev/rte_ethdev.c\n@@ -26,6 +26,7 @@\n #include <rte_class.h>\n #include <rte_ether.h>\n #include <rte_telemetry.h>\n+#include <rte_function_versioning.h>\n \n #include \"rte_ethdev.h\"\n #include \"rte_ethdev_trace_fp.h\"\n@@ -991,63 +992,111 @@ rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id)\n \treturn ret;\n }\n \n-uint32_t\n-rte_eth_speed_bitflag(uint32_t speed, int duplex)\n+uint32_t __vsym\n+rte_eth_speed_bitflag_v25(uint32_t speed, uint8_t lanes, int duplex)\n {\n-\tuint32_t ret;\n+\tuint32_t ret = 0;\n \n \tswitch (speed) {\n \tcase RTE_ETH_SPEED_NUM_10M:\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1)\n+\t\t\tbreak;\n \t\tret = duplex ? RTE_ETH_LINK_SPEED_10M : RTE_ETH_LINK_SPEED_10M_HD;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_100M:\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1)\n+\t\t\tbreak;\n \t\tret = duplex ? RTE_ETH_LINK_SPEED_100M : RTE_ETH_LINK_SPEED_100M_HD;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_1G:\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1)\n+\t\t\tbreak;\n \t\tret = RTE_ETH_LINK_SPEED_1G;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_2_5G:\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1)\n+\t\t\tbreak;\n \t\tret = RTE_ETH_LINK_SPEED_2_5G;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_5G:\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1)\n+\t\t\tbreak;\n \t\tret = RTE_ETH_LINK_SPEED_5G;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_10G:\n-\t\tret = RTE_ETH_LINK_SPEED_10G;\n+\t\tif (lanes == RTE_ETH_LANES_1)\n+\t\t\tret = RTE_ETH_LINK_SPEED_10G;\n+\t\tif (lanes == RTE_ETH_LANES_4)\n+\t\t\tret = RTE_ETH_LINK_SPEED_10G_4LANES;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_20G:\n-\t\tret = RTE_ETH_LINK_SPEED_20G;\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_2)\n+\t\t\tbreak;\n+\t\tret = RTE_ETH_LINK_SPEED_20G_2LANES;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_25G:\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_1)\n+\t\t\tbreak;\n \t\tret = RTE_ETH_LINK_SPEED_25G;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_40G:\n-\t\tret = RTE_ETH_LINK_SPEED_40G;\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_4)\n+\t\t\tbreak;\n+\t\tret = RTE_ETH_LINK_SPEED_40G_4LANES;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_50G:\n-\t\tret = RTE_ETH_LINK_SPEED_50G;\n+\t\tif (lanes == RTE_ETH_LANES_1)\n+\t\t\tret = RTE_ETH_LINK_SPEED_50G;\n+\t\tif (lanes == RTE_ETH_LANES_2)\n+\t\t\tret = RTE_ETH_LINK_SPEED_50G_2LANES;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_56G:\n-\t\tret = RTE_ETH_LINK_SPEED_56G;\n+\t\tif (lanes != RTE_ETH_LANES_UNKNOWN && lanes != RTE_ETH_LANES_4)\n+\t\t\tbreak;\n+\t\tret = RTE_ETH_LINK_SPEED_56G_4LANES;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_100G:\n-\t\tret = RTE_ETH_LINK_SPEED_100G;\n+\t\tif (lanes == RTE_ETH_LANES_1)\n+\t\t\tret = RTE_ETH_LINK_SPEED_100G;\n+\t\tif (lanes == RTE_ETH_LANES_2)\n+\t\t\tret = RTE_ETH_LINK_SPEED_100G_2LANES;\n+\t\tif (lanes == RTE_ETH_LANES_4)\n+\t\t\tret = RTE_ETH_LINK_SPEED_100G_4LANES;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_200G:\n-\t\tret = RTE_ETH_LINK_SPEED_200G;\n+\t\tif (lanes == RTE_ETH_LANES_2)\n+\t\t\tret = RTE_ETH_LINK_SPEED_200G_2LANES;\n+\t\tif (lanes == RTE_ETH_LANES_4)\n+\t\t\tret = RTE_ETH_LINK_SPEED_200G_4LANES;\n \t\tbreak;\n \tcase RTE_ETH_SPEED_NUM_400G:\n+\t\tif (lanes == RTE_ETH_LANES_4)\n+\t\t\tret = RTE_ETH_LINK_SPEED_400G_4LANES;\n+\t\tif (lanes == RTE_ETH_LANES_8)\n+\t\t\tret = RTE_ETH_LINK_SPEED_400G_8LANES;\n \t\tret = RTE_ETH_LINK_SPEED_400G;\n \t\tbreak;\n \tdefault:\n \t\tret = 0;\n \t}\n \n-\trte_eth_trace_speed_bitflag(speed, duplex, ret);\n+\trte_eth_trace_speed_bitflag(speed, lanes, duplex, ret);\n \n \treturn ret;\n }\n \n+uint32_t __vsym\n+rte_eth_speed_bitflag_v24(uint32_t speed, int duplex)\n+{\n+\treturn rte_eth_speed_bitflag_v25(speed, RTE_ETH_LANES_UNKNOWN, duplex);\n+}\n+\n+/* mark the v24 function as the older version, and v25 as the default version */\n+VERSION_SYMBOL(rte_eth_speed_bitflag, _v24, 24);\n+BIND_DEFAULT_SYMBOL(rte_eth_speed_bitflag, _v25, 25);\n+MAP_STATIC_SYMBOL(uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex),\n+\t\t rte_eth_speed_bitflag_v25);\n+\n const char *\n rte_eth_dev_rx_offload_name(uint64_t offload)\n {\n@@ -1066,6 +1115,204 @@ rte_eth_dev_rx_offload_name(uint64_t offload)\n \treturn name;\n }\n \n+int\n+rte_eth_speed_capa_to_info(uint32_t link_speed,\n+\t\t\t struct rte_eth_speed_capa_info *capa_info)\n+{\n+\tconst struct {\n+\t\tuint32_t speed_capa;\n+\t\tstruct rte_eth_speed_capa_info capa_info;\n+\t} speed_capa_info_map[] = {\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_10M_HD,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_10M,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_HALF_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_10M,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_10M,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_100M_HD,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_100M,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_HALF_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_100M,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_100M,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_1G,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_1G,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_2_5G,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_2_5G,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_5G,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_5G,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_10G,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_10G,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_20G_2LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_20G,\n+\t\t\t\t\tRTE_ETH_LANES_2,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_25G,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_25G,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_40G_4LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_40G,\n+\t\t\t\t\tRTE_ETH_LANES_4,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_50G,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_50G,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_56G_4LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_56G,\n+\t\t\t\t\tRTE_ETH_LANES_4,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_100G,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_100G,\n+\t\t\t\t\tRTE_ETH_LANES_1,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_200G_4LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_200G,\n+\t\t\t\t\tRTE_ETH_LANES_4,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_400G_4LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_400G,\n+\t\t\t\t\tRTE_ETH_LANES_4,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_10G_4LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_10G,\n+\t\t\t\t\tRTE_ETH_LANES_4,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_50G_2LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_50G,\n+\t\t\t\t\tRTE_ETH_LANES_2,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_100G_2LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_100G,\n+\t\t\t\t\tRTE_ETH_LANES_2,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_100G_4LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_100G,\n+\t\t\t\t\tRTE_ETH_LANES_4,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_200G_2LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_200G,\n+\t\t\t\t\tRTE_ETH_LANES_2,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t},\n+\t\t{\n+\t\t\tRTE_ETH_LINK_SPEED_400G_8LANES,\n+\t\t\t\t{\n+\t\t\t\t\tRTE_ETH_SPEED_NUM_400G,\n+\t\t\t\t\tRTE_ETH_LANES_8,\n+\t\t\t\t\tRTE_ETH_LINK_FULL_DUPLEX\n+\t\t\t\t}\n+\t\t}\n+\t};\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < RTE_DIM(speed_capa_info_map); i++)\n+\t\tif (link_speed == speed_capa_info_map[i].speed_capa) {\n+\t\t\tcapa_info->speed = speed_capa_info_map[i].capa_info.speed;\n+\t\t\tcapa_info->lanes = speed_capa_info_map[i].capa_info.lanes;\n+\t\t\tcapa_info->duplex = speed_capa_info_map[i].capa_info.duplex;\n+\t\t\treturn 0;\n+\t\t}\n+\n+\treturn -EINVAL;\n+}\n+\n const char *\n rte_eth_dev_tx_offload_name(uint64_t offload)\n {\n@@ -3111,8 +3358,9 @@ rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link)\n \tif (eth_link->link_status == RTE_ETH_LINK_DOWN)\n \t\tret = snprintf(str, len, \"Link down\");\n \telse\n-\t\tret = snprintf(str, len, \"Link up at %s %s %s\",\n+\t\tret = snprintf(str, len, \"Link up at %s %ulanes %s %s\",\n \t\t\trte_eth_link_speed_to_str(eth_link->link_speed),\n+\t\t\teth_link->link_lanes,\n \t\t\t(eth_link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ?\n \t\t\t\"FDX\" : \"HDX\",\n \t\t\t(eth_link->link_autoneg == RTE_ETH_LINK_AUTONEG) ?\ndiff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h\nindex 147257d6a2..3383ad8495 100644\n--- a/lib/ethdev/rte_ethdev.h\n+++ b/lib/ethdev/rte_ethdev.h\n@@ -288,24 +288,40 @@ struct rte_eth_stats {\n /**@{@name Link speed capabilities\n * Device supported speeds bitmap flags\n */\n-#define RTE_ETH_LINK_SPEED_AUTONEG 0 /**< Autonegotiate (all speeds) */\n-#define RTE_ETH_LINK_SPEED_FIXED RTE_BIT32(0) /**< Disable autoneg (fixed speed) */\n-#define RTE_ETH_LINK_SPEED_10M_HD RTE_BIT32(1) /**< 10 Mbps half-duplex */\n-#define RTE_ETH_LINK_SPEED_10M RTE_BIT32(2) /**< 10 Mbps full-duplex */\n-#define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3) /**< 100 Mbps half-duplex */\n-#define RTE_ETH_LINK_SPEED_100M RTE_BIT32(4) /**< 100 Mbps full-duplex */\n-#define RTE_ETH_LINK_SPEED_1G RTE_BIT32(5) /**< 1 Gbps */\n-#define RTE_ETH_LINK_SPEED_2_5G RTE_BIT32(6) /**< 2.5 Gbps */\n-#define RTE_ETH_LINK_SPEED_5G RTE_BIT32(7) /**< 5 Gbps */\n-#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */\n-#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps */\n-#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */\n-#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps */\n-#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */\n-#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps */\n-#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */\n-#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps */\n-#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps */\n+#define RTE_ETH_LINK_SPEED_AUTONEG 0 /**< Autonegotiate (all speeds) */\n+#define RTE_ETH_LINK_SPEED_FIXED RTE_BIT32(0) /**< Disable autoneg (fixed speed) */\n+#define RTE_ETH_LINK_SPEED_10M_HD RTE_BIT32(1) /**< 10 Mbps half-duplex */\n+#define RTE_ETH_LINK_SPEED_10M RTE_BIT32(2) /**< 10 Mbps full-duplex */\n+#define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3) /**< 100 Mbps half-duplex */\n+#define RTE_ETH_LINK_SPEED_100M RTE_BIT32(4) /**< 100 Mbps full-duplex */\n+#define RTE_ETH_LINK_SPEED_1G RTE_BIT32(5) /**< 1 Gbps */\n+#define RTE_ETH_LINK_SPEED_2_5G RTE_BIT32(6) /**< 2.5 Gbps */\n+#define RTE_ETH_LINK_SPEED_5G RTE_BIT32(7) /**< 5 Gbps */\n+#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */\n+#define RTE_ETH_LINK_SPEED_20G_2LANES RTE_BIT32(9) /**< 20 Gbps 2lanes */\n+#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */\n+#define RTE_ETH_LINK_SPEED_40G_4LANES RTE_BIT32(11) /**< 40 Gbps 4lanes */\n+#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */\n+#define RTE_ETH_LINK_SPEED_56G_4LANES RTE_BIT32(13) /**< 56 Gbps 4lanes */\n+#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */\n+#define RTE_ETH_LINK_SPEED_200G_4LANES RTE_BIT32(15) /**< 200 Gbps 4lanes */\n+#define RTE_ETH_LINK_SPEED_400G_4LANES RTE_BIT32(16) /**< 400 Gbps 4lanes */\n+#define RTE_ETH_LINK_SPEED_10G_4LANES RTE_BIT32(17) /**< 10 Gbps 4lanes */\n+#define RTE_ETH_LINK_SPEED_50G_2LANES RTE_BIT32(18) /**< 50 Gbps 2 lanes */\n+#define RTE_ETH_LINK_SPEED_100G_2LANES RTE_BIT32(19) /**< 100 Gbps 2 lanes */\n+#define RTE_ETH_LINK_SPEED_100G_4LANES RTE_BIT32(20) /**< 100 Gbps 4lanes */\n+#define RTE_ETH_LINK_SPEED_200G_2LANES RTE_BIT32(21) /**< 200 Gbps 2lanes */\n+#define RTE_ETH_LINK_SPEED_400G_8LANES RTE_BIT32(22) /**< 400 Gbps 8lanes */\n+/**@}*/\n+\n+/**@{@name Link speed capabilities\n+ * Default lanes, use to compatible with earlier versions\n+ */\n+#define RTE_ETH_LINK_SPEED_20G\tRTE_ETH_LINK_SPEED_20G_2LANES\n+#define RTE_ETH_LINK_SPEED_40G\tRTE_ETH_LINK_SPEED_40G_4LANES\n+#define RTE_ETH_LINK_SPEED_56G\tRTE_ETH_LINK_SPEED_56G_4LANES\n+#define RTE_ETH_LINK_SPEED_200G\tRTE_ETH_LINK_SPEED_200G_4LANES\n+#define RTE_ETH_LINK_SPEED_400G\tRTE_ETH_LINK_SPEED_400G_4LANES\n /**@}*/\n \n /**@{@name Link speed\n@@ -329,6 +345,25 @@ struct rte_eth_stats {\n #define RTE_ETH_SPEED_NUM_UNKNOWN UINT32_MAX /**< Unknown */\n /**@}*/\n \n+/**@{@name Link lane number\n+ * Ethernet lane number\n+ */\n+#define RTE_ETH_LANES_UNKNOWN 0 /**< Unknown */\n+#define RTE_ETH_LANES_1 1 /**< 1 lanes */\n+#define RTE_ETH_LANES_2 2 /**< 2 lanes */\n+#define RTE_ETH_LANES_4 4 /**< 4 lanes */\n+#define RTE_ETH_LANES_8 8 /**< 8 lanes */\n+/**@}*/\n+\n+/**\n+ * A structure used to store information of link speed capability.\n+ */\n+struct rte_eth_speed_capa_info {\n+\tuint32_t speed; /**< RTE_ETH_SPEED_NUM_ */\n+\tuint8_t lanes; /**< RTE_ETH_LANES_ */\n+\tuint8_t duplex; /**< RTE_ETH_LANES_ */\n+};\n+\n /**\n * A structure used to retrieve link-level information of an Ethernet port.\n */\n@@ -338,6 +373,7 @@ struct __rte_aligned(8) rte_eth_link { /**< aligned for atomic64 read/write */\n \tuint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */\n \tuint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */\n \tuint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */\n+\tuint16_t link_lanes : 8; /**< RTE_ETH_LANES_ */\n };\n \n /**@{@name Link negotiation\n@@ -1641,6 +1677,13 @@ struct rte_eth_conf {\n #define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP RTE_BIT64(3)\n /** Device supports keeping shared flow objects across restart. */\n #define RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP RTE_BIT64(4)\n+/**\n+ * Device supports setting lanes. When the driver does not support setting lane,\n+ * the lane in the speed capability reported by the driver may be incorrect,\n+ * for example, if the driver reports that the 200G speed capability\n+ * (@see RTE_ETH_LINK_SPEED_200G), the number of used lanes may be 2 or 4.\n+ */\n+#define RTE_ETH_DEV_CAPA_SETTING_LANES RTE_BIT64(4)\n /**@}*/\n \n /*\n@@ -2301,12 +2344,30 @@ uint16_t rte_eth_dev_count_total(void);\n *\n * @param speed\n * Numerical speed value in Mbps\n+ * @param lanes\n+ * RTE_ETH_LANES_x\n * @param duplex\n * RTE_ETH_LINK_[HALF/FULL]_DUPLEX (only for 10/100M speeds)\n * @return\n * 0 if the speed cannot be mapped\n */\n-uint32_t rte_eth_speed_bitflag(uint32_t speed, int duplex);\n+uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex);\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Convert bitmap flag to the struct of link speed capability info\n+ *\n+ * @param link_speed\n+ * speed bitmap (RTE_ETH_LINK_SPEED_)\n+ * @return\n+ * - (0) if successful.\n+ * - (-EINVAL) if bad parameter.\n+ */\n+__rte_experimental\n+int rte_eth_speed_capa_to_info(uint32_t link_speed,\n+\t\t\t\tstruct rte_eth_speed_capa_info *capa_info);\n \n /**\n * Get RTE_ETH_RX_OFFLOAD_* flag name.\ndiff --git a/lib/ethdev/version.map b/lib/ethdev/version.map\nindex 79f6f5293b..0e9c560920 100644\n--- a/lib/ethdev/version.map\n+++ b/lib/ethdev/version.map\n@@ -169,6 +169,12 @@ DPDK_24 {\n \tlocal: *;\n };\n \n+DPDK_25 {\n+\tglobal:\n+\n+\trte_eth_speed_bitflag;\n+} DPDK_24;\n+\n EXPERIMENTAL {\n \tglobal:\n \n@@ -320,6 +326,7 @@ EXPERIMENTAL {\n \t# added in 24.03\n \t__rte_eth_trace_tx_queue_count;\n \trte_eth_find_rss_algo;\n+\trte_eth_speed_capa_to_info;\n \trte_flow_async_update_resized;\n \trte_flow_calc_encap_hash;\n \trte_flow_template_table_resizable;\n", "prefixes": [ "1/3" ] }