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GET /api/patches/137805/?format=api
{ "id": 137805, "url": "http://patches.dpdk.org/api/patches/137805/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240302135328.531940-6-mattias.ronnblom@ericsson.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240302135328.531940-6-mattias.ronnblom@ericsson.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240302135328.531940-6-mattias.ronnblom@ericsson.com", "date": "2024-03-02T13:53:26", "name": "[RFC,5/7] eal: add atomic bit operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "57a72174c7c6d1f6002ae678fe47187fd8b69d81", "submitter": { "id": 1077, "url": "http://patches.dpdk.org/api/people/1077/?format=api", "name": "Mattias Rönnblom", "email": "mattias.ronnblom@ericsson.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240302135328.531940-6-mattias.ronnblom@ericsson.com/mbox/", "series": [ { "id": 31345, "url": "http://patches.dpdk.org/api/series/31345/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31345", "date": "2024-03-02T13:53:21", "name": "Improve EAL bit operations API", "version": 1, "mbox": "http://patches.dpdk.org/series/31345/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137805/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/137805/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 320EA43C3A;\n\tSat, 2 Mar 2024 15:02:57 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 06B9242DDB;\n\tSat, 2 Mar 2024 15:02:24 +0100 (CET)", "from EUR05-VI1-obe.outbound.protection.outlook.com\n (mail-vi1eur05on2085.outbound.protection.outlook.com [40.107.21.85])\n by mails.dpdk.org (Postfix) with ESMTP id F015F42DB0\n for <dev@dpdk.org>; Sat, 2 Mar 2024 15:02:19 +0100 (CET)", "from AM6PR0502CA0048.eurprd05.prod.outlook.com\n (2603:10a6:20b:56::25) by DUZPR07MB9814.eurprd07.prod.outlook.com\n (2603:10a6:10:4dd::15) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.34; Sat, 2 Mar\n 2024 14:02:18 +0000", "from AM4PEPF00025F9B.EURPRD83.prod.outlook.com\n (2603:10a6:20b:56:cafe::8f) by AM6PR0502CA0048.outlook.office365.com\n (2603:10a6:20b:56::25) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.36 via Frontend\n Transport; Sat, 2 Mar 2024 14:02:18 +0000", "from oa.msg.ericsson.com (192.176.1.74) by\n AM4PEPF00025F9B.mail.protection.outlook.com (10.167.16.10) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7386.0 via Frontend Transport; Sat, 2 Mar 2024 14:02:17 +0000", "from seliicinfr00050.seli.gic.ericsson.se (153.88.142.248) by\n smtp-central.internal.ericsson.com (100.87.178.60) with Microsoft SMTP Server\n id 15.2.1258.12; Sat, 2 Mar 2024 15:02:16 +0100", "from breslau.. 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helo=oa.msg.ericsson.com; pr=C", "From": "=?utf-8?q?Mattias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "To": "<dev@dpdk.org>", "CC": "<hofors@lysator.liu.se>, Heng Wang <heng.wang@ericsson.com>, =?utf-8?q?M?=\n\t=?utf-8?q?attias_R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>", "Subject": "[RFC 5/7] eal: add atomic bit operations", "Date": "Sat, 2 Mar 2024 14:53:26 +0100", "Message-ID": "<20240302135328.531940-6-mattias.ronnblom@ericsson.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240302135328.531940-1-mattias.ronnblom@ericsson.com>", "References": "<20240302135328.531940-1-mattias.ronnblom@ericsson.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "AM4PEPF00025F9B:EE_|DUZPR07MB9814:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c67f2b62-0698-4682-e8bd-08dc3ac15ef2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n uZQNlMbRGF41+EGkY5J0JVdlhEX8EH8oz0GpYchZulm6M/p3x3xjtLItdzIXsnK6rCTglMidmJhIXCfGvahRu+qDaF5M2tHEvnPk1Wv/sIXmZwQS8FD9npHzn64YYM0ODp5puv1OwrUGR+2Tuar+XAP+zJoz3sV7mISz6fJyo8ajXgBuC7/3bOk+Yg0d+Vyd5GZCkwwdqcFW9E5M+ZwhUb8v/JkxlvgGbQfbyd9woTAIDTKBxY2VZh+qYoF+iLAL8FxFdY/ecIQ5Ro/y3SgOhuQJvN/A96g2zlcSQ3PwReEbliU/TJNpRUkzBekr/KMGfl+NkHFSq0C4nqyoSpeziQTQxrR3TFqn1aVLQPk4Xj1avHEsv/FhfCgeJ8X1iQREldFwDRQTz/hjuoVekcD9Kehr2a15xqFfCoEIQ0F4lsyR+HvCEkjl8ArfBePPh9T5JRT8J81Rn+tQFEjA5zmPOFZxoQ6u8kab10GeQzJzlXOFSe/6knkvA2CNwjV4sDtWeHCQzXVadGTPXEbUr3b8NNGgVAhA1s85263ocUnpB7q9R/5Tfm37ztzAAqB6mjAjbs+0E+hyCak2gNTl8y+3BV/eplsm1HiQ7BhI+RM1tRiOShmMLAPlECIzRJtjgJYkqlY7bavNIeD+N6kupzuUmmXvuI9QWlAidLTkj62kNijJR0VUrm8UHJwGY9N+IXvfWhqA739RY1AMSV5R/oI0Pj+MEDK2YvDbgCea2gD5wYU=", "X-Forefront-Antispam-Report": "CIP:192.176.1.74; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net;\n CAT:NONE; SFS:(13230031)(376005)(82310400014)(36860700004); DIR:OUT;\n SFP:1101;", "X-OriginatorOrg": "ericsson.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Mar 2024 14:02:17.5219 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c67f2b62-0698-4682-e8bd-08dc3ac15ef2", "X-MS-Exchange-CrossTenant-Id": "92e84ceb-fbfd-47ab-be52-080c6b87953f", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74];\n Helo=[oa.msg.ericsson.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM4PEPF00025F9B.EURPRD83.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DUZPR07MB9814", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add atomic bit test/set/clear/assign and test-and-set/clear functions.\n\nAll atomic bit functions allow (and indeed, require) the caller to\nspecify a memory order.\n\nSigned-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>\n---\n lib/eal/include/rte_bitops.h | 337 +++++++++++++++++++++++++++++++++++\n 1 file changed, 337 insertions(+)", "diff": "diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h\nindex 450334c751..7eb08bc768 100644\n--- a/lib/eal/include/rte_bitops.h\n+++ b/lib/eal/include/rte_bitops.h\n@@ -20,6 +20,7 @@\n #include <stdint.h>\n \n #include <rte_debug.h>\n+#include <rte_stdatomic.h>\n \n #ifdef __cplusplus\n extern \"C\" {\n@@ -706,6 +707,342 @@ __RTE_GEN_BIT_TEST(rte_bit_once_test64, 64, volatile)\n __RTE_GEN_BIT_SET(rte_bit_once_set64, 64, volatile)\n __RTE_GEN_BIT_CLEAR(rte_bit_once_clear64, 64, volatile)\n \n+/**\n+ * Test if a particular bit in a 32-bit word is set with a particular\n+ * memory order.\n+ *\n+ * Test a bit with the resulting memory load ordered as per the\n+ * specified memory order.\n+ *\n+ * @param addr\n+ * A pointer to the 32-bit word to query.\n+ * @param nr\n+ * The index of the bit (0-31).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit is set, and false otherwise.\n+ */\n+static inline bool\n+rte_bit_atomic_test32(const uint32_t *addr, unsigned int nr, int memory_order);\n+\n+/**\n+ * Atomically set bit in 32-bit word.\n+ *\n+ * Atomically bit specified by @c nr in the 32-bit word pointed to by\n+ * @c addr to '1', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 32-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-31).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+static inline void\n+rte_bit_atomic_set32(uint32_t *addr, unsigned int nr, int memory_order);\n+\n+/**\n+ * Atomically clear bit in 32-bit word.\n+ *\n+ * Atomically set bit specified by @c nr in the 32-bit word pointed to\n+ * by @c addr to '0', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 32-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-31).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+static inline void\n+rte_bit_atomic_clear32(uint32_t *addr, unsigned int nr, int memory_order);\n+\n+/**\n+ * Atomically assign a value to bit in a 32-bit word.\n+ *\n+ * Atomically set bit specified by @c nr in the 32-bit word pointed to\n+ * by @c addr to the value indicated by @c value, with the memory\n+ * ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 32-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-31).\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+static inline void\n+rte_bit_atomic_assign32(uint32_t *addr, unsigned int nr, bool value,\n+\t\t\tint memory_order);\n+\n+/*\n+ * Atomic test-and-assign is not considered useful-enough to document\n+ * and expose in the public API.\n+ */\n+static inline bool\n+__rte_bit_atomic_test_and_assign32(uint32_t *addr, unsigned int nr, bool value,\n+\t\t\t\t int memory_order);\n+\n+/**\n+ * Atomically test and set a bit in a 32-bit word.\n+ *\n+ * Atomically test and set bit specified by @c nr in the 32-bit word\n+ * pointed to by @c addr to the value indicated by @c value, with the\n+ * memory ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 32-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-31).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+static inline bool\n+rte_bit_atomic_test_and_set32(uint32_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign32(addr, nr, true, memory_order);\n+}\n+\n+/**\n+ * Atomically test and clear a bit in a 32-bit word.\n+ *\n+ * Atomically test and clear bit specified by @c nr in the 32-bit word\n+ * pointed to by @c addr to the value indicated by @c value, with the\n+ * memory ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 32-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-31).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+static inline bool\n+rte_bit_atomic_test_and_clear32(uint32_t *addr, unsigned int nr,\n+\t\t\t\tint memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign32(addr, nr, false, memory_order);\n+}\n+\n+/**\n+ * Test if a particular bit in a 32-bit word is set with a particular\n+ * memory order.\n+ *\n+ * Test a bit with the resulting memory load ordered as per the\n+ * specified memory order.\n+ *\n+ * @param addr\n+ * A pointer to the 32-bit word to query.\n+ * @param nr\n+ * The index of the bit (0-31).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit is set, and false otherwise.\n+ */\n+static inline bool\n+rte_bit_atomic_test64(const uint64_t *addr, unsigned int nr, int memory_order);\n+\n+/**\n+ * Atomically set bit in 64-bit word.\n+ *\n+ * Atomically bit specified by @c nr in the 64-bit word pointed to by\n+ * @c addr to '1', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 64-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-63).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+static inline void\n+rte_bit_atomic_set64(uint64_t *addr, unsigned int nr, int memory_order);\n+\n+/**\n+ * Atomically clear bit in 64-bit word.\n+ *\n+ * Atomically set bit specified by @c nr in the 64-bit word pointed to\n+ * by @c addr to '0', with the memory ordering as specified by @c\n+ * memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 64-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-63).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+static inline void\n+rte_bit_atomic_clear64(uint64_t *addr, unsigned int nr, int memory_order);\n+\n+/**\n+ * Atomically assign a value to bit in a 64-bit word.\n+ *\n+ * Atomically set bit specified by @c nr in the 64-bit word pointed to\n+ * by @c addr to the value indicated by @c value, with the memory\n+ * ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 64-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-63).\n+ * @param value\n+ * The new value of the bit - true for '1', or false for '0'.\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ */\n+static inline void\n+rte_bit_atomic_assign64(uint64_t *addr, unsigned int nr, bool value,\n+\t\t\tint memory_order);\n+\n+/*\n+ * Atomic test-and-assign is not considered useful-enough to document\n+ * and expose in the public API.\n+ */\n+static inline bool\n+__rte_bit_atomic_test_and_assign64(uint64_t *addr, unsigned int nr, bool value,\n+\t\t\t\t int memory_order);\n+/**\n+ * Atomically test and set a bit in a 64-bit word.\n+ *\n+ * Atomically test and set bit specified by @c nr in the 64-bit word\n+ * pointed to by @c addr to the value indicated by @c value, with the\n+ * memory ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 64-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-63).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+static inline bool\n+rte_bit_atomic_test_and_set64(uint64_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign64(addr, nr, true, memory_order);\n+}\n+\n+/**\n+ * Atomically test and clear a bit in a 64-bit word.\n+ *\n+ * Atomically test and clear bit specified by @c nr in the 64-bit word\n+ * pointed to by @c addr to the value indicated by @c value, with the\n+ * memory ordering as specified with @c memory_order.\n+ *\n+ * @param addr\n+ * A pointer to the 64-bit word to modify.\n+ * @param nr\n+ * The index of the bit (0-63).\n+ * @param memory_order\n+ * The memory order to use. See <rte_stdatomics.h> for details.\n+ * @return\n+ * Returns true if the bit was set, and false otherwise.\n+ */\n+static inline bool\n+rte_bit_atomic_test_and_clear64(uint64_t *addr, unsigned int nr,\n+\t\t\t int memory_order)\n+{\n+\treturn __rte_bit_atomic_test_and_assign64(addr, nr, false, memory_order);\n+}\n+\n+#ifndef RTE_ENABLE_STDATOMIC\n+\n+#define __RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\trte_bit_atomic_test ## size(const uint ## size ## _t *addr,\t\\\n+\t\t\t\t unsigned int nr, int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\treturn __atomic_load_n(addr, memory_order) & mask;\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\trte_bit_atomic_set ## size(uint ## size ## _t *addr,\t\t\\\n+\t\t\t\t unsigned int nr, int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\t__atomic_fetch_or(addr, mask, memory_order);\t\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\trte_bit_atomic_clear ## size(uint ## size ## _t *addr,\t\t\\\n+\t\t\t\t unsigned int nr, int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ## _t mask = (uint ## size ## _t)1 << nr;\t\\\n+\t\t__atomic_fetch_and(addr, ~mask, memory_order);\t\t\\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\t\t\\\n+\tstatic inline void\t\t\t\t\t\t\\\n+\trte_bit_atomic_assign ## size(uint ## size ## _t *addr,\t\t\\\n+\t\t\t\t unsigned int nr, bool value,\t\\\n+\t\t\t\t int memory_order)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tif (value)\t\t\t\t\t\t\\\n+\t\t\trte_bit_atomic_set ## size(addr, nr, memory_order); \\\n+\t\telse\t\t\t\t\t\t\t\\\n+\t\t\trte_bit_atomic_clear ## size(addr, nr, memory_order); \\\n+\t}\n+\n+#define __RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\t\t\t\\\n+\tstatic inline bool\t\t\t\t\t\t\\\n+\t__rte_bit_atomic_test_and_assign ## size(uint ## size ## _t *addr, \\\n+\t\t\t\t\t\t unsigned int nr,\t\\\n+\t\t\t\t\t\t bool value,\t\t\\\n+\t\t\t\t\t\t int memory_order)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\tRTE_ASSERT(nr < size);\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tuint ## size ## _t before;\t\t\t\t\\\n+\t\tuint ## size ## _t after;\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tbefore = __atomic_load_n(addr, __ATOMIC_RELAXED);\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\trte_bit_assign ## size(&before, nr, value);\t\\\n+\t\t} while(!__atomic_compare_exchange_n(addr, &before, after, \\\n+\t\t\t\t\t\t true, __ATOMIC_RELAXED, \\\n+\t\t\t\t\t\t memory_order));\t\\\n+\t\treturn rte_bit_test ## size(&before, nr);\t\t\\\n+\t}\n+\n+#else\n+#error \"C11 atomics (MSVC) not supported in this RFC version\"\n+#endif\n+\n+#define __RTE_GEN_BIT_ATOMIC_OPS(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_SET(size)\t\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_CLEAR(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_ASSIGN(size)\t\t\\\n+\t__RTE_GEN_BIT_ATOMIC_TEST_AND_ASSIGN(size)\n+\n+__RTE_GEN_BIT_ATOMIC_OPS(32)\n+__RTE_GEN_BIT_ATOMIC_OPS(64)\n+\n /*------------------------ 32-bit relaxed operations ------------------------*/\n \n /**\n", "prefixes": [ "RFC", "5/7" ] }