Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/137688/?format=api
{ "id": 137688, "url": "http://patches.dpdk.org/api/patches/137688/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240301162553.30523-7-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240301162553.30523-7-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240301162553.30523-7-rnagadheeraj@marvell.com", "date": "2024-03-01T16:25:52", "name": "[v4,6/7] compress/nitrox: support stateless request", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a22717f6acf0faef1bd2103e8c1ef80bd6512c15", "submitter": { "id": 1365, "url": "http://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240301162553.30523-7-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 31338, "url": "http://patches.dpdk.org/api/series/31338/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31338", "date": "2024-03-01T16:25:46", "name": "add Nitrox compress device support", "version": 1, "mbox": "http://patches.dpdk.org/series/31338/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137688/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137688/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7A3A743C0C;\n\tFri, 1 Mar 2024 17:26:54 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E61804325A;\n\tFri, 1 Mar 2024 17:26:22 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id C55FC402CD\n for <dev@dpdk.org>; Fri, 1 Mar 2024 17:26:21 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id\n 4219mtiX013854; Fri, 1 Mar 2024 08:26:21 -0800", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wkcq593ug-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Fri, 01 Mar 2024 08:26:20 -0800 (PST)", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1258.12; Fri, 1 Mar 2024 08:26:19 -0800", "from hyd1399.caveonetworks.com.com (10.69.176.80) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id\n 15.2.1258.12 via Frontend Transport; Fri, 1 Mar 2024 08:26:17 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=wJXZEJWRLWIBUtoMEQvFFWA+oDQA05ii+qV+YfHkTPM=; b=IKb\n T4sKM676s0q9Dq1zHzhaw2ZGu7kLsVSEqTBDk4Uo7ZaX4B0K3kMPGsI5Er3iV5dc\n 21UsCmcvzUA51bQ68WGqc4oaHcK0FcSG0RLs0zzTtTIl5ZtsQbkXk7rgmBvw/qn5\n hoQArde3TUiJdzD+9cjEgfc/CnOfG/ao0skT8twUjt85YPSaWTuJMe4ZuxaJFw8O\n WCTnr0eHwH7UOp9MR8tR+bjUAFE9K9VlCqo6B3r8Cyo12MYEcTT3/u6qYudR3J7p\n sA55Jl072Xcbx+B2/5QtvTcUDciBmxVYYPldky+F8SJSutAma/L5yvJZ90610Rj3\n 5c/cJG+Zgx9/ozZN0ow==", "From": "Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "To": "<gakhil@marvell.com>, <fanzhang.oss@gmail.com>, <ashishg@marvell.com>", "CC": "<dev@dpdk.org>, Nagadheeraj Rottela <rnagadheeraj@marvell.com>", "Subject": "[PATCH v4 6/7] compress/nitrox: support stateless request", "Date": "Fri, 1 Mar 2024 21:55:52 +0530", "Message-ID": "<20240301162553.30523-7-rnagadheeraj@marvell.com>", "X-Mailer": "git-send-email 2.42.0", "In-Reply-To": "<20240301162553.30523-1-rnagadheeraj@marvell.com>", "References": "<20240301162553.30523-1-rnagadheeraj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "boCgUsBIJpE4_j7o33OXrAyj0OxCcYT2", "X-Proofpoint-ORIG-GUID": "boCgUsBIJpE4_j7o33OXrAyj0OxCcYT2", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2024-03-01_17,2024-03-01_02,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Implement enqueue and dequeue burst operations\nfor stateless request support.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n drivers/compress/nitrox/meson.build | 1 +\n drivers/compress/nitrox/nitrox_comp.c | 91 ++-\n drivers/compress/nitrox/nitrox_comp_reqmgr.c | 792 +++++++++++++++++++\n drivers/compress/nitrox/nitrox_comp_reqmgr.h | 10 +\n 4 files changed, 885 insertions(+), 9 deletions(-)\n create mode 100644 drivers/compress/nitrox/nitrox_comp_reqmgr.c", "diff": "diff --git a/drivers/compress/nitrox/meson.build b/drivers/compress/nitrox/meson.build\nindex f137303689..2c35aba60b 100644\n--- a/drivers/compress/nitrox/meson.build\n+++ b/drivers/compress/nitrox/meson.build\n@@ -10,6 +10,7 @@ deps += ['common_nitrox', 'bus_pci', 'compressdev']\n \n sources += files(\n 'nitrox_comp.c',\n+\t'nitrox_comp_reqmgr.c',\n )\n \n includes += include_directories('../../common/nitrox')\ndiff --git a/drivers/compress/nitrox/nitrox_comp.c b/drivers/compress/nitrox/nitrox_comp.c\nindex 299cb8e783..0ea5ed43ed 100644\n--- a/drivers/compress/nitrox/nitrox_comp.c\n+++ b/drivers/compress/nitrox/nitrox_comp.c\n@@ -187,10 +187,17 @@ static int nitrox_comp_queue_pair_setup(struct rte_compressdev *dev,\n \tif (unlikely(err))\n \t\tgoto qp_setup_err;\n \n+\tqp->sr_mp = nitrox_comp_req_pool_create(dev, qp->count, qp_id,\n+\t\t\t\t\t\tsocket_id);\n+\tif (unlikely(!qp->sr_mp))\n+\t\tgoto req_pool_err;\n+\n \tdev->data->queue_pairs[qp_id] = qp;\n \tNITROX_LOG(DEBUG, \"queue %d setup done\\n\", qp_id);\n \treturn 0;\n \n+req_pool_err:\n+\tnitrox_qp_release(qp, ndev->bar_addr);\n qp_setup_err:\n \trte_free(qp);\n \treturn err;\n@@ -224,6 +231,7 @@ static int nitrox_comp_queue_pair_release(struct rte_compressdev *dev,\n \n \tdev->data->queue_pairs[qp_id] = NULL;\n \terr = nitrox_qp_release(qp, ndev->bar_addr);\n+\tnitrox_comp_req_pool_free(qp->sr_mp);\n \trte_free(qp);\n \tNITROX_LOG(DEBUG, \"queue %d release done\\n\", qp_id);\n \treturn err;\n@@ -349,24 +357,89 @@ static int nitrox_comp_private_xform_free(struct rte_compressdev *dev,\n \treturn 0;\n }\n \n-static uint16_t nitrox_comp_dev_enq_burst(void *qp,\n+static int nitrox_enq_single_op(struct nitrox_qp *qp, struct rte_comp_op *op)\n+{\n+\tstruct nitrox_softreq *sr;\n+\tint err;\n+\n+\tif (unlikely(rte_mempool_get(qp->sr_mp, (void **)&sr)))\n+\t\treturn -ENOMEM;\n+\n+\terr = nitrox_process_comp_req(op, sr);\n+\tif (unlikely(err)) {\n+\t\trte_mempool_put(qp->sr_mp, sr);\n+\t\treturn err;\n+\t}\n+\n+\tnitrox_qp_enqueue(qp, nitrox_comp_instr_addr(sr), sr);\n+\treturn 0;\n+}\n+\n+static uint16_t nitrox_comp_dev_enq_burst(void *queue_pair,\n \t\t\t\t\t struct rte_comp_op **ops,\n \t\t\t\t\t uint16_t nb_ops)\n {\n-\tRTE_SET_USED(qp);\n-\tRTE_SET_USED(ops);\n-\tRTE_SET_USED(nb_ops);\n+\tstruct nitrox_qp *qp = queue_pair;\n+\tuint16_t free_slots = 0;\n+\tuint16_t cnt = 0;\n+\tbool err = false;\n+\n+\tfree_slots = nitrox_qp_free_count(qp);\n+\tif (nb_ops > free_slots)\n+\t\tnb_ops = free_slots;\n+\n+\tfor (cnt = 0; cnt < nb_ops; cnt++) {\n+\t\tif (unlikely(nitrox_enq_single_op(qp, ops[cnt]))) {\n+\t\t\terr = true;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tnitrox_ring_dbell(qp, cnt);\n+\tqp->stats.enqueued_count += cnt;\n+\tif (unlikely(err))\n+\t\tqp->stats.enqueue_err_count++;\n+\n+\treturn cnt;\n+}\n+\n+static int nitrox_deq_single_op(struct nitrox_qp *qp,\n+\t\t\t\tstruct rte_comp_op **op_ptr)\n+{\n+\tstruct nitrox_softreq *sr;\n+\tint err;\n+\n+\tsr = nitrox_qp_get_softreq(qp);\n+\terr = nitrox_check_comp_req(sr, op_ptr);\n+\tif (err == -EAGAIN)\n+\t\treturn err;\n+\n+\tnitrox_qp_dequeue(qp);\n+\trte_mempool_put(qp->sr_mp, sr);\n+\tif (err == 0)\n+\t\tqp->stats.dequeued_count++;\n+\telse\n+\t\tqp->stats.dequeue_err_count++;\n+\n \treturn 0;\n }\n \n-static uint16_t nitrox_comp_dev_deq_burst(void *qp,\n+static uint16_t nitrox_comp_dev_deq_burst(void *queue_pair,\n \t\t\t\t\t struct rte_comp_op **ops,\n \t\t\t\t\t uint16_t nb_ops)\n {\n-\tRTE_SET_USED(qp);\n-\tRTE_SET_USED(ops);\n-\tRTE_SET_USED(nb_ops);\n-\treturn 0;\n+\tstruct nitrox_qp *qp = queue_pair;\n+\tuint16_t filled_slots = nitrox_qp_used_count(qp);\n+\tint cnt = 0;\n+\n+\tif (nb_ops > filled_slots)\n+\t\tnb_ops = filled_slots;\n+\n+\tfor (cnt = 0; cnt < nb_ops; cnt++)\n+\t\tif (nitrox_deq_single_op(qp, &ops[cnt]))\n+\t\t\tbreak;\n+\n+\treturn cnt;\n }\n \n static struct rte_compressdev_ops nitrox_compressdev_ops = {\ndiff --git a/drivers/compress/nitrox/nitrox_comp_reqmgr.c b/drivers/compress/nitrox/nitrox_comp_reqmgr.c\nnew file mode 100644\nindex 0000000000..5ad1a4439a\n--- /dev/null\n+++ b/drivers/compress/nitrox/nitrox_comp_reqmgr.c\n@@ -0,0 +1,792 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2024 Marvell.\n+ */\n+\n+#include <rte_compressdev_pmd.h>\n+#include <rte_errno.h>\n+#include <rte_malloc.h>\n+\n+#include \"nitrox_comp_reqmgr.h\"\n+#include \"nitrox_logs.h\"\n+#include \"rte_comp.h\"\n+\n+#define NITROX_ZIP_SGL_COUNT 16\n+#define NITROX_ZIP_MAX_ZPTRS 2048\n+#define NITROX_ZIP_MAX_DATASIZE ((1 << 24) - 1)\n+#define NITROX_ZIP_MAX_ONFSIZE 1024\n+#define CMD_TIMEOUT 2\n+\n+union nitrox_zip_instr_word0 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz0 : 8;\n+\t\tuint64_t tol : 24;\n+\t\tuint64_t raz1 : 5;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t raz2 : 1;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t raz3 : 3;\n+\t\tuint64_t ca : 1;\n+\t\tuint64_t sf : 1;\n+\t\tuint64_t ss : 2;\n+\t\tuint64_t cc : 2;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t bf : 1;\n+\t\tuint64_t co : 1;\n+\t\tuint64_t raz4 : 1;\n+\t\tuint64_t ds : 1;\n+\t\tuint64_t dg : 1;\n+\t\tuint64_t hg : 1;\n+#else\n+\t\tuint64_t hg : 1;\n+\t\tuint64_t dg : 1;\n+\t\tuint64_t ds : 1;\n+\t\tuint64_t raz4 : 1;\n+\t\tuint64_t co : 1;\n+\t\tuint64_t bf : 1;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t cc : 2;\n+\t\tuint64_t ss : 2;\n+\t\tuint64_t sf : 1;\n+\t\tuint64_t ca : 1;\n+\t\tuint64_t raz3 : 3;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t raz2 : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t raz1 : 5;\n+\t\tuint64_t tol : 24;\n+\t\tuint64_t raz0 : 8;\n+#endif\n+\n+\t};\n+};\n+\n+union nitrox_zip_instr_word1 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t hl : 16;\n+\t\tuint64_t raz0\t\t: 16;\n+\t\tuint64_t adlercrc32\t: 32;\n+#else\n+\t\tuint64_t adlercrc32 : 32;\n+\t\tuint64_t raz0 : 16;\n+\t\tuint64_t hl : 16;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_instr_word2 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz0 : 20;\n+\t\tuint64_t cptr : 44;\n+#else\n+\t\tuint64_t cptr : 44;\n+\t\tuint64_t raz0 : 20;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_instr_word3 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz0 : 4;\n+\t\tuint64_t hlen : 16;\n+\t\tuint64_t hptr : 44;\n+#else\n+\t\tuint64_t hptr : 44;\n+\t\tuint64_t hlen : 16;\n+\t\tuint64_t raz0 : 4;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_instr_word4 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz0 : 4;\n+\t\tuint64_t ilen : 16;\n+\t\tuint64_t iptr : 44;\n+#else\n+\t\tuint64_t iptr : 44;\n+\t\tuint64_t ilen : 16;\n+\t\tuint64_t raz0 : 4;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_instr_word5 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz0 : 4;\n+\t\tuint64_t olen : 16;\n+\t\tuint64_t optr : 44;\n+#else\n+\t\tuint64_t optr : 44;\n+\t\tuint64_t olen : 16;\n+\t\tuint64_t raz0 : 4;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_instr_word6 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz0 : 20;\n+\t\tuint64_t rptr : 44;\n+#else\n+\t\tuint64_t rptr : 44;\n+\t\tuint64_t raz0 : 20;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_instr_word7 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t grp : 3;\n+\t\tuint64_t raz0 : 41;\n+\t\tuint64_t addr_msb: 20;\n+#else\n+\t\tuint64_t addr_msb: 20;\n+\t\tuint64_t raz0 : 41;\n+\t\tuint64_t grp : 3;\n+#endif\n+\t};\n+};\n+\n+struct nitrox_zip_instr {\n+\tunion nitrox_zip_instr_word0 w0;\n+\tunion nitrox_zip_instr_word1 w1;\n+\tunion nitrox_zip_instr_word2 w2;\n+\tunion nitrox_zip_instr_word3 w3;\n+\tunion nitrox_zip_instr_word4 w4;\n+\tunion nitrox_zip_instr_word5 w5;\n+\tunion nitrox_zip_instr_word6 w6;\n+\tunion nitrox_zip_instr_word7 w7;\n+};\n+\n+union nitrox_zip_result_word0 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t crc32 : 32;\n+\t\tuint64_t adler32: 32;\n+#else\n+\t\tuint64_t adler32: 32;\n+\t\tuint64_t crc32 : 32;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_result_word1 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t tbyteswritten : 32;\n+\t\tuint64_t tbytesread : 32;\n+#else\n+\t\tuint64_t tbytesread : 32;\n+\t\tuint64_t tbyteswritten : 32;\n+#endif\n+\t};\n+};\n+\n+union nitrox_zip_result_word2 {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t tbits : 32;\n+\t\tuint64_t raz0 : 5;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t raz1 : 1;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t raz2 : 7;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t compcode: 8;\n+#else\n+\t\tuint64_t compcode: 8;\n+\t\tuint64_t ef : 1;\n+\t\tuint64_t raz2 : 7;\n+\t\tuint64_t exbits : 7;\n+\t\tuint64_t raz1 : 1;\n+\t\tuint64_t exn : 3;\n+\t\tuint64_t raz0 : 5;\n+\t\tuint64_t tbits : 32;\n+#endif\n+\t};\n+};\n+\n+struct nitrox_zip_result {\n+\tunion nitrox_zip_result_word0 w0;\n+\tunion nitrox_zip_result_word1 w1;\n+\tunion nitrox_zip_result_word2 w2;\n+};\n+\n+union nitrox_zip_zptr {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz0 : 3;\n+\t\tuint64_t le : 1;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t addr : 44;\n+#else\n+\t\tuint64_t addr : 44;\n+\t\tuint64_t length : 16;\n+\t\tuint64_t le : 1;\n+\t\tuint64_t raz0 : 3;\n+#endif\n+\t} s;\n+};\n+\n+struct nitrox_zip_iova_addr {\n+\tunion {\n+\t\tuint64_t u64;\n+\t\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\t\tuint64_t addr_msb: 20;\n+\t\t\tuint64_t addr\t: 44;\n+#else\n+\t\t\tuint64_t addr\t: 44;\n+\t\t\tuint64_t addr_msb: 20;\n+#endif\n+\t\t} zda;\n+\n+\t\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\t\tuint64_t addr_msb: 20;\n+\t\t\tuint64_t addr\t: 41;\n+\t\t\tuint64_t align_8bytes: 3;\n+#else\n+\t\t\tuint64_t align_8bytes: 3;\n+\t\t\tuint64_t addr\t: 41;\n+\t\t\tuint64_t addr_msb: 20;\n+#endif\n+\t\t} z8a;\n+\t};\n+};\n+\n+enum nitrox_zip_comp_code {\n+\tNITROX_CC_NOTDONE = 0,\n+\tNITROX_CC_SUCCESS = 1,\n+\tNITROX_CC_DTRUNC = 2,\n+\tNITROX_CC_STOP = 3,\n+\tNITROX_CC_ITRUNK = 4,\n+\tNITROX_CC_RBLOCK = 5,\n+\tNITROX_CC_NLEN = 6,\n+\tNITROX_CC_BADCODE = 7,\n+\tNITROX_CC_BADCODE2 = 8,\n+\tNITROX_CC_ZERO_LEN = 9,\n+\tNITROX_CC_PARITY = 10,\n+\tNITROX_CC_FATAL = 11,\n+\tNITROX_CC_TIMEOUT = 12,\n+\tNITROX_CC_NPCI_ERR = 13,\n+};\n+\n+struct nitrox_sgtable {\n+\tunion nitrox_zip_zptr *sgl;\n+\tuint64_t addr_msb;\n+\tuint32_t total_bytes;\n+\tuint16_t nb_sgls;\n+\tuint16_t filled_sgls;\n+};\n+\n+struct nitrox_softreq {\n+\tstruct nitrox_zip_instr instr;\n+\tstruct nitrox_zip_result zip_res __rte_aligned(8);\n+\tuint8_t decomp_threshold[NITROX_ZIP_MAX_ONFSIZE];\n+\tstruct rte_comp_op *op;\n+\tstruct nitrox_sgtable src;\n+\tstruct nitrox_sgtable dst;\n+\tstruct nitrox_comp_xform xform;\n+\tuint64_t timeout;\n+};\n+\n+static int create_sglist_from_mbuf(struct nitrox_sgtable *sgtbl,\n+\t\t\t\t struct rte_mbuf *mbuf, uint32_t off,\n+\t\t\t\t uint32_t datalen, uint8_t extra_segs,\n+\t\t\t\t int socket_id)\n+{\n+\tstruct rte_mbuf *m;\n+\tunion nitrox_zip_zptr *sgl;\n+\tstruct nitrox_zip_iova_addr zip_addr;\n+\tuint16_t nb_segs;\n+\tuint16_t i;\n+\tuint32_t mlen;\n+\n+\tif (unlikely(datalen > NITROX_ZIP_MAX_DATASIZE)) {\n+\t\tNITROX_LOG(ERR, \"Unsupported datalen %d, max supported %d\\n\",\n+\t\t\t datalen, NITROX_ZIP_MAX_DATASIZE);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tnb_segs = mbuf->nb_segs + extra_segs;\n+\tfor (m = mbuf; m && off > rte_pktmbuf_data_len(m); m = m->next) {\n+\t\toff -= rte_pktmbuf_data_len(m);\n+\t\tnb_segs--;\n+\t}\n+\n+\tif (unlikely(nb_segs > NITROX_ZIP_MAX_ZPTRS)) {\n+\t\tNITROX_LOG(ERR, \"Mbuf has more segments %d than supported\\n\",\n+\t\t\t nb_segs);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (unlikely(nb_segs > sgtbl->nb_sgls)) {\n+\t\tunion nitrox_zip_zptr *sgl;\n+\n+\t\tNITROX_LOG(INFO, \"Mbuf has more segs %d than allocated %d\\n\",\n+\t\t\t nb_segs, sgtbl->nb_sgls);\n+\t\tsgl = rte_realloc_socket(sgtbl->sgl,\n+\t\t\t\t\t sizeof(*sgtbl->sgl) * nb_segs,\n+\t\t\t\t\t 8, socket_id);\n+\t\tif (unlikely(!sgl)) {\n+\t\t\tNITROX_LOG(ERR, \"Failed to expand sglist memory\\n\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tsgtbl->sgl = sgl;\n+\t\tsgtbl->nb_sgls = nb_segs;\n+\t}\n+\n+\tsgtbl->filled_sgls = 0;\n+\tsgtbl->total_bytes = 0;\n+\tsgl = sgtbl->sgl;\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tmlen = rte_pktmbuf_data_len(m) - off;\n+\tif (datalen <= mlen)\n+\t\tmlen = datalen;\n+\n+\ti = 0;\n+\tzip_addr.u64 = rte_pktmbuf_iova_offset(m, off);\n+\tsgl[i].s.addr = zip_addr.zda.addr;\n+\tsgl[i].s.length = mlen;\n+\tsgl[i].s.le = 0;\n+\tsgtbl->total_bytes += mlen;\n+\tsgtbl->addr_msb = zip_addr.zda.addr_msb;\n+\tdatalen -= mlen;\n+\ti++;\n+\tfor (m = m->next; m && datalen; m = m->next) {\n+\t\tmlen = rte_pktmbuf_data_len(m) < datalen ?\n+\t\t\trte_pktmbuf_data_len(m) : datalen;\n+\t\tzip_addr.u64 = rte_pktmbuf_iova(m);\n+\t\tif (unlikely(zip_addr.zda.addr_msb != sgtbl->addr_msb)) {\n+\t\t\tNITROX_LOG(ERR, \"zip_ptrs have different msb addr\\n\");\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\n+\t\tsgl[i].s.addr = zip_addr.zda.addr;\n+\t\tsgl[i].s.length = mlen;\n+\t\tsgl[i].s.le = 0;\n+\t\tsgtbl->total_bytes += mlen;\n+\t\tdatalen -= mlen;\n+\t\ti++;\n+\t}\n+\n+\tsgtbl->filled_sgls = i;\n+\treturn 0;\n+}\n+\n+static int softreq_init(struct nitrox_softreq *sr)\n+{\n+\tstruct rte_mempool *mp;\n+\tint err;\n+\n+\tmp = rte_mempool_from_obj(sr);\n+\tif (unlikely(mp == NULL))\n+\t\treturn -EINVAL;\n+\n+\terr = create_sglist_from_mbuf(&sr->src, sr->op->m_src,\n+\t\t\t\t sr->op->src.offset,\n+\t\t\t\t sr->op->src.length, 0, mp->socket_id);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\terr = create_sglist_from_mbuf(&sr->dst, sr->op->m_dst,\n+\t\t\tsr->op->dst.offset,\n+\t\t\trte_pktmbuf_pkt_len(sr->op->m_dst) - sr->op->dst.offset,\n+\t\t\t(sr->xform.op == NITROX_COMP_OP_DECOMPRESS) ? 1 : 0,\n+\t\t\tmp->socket_id);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\tif (sr->xform.op == NITROX_COMP_OP_DECOMPRESS) {\n+\t\tstruct nitrox_zip_iova_addr zip_addr;\n+\t\tint i;\n+\n+\t\tzip_addr.u64 = rte_mempool_virt2iova(sr) +\n+\t\t\toffsetof(struct nitrox_softreq, decomp_threshold);\n+\t\ti = sr->dst.filled_sgls;\n+\t\tsr->dst.sgl[i].s.addr = zip_addr.zda.addr;\n+\t\tsr->dst.sgl[i].s.length = NITROX_ZIP_MAX_ONFSIZE;\n+\t\tsr->dst.sgl[i].s.le = 0;\n+\t\tsr->dst.total_bytes += NITROX_ZIP_MAX_ONFSIZE;\n+\t\tsr->dst.filled_sgls++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void nitrox_zip_instr_to_b64(struct nitrox_softreq *sr)\n+{\n+\tstruct nitrox_zip_instr *instr = &sr->instr;\n+\tint i;\n+\n+\tfor (i = 0; instr->w0.dg && (i < instr->w4.ilen); i++)\n+\t\tsr->src.sgl[i].u64 = rte_cpu_to_be_64(sr->src.sgl[i].u64);\n+\n+\tfor (i = 0; instr->w0.ds && (i < instr->w5.olen); i++)\n+\t\tsr->dst.sgl[i].u64 = rte_cpu_to_be_64(sr->dst.sgl[i].u64);\n+\n+\tinstr->w0.u64 = rte_cpu_to_be_64(instr->w0.u64);\n+\tinstr->w1.u64 = rte_cpu_to_be_64(instr->w1.u64);\n+\tinstr->w2.u64 = rte_cpu_to_be_64(instr->w2.u64);\n+\tinstr->w3.u64 = rte_cpu_to_be_64(instr->w3.u64);\n+\tinstr->w4.u64 = rte_cpu_to_be_64(instr->w4.u64);\n+\tinstr->w5.u64 = rte_cpu_to_be_64(instr->w5.u64);\n+\tinstr->w6.u64 = rte_cpu_to_be_64(instr->w6.u64);\n+\tinstr->w7.u64 = rte_cpu_to_be_64(instr->w7.u64);\n+}\n+\n+static int process_zip_stateless(struct nitrox_softreq *sr)\n+{\n+\tstruct nitrox_zip_instr *instr;\n+\tstruct nitrox_comp_xform *xform;\n+\tstruct nitrox_zip_iova_addr zip_addr;\n+\tuint64_t iptr_msb, optr_msb, rptr_msb;\n+\tint err;\n+\n+\txform = sr->op->private_xform;\n+\tif (unlikely(xform == NULL)) {\n+\t\tNITROX_LOG(ERR, \"Invalid stateless comp op\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (unlikely(xform->op == NITROX_COMP_OP_COMPRESS &&\n+\t\t sr->op->flush_flag != RTE_COMP_FLUSH_FULL &&\n+\t\t sr->op->flush_flag != RTE_COMP_FLUSH_FINAL)) {\n+\t\tNITROX_LOG(ERR, \"Invalid flush flag %d in stateless op\\n\",\n+\t\t\t sr->op->flush_flag);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsr->xform = *xform;\n+\terr = softreq_init(sr);\n+\tif (unlikely(err))\n+\t\treturn err;\n+\n+\tinstr = &sr->instr;\n+\tmemset(instr, 0, sizeof(*instr));\n+\t/* word 0 */\n+\tinstr->w0.tol = sr->dst.total_bytes;\n+\tinstr->w0.exn = 0;\n+\tinstr->w0.exbits = 0;\n+\tinstr->w0.ca = 0;\n+\tif (xform->op == NITROX_COMP_OP_DECOMPRESS ||\n+\t sr->op->flush_flag == RTE_COMP_FLUSH_FULL)\n+\t\tinstr->w0.sf = 1;\n+\telse\n+\t\tinstr->w0.sf = 0;\n+\n+\tinstr->w0.ss = xform->level;\n+\tinstr->w0.cc = xform->algo;\n+\tif (xform->op == NITROX_COMP_OP_COMPRESS &&\n+\t sr->op->flush_flag == RTE_COMP_FLUSH_FINAL)\n+\t\tinstr->w0.ef = 1;\n+\telse\n+\t\tinstr->w0.ef = 0;\n+\n+\tinstr->w0.bf = 1;\n+\tinstr->w0.co = xform->op;\n+\tif (sr->dst.filled_sgls > 1)\n+\t\tinstr->w0.ds = 1;\n+\telse\n+\t\tinstr->w0.ds = 0;\n+\n+\tif (sr->src.filled_sgls > 1)\n+\t\tinstr->w0.dg = 1;\n+\telse\n+\t\tinstr->w0.dg = 0;\n+\n+\tinstr->w0.hg = 0;\n+\n+\t/* word 1 */\n+\tinstr->w1.hl = 0;\n+\tif (sr->op->input_chksum != 0)\n+\t\tinstr->w1.adlercrc32 = sr->op->input_chksum;\n+\telse if (xform->chksum_type == NITROX_CHKSUM_TYPE_ADLER32)\n+\t\tinstr->w1.adlercrc32 = 1;\n+\telse if (xform->chksum_type == NITROX_CHKSUM_TYPE_CRC32)\n+\t\tinstr->w1.adlercrc32 = 0;\n+\n+\t/* word 2 */\n+\tinstr->w2.cptr = 0;\n+\n+\t/* word 3 */\n+\tinstr->w3.hlen = 0;\n+\tinstr->w3.hptr = 0;\n+\n+\t/* word 4 */\n+\tif (sr->src.filled_sgls == 1) {\n+\t\tinstr->w4.ilen = sr->src.sgl[0].s.length;\n+\t\tinstr->w4.iptr = sr->src.sgl[0].s.addr;\n+\t\tiptr_msb = sr->src.addr_msb;\n+\t} else {\n+\t\tzip_addr.u64 = rte_malloc_virt2iova(sr->src.sgl);\n+\t\tinstr->w4.ilen = sr->src.filled_sgls;\n+\t\tinstr->w4.iptr = zip_addr.zda.addr;\n+\t\tiptr_msb = zip_addr.zda.addr_msb;\n+\t}\n+\n+\t/* word 5 */\n+\tif (sr->dst.filled_sgls == 1) {\n+\t\tinstr->w5.olen = sr->dst.sgl[0].s.length;\n+\t\tinstr->w5.optr = sr->dst.sgl[0].s.addr;\n+\t\toptr_msb = sr->dst.addr_msb;\n+\t} else {\n+\t\tzip_addr.u64 = rte_malloc_virt2iova(sr->dst.sgl);\n+\t\tinstr->w5.olen = sr->dst.filled_sgls;\n+\t\tinstr->w5.optr = zip_addr.zda.addr;\n+\t\toptr_msb = zip_addr.zda.addr_msb;\n+\t}\n+\n+\t/* word 6 */\n+\tmemset(&sr->zip_res, 0, sizeof(sr->zip_res));\n+\tzip_addr.u64 = rte_mempool_virt2iova(sr) +\n+\t\toffsetof(struct nitrox_softreq, zip_res);\n+\tinstr->w6.rptr = zip_addr.zda.addr;\n+\trptr_msb = zip_addr.zda.addr_msb;\n+\n+\tif (iptr_msb != optr_msb || iptr_msb != rptr_msb) {\n+\t\tNITROX_LOG(ERR, \"addr_msb is not same for all addresses\\n\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/* word 7 */\n+\tinstr->w7.addr_msb = iptr_msb;\n+\tinstr->w7.grp = 0;\n+\n+\tnitrox_zip_instr_to_b64(sr);\n+\treturn 0;\n+}\n+\n+static int process_zip_request(struct nitrox_softreq *sr)\n+{\n+\tint err;\n+\n+\tswitch (sr->op->op_type) {\n+\tcase RTE_COMP_OP_STATELESS:\n+\t\terr = process_zip_stateless(sr);\n+\t\tbreak;\n+\tdefault:\n+\t\terr = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+nitrox_process_comp_req(struct rte_comp_op *op, struct nitrox_softreq *sr)\n+{\n+\tint err;\n+\n+\tsr->op = op;\n+\terr = process_zip_request(sr);\n+\tif (unlikely(err))\n+\t\tgoto err_exit;\n+\n+\tsr->timeout = rte_get_timer_cycles() + CMD_TIMEOUT * rte_get_timer_hz();\n+\treturn 0;\n+err_exit:\n+\tif (err == -ENOMEM)\n+\t\tsr->op->status = RTE_COMP_OP_STATUS_ERROR;\n+\telse\n+\t\tsr->op->status = RTE_COMP_OP_STATUS_INVALID_ARGS;\n+\n+\treturn err;\n+}\n+\n+static struct nitrox_zip_result zip_result_to_cpu64(struct nitrox_zip_result *r)\n+{\n+\tstruct nitrox_zip_result out_res;\n+\n+\tout_res.w2.u64 = rte_be_to_cpu_64(r->w2.u64);\n+\tout_res.w1.u64 = rte_be_to_cpu_64(r->w1.u64);\n+\tout_res.w0.u64 = rte_be_to_cpu_64(r->w0.u64);\n+\treturn out_res;\n+}\n+\n+int\n+nitrox_check_comp_req(struct nitrox_softreq *sr, struct rte_comp_op **op)\n+{\n+\tstruct nitrox_zip_result zip_res;\n+\tint output_unused_bytes;\n+\tint err = 0;\n+\n+\tzip_res = zip_result_to_cpu64(&sr->zip_res);\n+\tif (zip_res.w2.compcode == NITROX_CC_NOTDONE) {\n+\t\tif (rte_get_timer_cycles() >= sr->timeout) {\n+\t\t\tNITROX_LOG(ERR, \"Op timedout\\n\");\n+\t\t\tsr->op->status = RTE_COMP_OP_STATUS_ERROR;\n+\t\t\terr = -ETIMEDOUT;\n+\t\t\tgoto exit;\n+\t\t} else {\n+\t\t\treturn -EAGAIN;\n+\t\t}\n+\t}\n+\n+\tif (unlikely(zip_res.w2.compcode != NITROX_CC_SUCCESS)) {\n+\t\tstruct rte_comp_op *op = sr->op;\n+\n+\t\tNITROX_LOG(ERR, \"Op dequeue error 0x%x\\n\",\n+\t\t\t zip_res.w2.compcode);\n+\t\tif (zip_res.w2.compcode == NITROX_CC_STOP ||\n+\t\t zip_res.w2.compcode == NITROX_CC_DTRUNC)\n+\t\t\top->status = RTE_COMP_OP_STATUS_OUT_OF_SPACE_TERMINATED;\n+\t\telse\n+\t\t\top->status = RTE_COMP_OP_STATUS_ERROR;\n+\n+\t\top->consumed = 0;\n+\t\top->produced = 0;\n+\t\terr = -EFAULT;\n+\t\tgoto exit;\n+\t}\n+\n+\toutput_unused_bytes = sr->dst.total_bytes - zip_res.w1.tbyteswritten;\n+\tif (unlikely(sr->xform.op == NITROX_COMP_OP_DECOMPRESS &&\n+\t\t output_unused_bytes < NITROX_ZIP_MAX_ONFSIZE)) {\n+\t\tNITROX_LOG(ERR, \"TOL %d, Total bytes written %d\\n\",\n+\t\t\t sr->dst.total_bytes, zip_res.w1.tbyteswritten);\n+\t\tsr->op->status = RTE_COMP_OP_STATUS_OUT_OF_SPACE_TERMINATED;\n+\t\tsr->op->consumed = 0;\n+\t\tsr->op->produced = sr->dst.total_bytes - NITROX_ZIP_MAX_ONFSIZE;\n+\t\terr = -EIO;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (sr->xform.op == NITROX_COMP_OP_COMPRESS &&\n+\t sr->op->flush_flag == RTE_COMP_FLUSH_FINAL &&\n+\t zip_res.w2.exn) {\n+\t\tuint32_t datalen = zip_res.w1.tbyteswritten;\n+\t\tuint32_t off = sr->op->dst.offset;\n+\t\tstruct rte_mbuf *m = sr->op->m_dst;\n+\t\tuint32_t mlen;\n+\t\tuint8_t *last_byte;\n+\n+\t\tfor (; m && off > rte_pktmbuf_data_len(m); m = m->next)\n+\t\t\toff -= rte_pktmbuf_data_len(m);\n+\n+\t\tmlen = rte_pktmbuf_data_len(m) - off;\n+\t\tfor (; m && (datalen > mlen); m = m->next)\n+\t\t\tdatalen -= mlen;\n+\n+\t\tlast_byte = rte_pktmbuf_mtod_offset(m, uint8_t *, datalen - 1);\n+\t\t*last_byte = zip_res.w2.exbits & 0xFF;\n+\t}\n+\n+\tsr->op->consumed = zip_res.w1.tbytesread;\n+\tsr->op->produced = zip_res.w1.tbyteswritten;\n+\tif (sr->xform.chksum_type == NITROX_CHKSUM_TYPE_CRC32)\n+\t\tsr->op->output_chksum = zip_res.w0.crc32;\n+\telse if (sr->xform.chksum_type == NITROX_CHKSUM_TYPE_ADLER32)\n+\t\tsr->op->output_chksum = zip_res.w0.adler32;\n+\n+\tsr->op->status = RTE_COMP_OP_STATUS_SUCCESS;\n+\terr = 0;\n+exit:\n+\t*op = sr->op;\n+\treturn err;\n+}\n+\n+void *\n+nitrox_comp_instr_addr(struct nitrox_softreq *sr)\n+{\n+\treturn &sr->instr;\n+}\n+\n+static void req_pool_obj_free(struct rte_mempool *mp, void *opaque, void *obj,\n+\t\t\t unsigned int obj_idx)\n+{\n+\tstruct nitrox_softreq *sr;\n+\n+\tRTE_SET_USED(mp);\n+\tRTE_SET_USED(opaque);\n+\tRTE_SET_USED(obj_idx);\n+\tsr = obj;\n+\trte_free(sr->src.sgl);\n+\tsr->src.sgl = NULL;\n+\trte_free(sr->dst.sgl);\n+\tsr->dst.sgl = NULL;\n+}\n+\n+void\n+nitrox_comp_req_pool_free(struct rte_mempool *mp)\n+{\n+\trte_mempool_obj_iter(mp, req_pool_obj_free, NULL);\n+\trte_mempool_free(mp);\n+}\n+\n+static void req_pool_obj_init(struct rte_mempool *mp, void *arg, void *obj,\n+\t\t\t unsigned int obj_idx)\n+{\n+\tstruct nitrox_softreq *sr;\n+\tint *err = arg;\n+\n+\tRTE_SET_USED(mp);\n+\tRTE_SET_USED(obj_idx);\n+\tsr = obj;\n+\tsr->src.sgl = rte_zmalloc_socket(NULL,\n+\t\t\t\tsizeof(*sr->src.sgl) * NITROX_ZIP_SGL_COUNT,\n+\t\t\t\t8, mp->socket_id);\n+\tsr->dst.sgl = rte_zmalloc_socket(NULL,\n+\t\t\t\tsizeof(*sr->dst.sgl) * NITROX_ZIP_SGL_COUNT,\n+\t\t\t\t8, mp->socket_id);\n+\tif (sr->src.sgl == NULL || sr->dst.sgl == NULL) {\n+\t\tNITROX_LOG(ERR, \"Failed to allocate zip_sgl memory\\n\");\n+\t\t*err = -ENOMEM;\n+\t}\n+\n+\tsr->src.nb_sgls = NITROX_ZIP_SGL_COUNT;\n+\tsr->src.filled_sgls = 0;\n+\tsr->dst.nb_sgls = NITROX_ZIP_SGL_COUNT;\n+\tsr->dst.filled_sgls = 0;\n+}\n+\n+struct rte_mempool *\n+nitrox_comp_req_pool_create(struct rte_compressdev *dev, uint32_t nobjs,\n+\t\t\t uint16_t qp_id, int socket_id)\n+{\n+\tchar softreq_pool_name[RTE_RING_NAMESIZE];\n+\tstruct rte_mempool *mp;\n+\tint err = 0;\n+\n+\tsnprintf(softreq_pool_name, RTE_RING_NAMESIZE, \"%s_sr_%d\",\n+\t\t dev->data->name, qp_id);\n+\tmp = rte_mempool_create(softreq_pool_name,\n+\t\t\t\tRTE_ALIGN_MUL_CEIL(nobjs, 64),\n+\t\t\t\tsizeof(struct nitrox_softreq),\n+\t\t\t\t64, 0, NULL, NULL, req_pool_obj_init, &err,\n+\t\t\t\tsocket_id, 0);\n+\tif (unlikely(!mp))\n+\t\tNITROX_LOG(ERR, \"Failed to create req pool, qid %d, err %d\\n\",\n+\t\t\t qp_id, rte_errno);\n+\n+\tif (unlikely(err)) {\n+\t\tnitrox_comp_req_pool_free(mp);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn mp;\n+}\ndiff --git a/drivers/compress/nitrox/nitrox_comp_reqmgr.h b/drivers/compress/nitrox/nitrox_comp_reqmgr.h\nindex 14f35a1e5b..07c65f0d5e 100644\n--- a/drivers/compress/nitrox/nitrox_comp_reqmgr.h\n+++ b/drivers/compress/nitrox/nitrox_comp_reqmgr.h\n@@ -5,6 +5,8 @@\n #ifndef _NITROX_COMP_REQMGR_H_\n #define _NITROX_COMP_REQMGR_H_\n \n+struct nitrox_softreq;\n+\n enum nitrox_comp_op {\n \tNITROX_COMP_OP_DECOMPRESS,\n \tNITROX_COMP_OP_COMPRESS,\n@@ -37,4 +39,12 @@ struct nitrox_comp_xform {\n \tenum nitrox_chksum_type chksum_type;\n };\n \n+int nitrox_process_comp_req(struct rte_comp_op *op, struct nitrox_softreq *sr);\n+int nitrox_check_comp_req(struct nitrox_softreq *sr, struct rte_comp_op **op);\n+void *nitrox_comp_instr_addr(struct nitrox_softreq *sr);\n+struct rte_mempool *nitrox_comp_req_pool_create(struct rte_compressdev *cdev,\n+\t\t\t\t\t uint32_t nobjs, uint16_t qp_id,\n+\t\t\t\t\t int socket_id);\n+void nitrox_comp_req_pool_free(struct rte_mempool *mp);\n+\n #endif /* _NITROX_COMP_REQMGR_H_ */\n", "prefixes": [ "v4", "6/7" ] }