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GET /api/patches/137653/?format=api
{ "id": 137653, "url": "http://patches.dpdk.org/api/patches/137653/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240301072651.1597062-1-shunh@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240301072651.1597062-1-shunh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240301072651.1597062-1-shunh@nvidia.com", "date": "2024-03-01T07:26:51", "name": "[v1] net/mlx5: set correct priority for meter policy", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "68eb39603e159c47085c9fd030eed2ac82119e57", "submitter": { "id": 2212, "url": "http://patches.dpdk.org/api/people/2212/?format=api", "name": "Shun Hao", "email": "shunh@nvidia.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240301072651.1597062-1-shunh@nvidia.com/mbox/", "series": [ { "id": 31321, "url": "http://patches.dpdk.org/api/series/31321/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31321", "date": "2024-03-01T07:26:51", "name": "[v1] net/mlx5: set correct priority for meter policy", "version": 1, "mbox": "http://patches.dpdk.org/series/31321/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137653/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/137653/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 899B043BC0;\n\tFri, 1 Mar 2024 08:27:25 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 572554025C;\n\tFri, 1 Mar 2024 08:27:25 +0100 (CET)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1nam02on2078.outbound.protection.outlook.com [40.107.96.78])\n by mails.dpdk.org (Postfix) with ESMTP id C8017400D5;\n Fri, 1 Mar 2024 08:27:23 +0100 (CET)", "from DM6PR02CA0129.namprd02.prod.outlook.com (2603:10b6:5:1b4::31)\n by CYYPR12MB8853.namprd12.prod.outlook.com (2603:10b6:930:cb::7) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.34; 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helo=mail.nvidia.com; pr=C", "From": "Shun Hao <shunh@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>, <orika@nvidia.com>, \"Dariusz\n Sosnowski\" <dsosnowski@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>,\n \"Bing Zhao\" <bingz@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH v1] net/mlx5: set correct priority for meter policy", "Date": "Fri, 1 Mar 2024 09:26:51 +0200", "Message-ID": "<20240301072651.1597062-1-shunh@nvidia.com>", "X-Mailer": "git-send-email 2.20.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000EDD7:EE_|CYYPR12MB8853:EE_", "X-MS-Office365-Filtering-Correlation-Id": "290b6a17-365d-4632-e8c6-08dc39c10853", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n thFbS92gafdPtz1brl5E0JbG4YRVGTiEnzV+JZEUOfVEY2jtKKP438DVXC58QFe1wLRlqQDgG/BbkPULpa07ljdy9/3S3LFwoT6OnK1sumJ6tSsONCBrzjZRNqA+CT7xEJ7cOJlJ6e++/OprrSfJNz5BTQ7+aLpbULqbUkZfSgKR7niYxw6qdA6tpuAb3J/wdH/IipAeUf2cghKfiNDgfpF9thymQz4nwlgq3pXELvrmNUHlmJt7GjlCvaF3AedtxQkizGA6M58a110suKB3B27ocl/fCSw4GeTReGcQU1t3geJkp4motRhukhI0Cy8OIyEe5vdSKKxRi8Qqb0Ria4mSZc1IlHnI5rr2y3cItcMGr1hn4NAuDtmojrmRQ0A02F8sZ1rQg0S1YlofDfPlFfGtvTocw5stYUTFx5dx+X0zeoHea57UxST7xfTq8QveOYiAV3ki8WgCAEmIGl1BMOSgcIb21mSG3/KcyL6LHQAt9cDwHCkJE/FXH9cJCJ9HRfO2AuD1Hq0nDQhXjuD5gA8aXSbYQ1QWBZBoPlJYfD7nIJI+9BxVlFD1gQ7YW2Y9eGtrkEk9KJWjl08MhzMI4N9+04+NQ0WoGP6E38fMOM9c7NKb1vMGIu9WSTRmdMuH+HHLchqxus9vUyU+413dk5+LMNZn8bOyTJhShkWyK8pzd654h5uJqn3VPkMHYcInBScun0BkITAkVA/rnZ+W4tbzZT4e8kUOsILIwjDWqyUme5SwkYBbWBju6icDRdg6", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(82310400014)(36860700004); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Mar 2024 07:27:20.9705 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 290b6a17-365d-4632-e8c6-08dc39c10853", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000EDD7.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CYYPR12MB8853", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Currently a meter policy's flows are always using the same priority for\nall colors, so the red color flow might be before green/yellow ones.\nThis will impact the performance cause green/yellow packets will check\nred flow first and got miss, then match green/yellow flows, introducing\nmore hops.\n\nThis patch fixes this by giving the the same priority to flows for all\ncolors.\n\nFixes: 363db9b00f (\"net/mlx5: handle yellow case in default meter policy\")\nCC: stable@dpdk.org\n\nSigned-off-by: Shun Hao <shunh@nvidia.com>\nAcked-by: Bing Zhao <bingz@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 41 +++++++++++++++++++--------------\n 1 file changed, 24 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 18f09b22be..f1584ed6e0 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -17922,9 +17922,8 @@ __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,\n \t\t}\n \t}\n \ttbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);\n-\tif (priority < RTE_COLOR_RED)\n-\t\tflow_dv_match_meta_reg(matcher.mask.buf,\n-\t\t\t(enum modify_reg)color_reg_c_idx, color_mask, color_mask);\n+\tflow_dv_match_meta_reg(matcher.mask.buf,\n+\t\t(enum modify_reg)color_reg_c_idx, color_mask, color_mask);\n \tmatcher.priority = priority;\n \tmatcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,\n \t\t\t\t matcher.mask.size);\n@@ -17975,7 +17974,6 @@ __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,\n \tint i;\n \tint ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);\n \tstruct mlx5_sub_policy_color_rule *color_rule;\n-\tbool svport_match;\n \tstruct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};\n \n \tif (ret < 0)\n@@ -18011,10 +18009,9 @@ __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,\n \t\t/* No use. */\n \t\tattr.priority = i;\n \t\t/* Create matchers for colors. */\n-\t\tsvport_match = (i != RTE_COLOR_RED) ? match_src_port : false;\n \t\tif (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,\n \t\t\t\tMLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,\n-\t\t\t\t&attr, svport_match, NULL,\n+\t\t\t\t&attr, match_src_port, NULL,\n \t\t\t\t&color_rule->matcher, &flow_err)) {\n \t\t\tDRV_LOG(ERR, \"Failed to create color%u matcher.\", i);\n \t\t\tgoto err_exit;\n@@ -18024,7 +18021,7 @@ __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,\n \t\t\t\tcolor_reg_c_idx, (enum rte_color)i,\n \t\t\t\tcolor_rule->matcher,\n \t\t\t\tacts[i].actions_n, acts[i].dv_actions,\n-\t\t\t\tsvport_match, NULL, &color_rule->rule,\n+\t\t\t\tmatch_src_port, NULL, &color_rule->rule,\n \t\t\t\t&attr)) {\n \t\t\tDRV_LOG(ERR, \"Failed to create color%u rule.\", i);\n \t\t\tgoto err_exit;\n@@ -18907,7 +18904,7 @@ flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,\n \tstruct {\n \t\tstruct mlx5_flow_meter_policy *fm_policy;\n \t\tstruct mlx5_flow_meter_info *next_fm;\n-\t\tstruct mlx5_sub_policy_color_rule *tag_rule[MLX5_MTR_RTE_COLORS];\n+\t\tstruct mlx5_sub_policy_color_rule *tag_rule[RTE_COLORS];\n \t} fm_info[MLX5_MTR_CHAIN_MAX_NUM] = { {0} };\n \tuint32_t fm_cnt = 0;\n \tuint32_t i, j;\n@@ -18941,14 +18938,22 @@ flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,\n \t\tmtr_policy = fm_info[i].fm_policy;\n \t\trte_spinlock_lock(&mtr_policy->sl);\n \t\tsub_policy = mtr_policy->sub_policys[domain][0];\n-\t\tfor (j = 0; j < MLX5_MTR_RTE_COLORS; j++) {\n+\t\tfor (j = 0; j < RTE_COLORS; j++) {\n \t\t\tuint8_t act_n = 0;\n-\t\t\tstruct mlx5_flow_dv_modify_hdr_resource *modify_hdr;\n+\t\t\tstruct mlx5_flow_dv_modify_hdr_resource *modify_hdr = NULL;\n \t\t\tstruct mlx5_flow_dv_port_id_action_resource *port_action;\n+\t\t\tuint8_t fate_action;\n \n-\t\t\tif (mtr_policy->act_cnt[j].fate_action != MLX5_FLOW_FATE_MTR &&\n-\t\t\t mtr_policy->act_cnt[j].fate_action != MLX5_FLOW_FATE_PORT_ID)\n-\t\t\t\tcontinue;\n+\t\t\tif (j == RTE_COLOR_RED) {\n+\t\t\t\tfate_action = MLX5_FLOW_FATE_DROP;\n+\t\t\t} else {\n+\t\t\t\tfate_action = mtr_policy->act_cnt[j].fate_action;\n+\t\t\t\tmodify_hdr = mtr_policy->act_cnt[j].modify_hdr;\n+\t\t\t\tif (fate_action != MLX5_FLOW_FATE_MTR &&\n+\t\t\t\t fate_action != MLX5_FLOW_FATE_PORT_ID &&\n+\t\t\t\t fate_action != MLX5_FLOW_FATE_DROP)\n+\t\t\t\t\tcontinue;\n+\t\t\t}\n \t\t\tcolor_rule = mlx5_malloc(MLX5_MEM_ZERO,\n \t\t\t\t\t\t sizeof(struct mlx5_sub_policy_color_rule),\n \t\t\t\t\t\t 0, SOCKET_ID_ANY);\n@@ -18960,9 +18965,8 @@ flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,\n \t\t\t\tgoto err_exit;\n \t\t\t}\n \t\t\tcolor_rule->src_port = src_port;\n-\t\t\tmodify_hdr = mtr_policy->act_cnt[j].modify_hdr;\n \t\t\t/* Prepare to create color rule. */\n-\t\t\tif (mtr_policy->act_cnt[j].fate_action == MLX5_FLOW_FATE_MTR) {\n+\t\t\tif (fate_action == MLX5_FLOW_FATE_MTR) {\n \t\t\t\tnext_fm = fm_info[i].next_fm;\n \t\t\t\tif (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {\n \t\t\t\t\tmlx5_free(color_rule);\n@@ -18989,7 +18993,7 @@ flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,\n \t\t\t\t}\n \t\t\t\tacts.dv_actions[act_n++] = tbl_data->jump.action;\n \t\t\t\tacts.actions_n = act_n;\n-\t\t\t} else {\n+\t\t\t} else if (fate_action == MLX5_FLOW_FATE_PORT_ID) {\n \t\t\t\tport_action =\n \t\t\t\t\tmlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],\n \t\t\t\t\t\t mtr_policy->act_cnt[j].rix_port_id_action);\n@@ -19002,6 +19006,9 @@ flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,\n \t\t\t\t\tacts.dv_actions[act_n++] = modify_hdr->action;\n \t\t\t\tacts.dv_actions[act_n++] = port_action->action;\n \t\t\t\tacts.actions_n = act_n;\n+\t\t\t} else {\n+\t\t\t\tacts.dv_actions[act_n++] = mtr_policy->dr_drop_action[domain];\n+\t\t\t\tacts.actions_n = act_n;\n \t\t\t}\n \t\t\tfm_info[i].tag_rule[j] = color_rule;\n \t\t\tTAILQ_INSERT_TAIL(&sub_policy->color_rules[j], color_rule, next_port);\n@@ -19033,7 +19040,7 @@ flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,\n \t\tmtr_policy = fm_info[i].fm_policy;\n \t\trte_spinlock_lock(&mtr_policy->sl);\n \t\tsub_policy = mtr_policy->sub_policys[domain][0];\n-\t\tfor (j = 0; j < MLX5_MTR_RTE_COLORS; j++) {\n+\t\tfor (j = 0; j < RTE_COLORS; j++) {\n \t\t\tcolor_rule = fm_info[i].tag_rule[j];\n \t\t\tif (!color_rule)\n \t\t\t\tcontinue;\n", "prefixes": [ "v1" ] }