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GET /api/patches/137475/?format=api
{ "id": 137475, "url": "http://patches.dpdk.org/api/patches/137475/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240229115157.201671-7-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240229115157.201671-7-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240229115157.201671-7-dsosnowski@nvidia.com", "date": "2024-02-29T11:51:51", "name": "[v2,06/11] net/mlx5: remove flow pattern from job", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ecbd943e7cb4fe402b4f376d6e7e50ee90028cf2", "submitter": { "id": 2386, "url": "http://patches.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240229115157.201671-7-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 31292, "url": "http://patches.dpdk.org/api/series/31292/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31292", "date": "2024-02-29T11:51:45", "name": "net/mlx5: flow insertion performance improvements", "version": 2, "mbox": "http://patches.dpdk.org/series/31292/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137475/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137475/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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b=DLrwvNEpiXBjtHk841fIJgnz28e7Vz6JCinqkmz5SXwHJCTOKiJb7r95cPnhZxsSHEsfsh6SjLJossHU3e8zpbiEySVaTPppiTeOvR0Bmbu7rzyMCGDYjxco6ROSmaZIldNktx5OcoWNICfjMijVvASHI7CTewZjRHlSh1QLSJiP/4BJjQT3pXXCdCXmA1PpOTG61Z7+82KUhIy+qGbGk3ox08/JQmk3eB9TMmffbvepwrNGATiX+9llomI7iJG0J4AYefXAEpMlSg0UxWTD3rooSGPh7tvTvxFBlNeAnjM7b1YWSPhyeVwvZ61GqmeAQCXumEh/IuUejDE2dEj0Lg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, Raslan Darawsheh <rasland@nvidia.com>, Bing Zhao\n <bingz@nvidia.com>", "Subject": "[PATCH v2 06/11] net/mlx5: remove flow pattern from job", "Date": "Thu, 29 Feb 2024 12:51:51 +0100", "Message-ID": "<20240229115157.201671-7-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240229115157.201671-1-dsosnowski@nvidia.com>", "References": "<20240228170046.176600-1-dsosnowski@nvidia.com>\n <20240229115157.201671-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB51:EE_|CY5PR12MB6251:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f1588e6b-82ef-4f2c-3eda-08dc391cf1d4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", 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CAT:NONE;\n SFS:(13230031)(36860700004)(82310400014); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Feb 2024 11:52:45.6041 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f1588e6b-82ef-4f2c-3eda-08dc391cf1d4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL6PEPF0001AB51.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY5PR12MB6251", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "mlx5_hw_q_job struct held a reference to temporary flow rule pattern\nand contained temporary REPRESENTED_PORT and TAG items structs.\nThey are used whenever it is required to prepend a flow rule pattern,\nprovided by the application with one of such items.\nIf prepending is required, then flow rule pattern is copied over to\ntemporary buffer and a new item added internally in PMD.\nSuch constructed buffer is passed to the HWS layer when flow create\noperation is being enqueued.\nAfter operation is enqueued, temporary flow pattern can be safely\ndiscarded, so there is no need to store it during\nthe whole lifecycle of mlx5_hw_q_job.\n\nThis patch removes all references to flow rule pattern and items stored\ninside mlx5_hw_q_job and removes relevant allocations to reduce job\nmemory footprint.\nTemporary pattern and items stored per job are replaced with stack\nallocated ones, contained in mlx5_flow_hw_pattern_params struct.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 17 ++++-------\n drivers/net/mlx5/mlx5_flow.h | 10 +++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 51 ++++++++++++++-------------------\n 3 files changed, 37 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 42dc312a87..1ca6223f95 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -401,17 +401,12 @@ struct mlx5_hw_q_job {\n \t\tconst void *action; /* Indirect action attached to the job. */\n \t};\n \tvoid *user_data; /* Job user data. */\n-\tstruct rte_flow_item *items;\n-\tunion {\n-\t\tstruct {\n-\t\t\t/* User memory for query output */\n-\t\t\tvoid *user;\n-\t\t\t/* Data extracted from hardware */\n-\t\t\tvoid *hw;\n-\t\t} __rte_packed query;\n-\t\tstruct rte_flow_item_ethdev port_spec;\n-\t\tstruct rte_flow_item_tag tag_spec;\n-\t} __rte_packed;\n+\tstruct {\n+\t\t/* User memory for query output */\n+\t\tvoid *user;\n+\t\t/* Data extracted from hardware */\n+\t\tvoid *hw;\n+\t} query;\n \tstruct rte_flow_hw *upd_flow; /* Flow with updated values. */\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 9ed356e1c2..436d1391bc 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1316,6 +1316,16 @@ struct mlx5_flow_hw_action_params {\n \tuint8_t ipv6_push_data[MLX5_PUSH_MAX_LEN];\n };\n \n+/** Container for dynamically generated flow items used during flow rule creation. */\n+struct mlx5_flow_hw_pattern_params {\n+\t/** Array of dynamically generated flow items. */\n+\tstruct rte_flow_item items[MLX5_HW_MAX_ITEMS];\n+\t/** Temporary REPRESENTED_PORT item generated by PMD. */\n+\tstruct rte_flow_item_ethdev port_spec;\n+\t/** Temporary TAG item generated by PMD. */\n+\tstruct rte_flow_item_tag tag_spec;\n+};\n+\n /* rte flow action translate to DR action struct. */\n struct mlx5_action_construct_data {\n \tLIST_ENTRY(mlx5_action_construct_data) next;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex a87fe4d07a..ab67dc139e 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -3272,44 +3272,44 @@ flow_hw_get_rule_items(struct rte_eth_dev *dev,\n \t\t const struct rte_flow_template_table *table,\n \t\t const struct rte_flow_item items[],\n \t\t uint8_t pattern_template_index,\n-\t\t struct mlx5_hw_q_job *job)\n+\t\t struct mlx5_flow_hw_pattern_params *pp)\n {\n \tstruct rte_flow_pattern_template *pt = table->its[pattern_template_index];\n \n \t/* Only one implicit item can be added to flow rule pattern. */\n \tMLX5_ASSERT(!pt->implicit_port || !pt->implicit_tag);\n-\t/* At least one item was allocated in job descriptor for items. */\n+\t/* At least one item was allocated in pattern params for items. */\n \tMLX5_ASSERT(MLX5_HW_MAX_ITEMS >= 1);\n \tif (pt->implicit_port) {\n \t\tif (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {\n \t\t\trte_errno = ENOMEM;\n \t\t\treturn NULL;\n \t\t}\n-\t\t/* Set up represented port item in job descriptor. */\n-\t\tjob->port_spec = (struct rte_flow_item_ethdev){\n+\t\t/* Set up represented port item in pattern params. */\n+\t\tpp->port_spec = (struct rte_flow_item_ethdev){\n \t\t\t.port_id = dev->data->port_id,\n \t\t};\n-\t\tjob->items[0] = (struct rte_flow_item){\n+\t\tpp->items[0] = (struct rte_flow_item){\n \t\t\t.type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,\n-\t\t\t.spec = &job->port_spec,\n+\t\t\t.spec = &pp->port_spec,\n \t\t};\n-\t\trte_memcpy(&job->items[1], items, sizeof(*items) * pt->orig_item_nb);\n-\t\treturn job->items;\n+\t\trte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);\n+\t\treturn pp->items;\n \t} else if (pt->implicit_tag) {\n \t\tif (pt->orig_item_nb + 1 > MLX5_HW_MAX_ITEMS) {\n \t\t\trte_errno = ENOMEM;\n \t\t\treturn NULL;\n \t\t}\n-\t\t/* Set up tag item in job descriptor. */\n-\t\tjob->tag_spec = (struct rte_flow_item_tag){\n+\t\t/* Set up tag item in pattern params. */\n+\t\tpp->tag_spec = (struct rte_flow_item_tag){\n \t\t\t.data = flow_hw_tx_tag_regc_value(dev),\n \t\t};\n-\t\tjob->items[0] = (struct rte_flow_item){\n+\t\tpp->items[0] = (struct rte_flow_item){\n \t\t\t.type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,\n-\t\t\t.spec = &job->tag_spec,\n+\t\t\t.spec = &pp->tag_spec,\n \t\t};\n-\t\trte_memcpy(&job->items[1], items, sizeof(*items) * pt->orig_item_nb);\n-\t\treturn job->items;\n+\t\trte_memcpy(&pp->items[1], items, sizeof(*items) * pt->orig_item_nb);\n+\t\treturn pp->items;\n \t} else {\n \t\treturn items;\n \t}\n@@ -3364,6 +3364,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t};\n \tstruct mlx5dr_rule_action *rule_acts;\n \tstruct mlx5_flow_hw_action_params ap;\n+\tstruct mlx5_flow_hw_pattern_params pp;\n \tstruct rte_flow_hw *flow = NULL;\n \tstruct mlx5_hw_q_job *job = NULL;\n \tconst struct rte_flow_item *rule_items;\n@@ -3428,7 +3429,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\tgoto error;\n \t}\n \trule_items = flow_hw_get_rule_items(dev, table, items,\n-\t\t\t\t\t pattern_template_index, job);\n+\t\t\t\t\t pattern_template_index, &pp);\n \tif (!rule_items)\n \t\tgoto error;\n \tif (likely(!rte_flow_template_table_resizable(dev->data->port_id, &table->cfg.attr))) {\n@@ -10121,11 +10122,8 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\tgoto err;\n \t\t}\n \t\tmem_size += (sizeof(struct mlx5_hw_q_job *) +\n-\t\t\t sizeof(struct mlx5_hw_q_job) +\n-\t\t\t sizeof(struct rte_flow_item) *\n-\t\t\t MLX5_HW_MAX_ITEMS +\n-\t\t\t\tsizeof(struct rte_flow_hw)) *\n-\t\t\t _queue_attr[i]->size;\n+\t\t\t sizeof(struct mlx5_hw_q_job) +\n+\t\t\t sizeof(struct rte_flow_hw)) * _queue_attr[i]->size;\n \t}\n \tpriv->hw_q = mlx5_malloc(MLX5_MEM_ZERO, mem_size,\n \t\t\t\t 64, SOCKET_ID_ANY);\n@@ -10134,7 +10132,6 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\tgoto err;\n \t}\n \tfor (i = 0; i < nb_q_updated; i++) {\n-\t\tstruct rte_flow_item *items = NULL;\n \t\tstruct rte_flow_hw *upd_flow = NULL;\n \n \t\tpriv->hw_q[i].job_idx = _queue_attr[i]->size;\n@@ -10147,12 +10144,8 @@ flow_hw_configure(struct rte_eth_dev *dev,\n \t\t\t\t&job[_queue_attr[i - 1]->size - 1].upd_flow[1];\n \t\tjob = (struct mlx5_hw_q_job *)\n \t\t &priv->hw_q[i].job[_queue_attr[i]->size];\n-\t\titems = (struct rte_flow_item *)\n-\t\t\t &job[_queue_attr[i]->size];\n-\t\tupd_flow = (struct rte_flow_hw *)\n-\t\t\t&items[_queue_attr[i]->size * MLX5_HW_MAX_ITEMS];\n+\t\tupd_flow = (struct rte_flow_hw *)&job[_queue_attr[i]->size];\n \t\tfor (j = 0; j < _queue_attr[i]->size; j++) {\n-\t\t\tjob[j].items = &items[j * MLX5_HW_MAX_ITEMS];\n \t\t\tjob[j].upd_flow = &upd_flow[j];\n \t\t\tpriv->hw_q[i].job[j] = &job[j];\n \t\t}\n@@ -12329,14 +12322,12 @@ flow_hw_calc_table_hash(struct rte_eth_dev *dev,\n \t\t\t uint32_t *hash, struct rte_flow_error *error)\n {\n \tconst struct rte_flow_item *items;\n-\t/* Temp job to allow adding missing items */\n-\tstatic struct rte_flow_item tmp_items[MLX5_HW_MAX_ITEMS];\n-\tstatic struct mlx5_hw_q_job job = {.items = tmp_items};\n+\tstruct mlx5_flow_hw_pattern_params pp;\n \tint res;\n \n \titems = flow_hw_get_rule_items(dev, table, pattern,\n \t\t\t\t pattern_template_index,\n-\t\t\t\t &job);\n+\t\t\t\t &pp);\n \tres = mlx5dr_rule_hash_calculate(mlx5_table_matcher(table), items,\n \t\t\t\t\t pattern_template_index,\n \t\t\t\t\t MLX5DR_RULE_HASH_CALC_MODE_RAW,\n", "prefixes": [ "v2", "06/11" ] }