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GET /api/patches/137428/?format=api
{ "id": 137428, "url": "http://patches.dpdk.org/api/patches/137428/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20240228133312.474474-3-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240228133312.474474-3-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240228133312.474474-3-getelson@nvidia.com", "date": "2024-02-28T13:33:10", "name": "[v3,2/4] net/mlx5: fix parameters verification in HWS table create", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c9807b60015d9eae0d5d164f223d4b10fe98887c", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20240228133312.474474-3-getelson@nvidia.com/mbox/", "series": [ { "id": 31274, "url": "http://patches.dpdk.org/api/series/31274/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=31274", "date": "2024-02-28T13:33:09", "name": "net/mlx5: add support for flow table resizing", "version": 3, "mbox": "http://patches.dpdk.org/series/31274/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/137428/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/137428/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A335D43C27;\n\tWed, 28 Feb 2024 14:34:00 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9190E432A8;\n\tWed, 28 Feb 2024 14:34:00 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2068.outbound.protection.outlook.com [40.107.243.68])\n by mails.dpdk.org (Postfix) with ESMTP id EAC364329C;\n Wed, 28 Feb 2024 14:33:54 +0100 (CET)", "from CH2PR12CA0028.namprd12.prod.outlook.com (2603:10b6:610:57::38)\n by DS0PR12MB7582.namprd12.prod.outlook.com (2603:10b6:8:13c::18) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.36; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>,\n <stable@dpdk.org>, Dariusz Sosnowski <dsosnowski@nvidia.com>, \"Viacheslav\n Ovsiienko\" <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>, Rongwei Liu\n <rongweil@nvidia.com>", "Subject": "[PATCH v3 2/4] net/mlx5: fix parameters verification in HWS table\n create", "Date": "Wed, 28 Feb 2024 15:33:10 +0200", "Message-ID": "<20240228133312.474474-3-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240228133312.474474-1-getelson@nvidia.com>", "References": "<20240202115611.288892-2-getelson@nvidia.com>\n <20240228133312.474474-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH2PEPF0000009B:EE_|DS0PR12MB7582:EE_", "X-MS-Office365-Filtering-Correlation-Id": "44637361-da63-460d-c391-08dc3861e6f8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n UC1LfRU5Ygr0NnH8qEEHS8RzTUY8PtZr7JRCOb1mCoSfv9r3sVy7oJvnv91b/Vpw/uNpyR5K7hYZkJaKmLAU9XyLrbEEaWN/inwWo+R2DSRtOWXC0XX0GznwP+dIE7um3mzO3QcsO5hSS9pJRqUBQ19rvzBXzb2SpgSsn3W3KfXcfKS7BVfhndB72Fm/3gJwwZeBd3OR1dhkFqcR3ZmDFJE6wYwsYr+59ZaVZqXccC/mQh3wwHzVQHb200RQ9Rb+baD7LriVpdPPWbOayGfuS89gaiiJPGMhMzAhGnz4lEsdsAek8Um9a3Ux6fDs7MgwITqaX7I1dWWr9ColC/iJou0di9a0Ynj3Dh5Ty/mfxeb4b9kHDbaLl7kbCEDW4nVwYObEV5wSiM/jM0l+KPKWfmmCtS+2INJ1cHlwNwkSf4CJi1z/walBsYHLRHXbxj58nBH0+5UeEGSoos9VD3CEmR6CS3VUWj5qvy4D9WXg7bgn/P3tiOS4M0moIBDaqi/dNKa+/C/EyFY6isW0VPwSAdpWpIWH7TkorbjGgiJyU+2keq/k52w2pK/njOOwdUKNbzovfVCa8bImbkJ9PCx6xCbzZ/IALGe6E3Ye+YVwEwJJT6xgDiuf4CxDyxByoUnAjYqyrARovKIpk3Wqnw1o77Vi/gb5Qt062a7x442vpqQSIwgdIW8mX19JynuovplPNfACsn4oUsQ+h+hY+lBoc8UOZP2GvtWYZhqCyx1s7DBb1CkQfbsbx9zxANMWgz9F", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(82310400014)(36860700004); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Feb 2024 13:33:51.5469 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 44637361-da63-460d-c391-08dc3861e6f8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH2PEPF0000009B.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB7582", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Modified the conditionals in `flow_hw_table_create()` to use bitwise\nAND instead of equality checks when assessing\n`table_cfg->attr->specialize` bitmask.\nThis will allow for greater flexibility as the bitmask may encapsulate\nmultiple flags.\nThe patch maintains the previous behavior with single flag values,\nwhile providing support for multiple flags.\n\nFixes: 240b77cfcba5 (\"net/mlx5: enable hint in async flow table\")\n\nCc: stable@dpdk.org\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_hw.c | 23 +++++++++++++++++------\n 1 file changed, 17 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 783ad9e72a..5938d8b90c 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -4390,12 +4390,23 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \tmatcher_attr.rule.num_log = rte_log2_u32(nb_flows);\n \t/* Parse hints information. */\n \tif (attr->specialize) {\n-\t\tif (attr->specialize == RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)\n-\t\t\tmatcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_WIRE;\n-\t\telse if (attr->specialize == RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)\n-\t\t\tmatcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_VPORT;\n-\t\telse\n-\t\t\tDRV_LOG(INFO, \"Unsupported hint value %x\", attr->specialize);\n+\t\tuint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG |\n+\t\t\t RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG;\n+\n+\t\tif ((attr->specialize & val) == val) {\n+\t\t\tDRV_LOG(INFO, \"Invalid hint value %x\",\n+\t\t\t\tattr->specialize);\n+\t\t\trte_errno = EINVAL;\n+\t\t\tgoto it_error;\n+\t\t}\n+\t\tif (attr->specialize &\n+\t\t RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG)\n+\t\t\tmatcher_attr.optimize_flow_src =\n+\t\t\t\tMLX5DR_MATCHER_FLOW_SRC_WIRE;\n+\t\telse if (attr->specialize &\n+\t\t\t RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG)\n+\t\t\tmatcher_attr.optimize_flow_src =\n+\t\t\t\tMLX5DR_MATCHER_FLOW_SRC_VPORT;\n \t}\n \t/* Build the item template. */\n \tfor (i = 0; i < nb_item_templates; i++) {\n", "prefixes": [ "v3", "2/4" ] }